lsq_impl.hh (4985:9f577f468009) lsq_impl.hh (4986:b7c82ad6b3ef)
1/*
2 * Copyright (c) 2005-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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75 }
76 panic("O3CPU doesn't expect recvStatusChange callback!");
77}
78
79template <class Impl>
80bool
81LSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt)
82{
1/*
2 * Copyright (c) 2005-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 66 unchanged lines hidden (view full) ---

75 }
76 panic("O3CPU doesn't expect recvStatusChange callback!");
77}
78
79template <class Impl>
80bool
81LSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt)
82{
83 if (pkt->isError())
84 DPRINTF(LSQ, "Got error packet back for address: %#X\n", pkt->getAddr());
83 if (pkt->isResponse()) {
84 lsq->thread[pkt->req->getThreadNum()].completeDataAccess(pkt);
85 }
86 else {
87 // must be a snoop
88
89 // @TODO someday may need to process invalidations in LSQ here
90 // to provide stronger consistency model

--- 535 unchanged lines hidden --- 		85 if (pkt->isResponse()) {
86 lsq->thread[pkt->req->getThreadNum()].completeDataAccess(pkt);
87 }
88 else {
89 // must be a snoop
90
91 // @TODO someday may need to process invalidations in LSQ here
92 // to provide stronger consistency model

--- 535 unchanged lines hidden ---