lsq_impl.hh (4329:52057dbec096) lsq_impl.hh (4895:d36959284fbc)
1/*
2 * Copyright (c) 2005-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 70 unchanged lines hidden (view full) ---

79template <class Impl>
80bool
81LSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt)
82{
83 if (pkt->isResponse()) {
84 lsq->thread[pkt->req->getThreadNum()].completeDataAccess(pkt);
85 }
86 else {
1/*
2 * Copyright (c) 2005-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 70 unchanged lines hidden (view full) ---

79template <class Impl>
80bool
81LSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt)
82{
83 if (pkt->isResponse()) {
84 lsq->thread[pkt->req->getThreadNum()].completeDataAccess(pkt);
85 }
86 else {
87 //else it is a coherence request, maybe you need to do something
88 warn("Recieved a coherence request (Invalidate?), 03CPU doesn't"
89 "update LSQ for these\n");
87 // must be a snoop
88
89 // @TODO someday may need to process invalidations in LSQ here
90 // to provide stronger consistency model
90 }
91 return true;
92}
93
94template <class Impl>
95void
96LSQ<Impl>::DcachePort::recvRetry()
97{

--- 526 unchanged lines hidden --- 		91 }
92 return true;
93}
94
95template <class Impl>
96void
97LSQ<Impl>::DcachePort::recvRetry()
98{

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