lsq_impl.hh (14194:967b9c450b04) lsq_impl.hh (14297:b4519e586f5e)
1/*
2 * Copyright (c) 2011-2012, 2014, 2017-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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682 thread[tid].dumpInsts();
683 }
684}
685
686template<class Impl>
687Fault
688LSQ<Impl>::pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
689 unsigned int size, Addr addr, Request::Flags flags,
1/*
2 * Copyright (c) 2011-2012, 2014, 2017-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 673 unchanged lines hidden (view full) ---

682 thread[tid].dumpInsts();
683 }
684}
685
686template<class Impl>
687Fault
688LSQ<Impl>::pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
689 unsigned int size, Addr addr, Request::Flags flags,
690 uint64_t *res, AtomicOpFunctor *amo_op,
690 uint64_t *res, AtomicOpFunctorPtr amo_op,
691 const std::vector<bool>& byteEnable)
692{
693 // This comming request can be either load, store or atomic.
694 // Atomic request has a corresponding pointer to its atomic memory
695 // operation
696 bool isAtomic M5_VAR_USED = !isLoad && amo_op;
697
698 ThreadID tid = cpu->contextToThread(inst->contextId());

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712 req = inst->savedReq;
713 assert(req);
714 } else {
715 if (needs_burst) {
716 req = new SplitDataRequest(&thread[tid], inst, isLoad, addr,
717 size, flags, data, res);
718 } else {
719 req = new SingleDataRequest(&thread[tid], inst, isLoad, addr,
691 const std::vector<bool>& byteEnable)
692{
693 // This comming request can be either load, store or atomic.
694 // Atomic request has a corresponding pointer to its atomic memory
695 // operation
696 bool isAtomic M5_VAR_USED = !isLoad && amo_op;
697
698 ThreadID tid = cpu->contextToThread(inst->contextId());

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712 req = inst->savedReq;
713 assert(req);
714 } else {
715 if (needs_burst) {
716 req = new SplitDataRequest(&thread[tid], inst, isLoad, addr,
717 size, flags, data, res);
718 } else {
719 req = new SingleDataRequest(&thread[tid], inst, isLoad, addr,
720 size, flags, data, res, amo_op);
720 size, flags, data, res, std::move(amo_op));
721 }
722 assert(req);
723 if (!byteEnable.empty()) {
724 req->_byteEnable = byteEnable;
725 }
726 inst->setRequest();
727 req->taskId(cpu->taskId());
728

--- 467 unchanged lines hidden --- 		721 }
722 assert(req);
723 if (!byteEnable.empty()) {
724 req->_byteEnable = byteEnable;
725 }
726 inst->setRequest();
727 req->taskId(cpu->taskId());
728

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