lsq_impl.hh (14105:969b4e972b07) | lsq_impl.hh (14111:14c05f862590) |
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1/* 2 * Copyright (c) 2011-2012, 2014, 2017-2018 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 971 unchanged lines hidden (view full) --- 980} 981 982template<class Impl> 983bool 984LSQ<Impl>::SingleDataRequest::recvTimingResp(PacketPtr pkt) 985{ 986 assert(_numOutstandingPackets == 1); 987 auto state = dynamic_cast<LSQSenderState*>(pkt->senderState); | 1/* 2 * Copyright (c) 2011-2012, 2014, 2017-2018 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 971 unchanged lines hidden (view full) --- 980} 981 982template<class Impl> 983bool 984LSQ<Impl>::SingleDataRequest::recvTimingResp(PacketPtr pkt) 985{ 986 assert(_numOutstandingPackets == 1); 987 auto state = dynamic_cast<LSQSenderState*>(pkt->senderState); |
988 setState(State::Complete); | |
989 flags.set(Flag::Complete); 990 state->outstanding--; 991 assert(pkt == _packets.front()); 992 _port.completeDataAccess(pkt); 993 return true; 994} 995 996template<class Impl> 997bool 998LSQ<Impl>::SplitDataRequest::recvTimingResp(PacketPtr pkt) 999{ 1000 auto state = dynamic_cast<LSQSenderState*>(pkt->senderState); 1001 uint32_t pktIdx = 0; 1002 while (pktIdx < _packets.size() && pkt != _packets[pktIdx]) 1003 pktIdx++; 1004 assert(pktIdx < _packets.size()); 1005 numReceivedPackets++; 1006 state->outstanding--; 1007 if (numReceivedPackets == _packets.size()) { | 988 flags.set(Flag::Complete); 989 state->outstanding--; 990 assert(pkt == _packets.front()); 991 _port.completeDataAccess(pkt); 992 return true; 993} 994 995template<class Impl> 996bool 997LSQ<Impl>::SplitDataRequest::recvTimingResp(PacketPtr pkt) 998{ 999 auto state = dynamic_cast<LSQSenderState*>(pkt->senderState); 1000 uint32_t pktIdx = 0; 1001 while (pktIdx < _packets.size() && pkt != _packets[pktIdx]) 1002 pktIdx++; 1003 assert(pktIdx < _packets.size()); 1004 numReceivedPackets++; 1005 state->outstanding--; 1006 if (numReceivedPackets == _packets.size()) { |
1008 setState(State::Complete); | |
1009 flags.set(Flag::Complete); 1010 /* Assemble packets. */ 1011 PacketPtr resp = isLoad() 1012 ? Packet::createRead(mainReq) 1013 : Packet::createWrite(mainReq); 1014 if (isLoad()) 1015 resp->dataStatic(_inst->memData); 1016 else --- 153 unchanged lines hidden --- | 1007 flags.set(Flag::Complete); 1008 /* Assemble packets. */ 1009 PacketPtr resp = isLoad() 1010 ? Packet::createRead(mainReq) 1011 : Packet::createWrite(mainReq); 1012 if (isLoad()) 1013 resp->dataStatic(_inst->memData); 1014 else --- 153 unchanged lines hidden --- |