lsq_impl.hh (13688:5bb3bf2f2559) lsq_impl.hh (13710:5ba1d8066ef0)
1/*
2 * Copyright (c) 2011-2012, 2014, 2017-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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58
59using namespace std;
60
61template <class Impl>
62LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params)
63 : cpu(cpu_ptr), iewStage(iew_ptr),
64 _cacheBlocked(false),
65 cacheStorePorts(params->cacheStorePorts), usedStorePorts(0),
1/*
2 * Copyright (c) 2011-2012, 2014, 2017-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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58
59using namespace std;
60
61template <class Impl>
62LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params)
63 : cpu(cpu_ptr), iewStage(iew_ptr),
64 _cacheBlocked(false),
65 cacheStorePorts(params->cacheStorePorts), usedStorePorts(0),
66 cacheLoadPorts(params->cacheLoadPorts), usedLoadPorts(0),
66 lsqPolicy(params->smtLSQPolicy),
67 LQEntries(params->LQEntries),
68 SQEntries(params->SQEntries),
69 maxLQEntries(maxLSQAllocation(lsqPolicy, LQEntries, params->numThreads,
70 params->smtLSQThreshold)),
71 maxSQEntries(maxLSQAllocation(lsqPolicy, SQEntries, params->numThreads,
72 params->smtLSQThreshold)),
73 numThreads(params->numThreads)

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168 usedStorePorts = 0;
169 _cacheBlocked = false;
170
171 for (ThreadID tid = 0; tid < numThreads; tid++) {
172 thread[tid].takeOverFrom();
173 }
174}
175
67 lsqPolicy(params->smtLSQPolicy),
68 LQEntries(params->LQEntries),
69 SQEntries(params->SQEntries),
70 maxLQEntries(maxLSQAllocation(lsqPolicy, LQEntries, params->numThreads,
71 params->smtLSQThreshold)),
72 maxSQEntries(maxLSQAllocation(lsqPolicy, SQEntries, params->numThreads,
73 params->smtLSQThreshold)),
74 numThreads(params->numThreads)

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169 usedStorePorts = 0;
170 _cacheBlocked = false;
171
172 for (ThreadID tid = 0; tid < numThreads; tid++) {
173 thread[tid].takeOverFrom();
174 }
175}
176
177template <class Impl>
178void
179LSQ<Impl>::tick()
180{
181 // Re-issue loads which got blocked on the per-cycle load ports limit.
182 if (usedLoadPorts == cacheLoadPorts && !_cacheBlocked)
183 iewStage->cacheUnblocked();
184
185 usedLoadPorts = 0;
186 usedStorePorts = 0;
187}
188
176template<class Impl>
177bool
178LSQ<Impl>::cacheBlocked() const
179{
180 return _cacheBlocked;
181}
182
183template<class Impl>
184void
185LSQ<Impl>::cacheBlocked(bool v)
186{
187 _cacheBlocked = v;
188}
189
190template<class Impl>
191bool
189template<class Impl>
190bool
191LSQ<Impl>::cacheBlocked() const
192{
193 return _cacheBlocked;
194}
195
196template<class Impl>
197void
198LSQ<Impl>::cacheBlocked(bool v)
199{
200 _cacheBlocked = v;
201}
202
203template<class Impl>
204bool
192LSQ<Impl>::storePortAvailable() const
205LSQ<Impl>::cachePortAvailable(bool is_load) const
193{
206{
194 return usedStorePorts < cacheStorePorts;
207 bool ret;
208 if (is_load) {
209 ret = usedLoadPorts < cacheLoadPorts;
210 } else {
211 ret = usedStorePorts < cacheStorePorts;
212 }
213 return ret;
195}
196
197template<class Impl>
198void
214}
215
216template<class Impl>
217void
199LSQ<Impl>::storePortBusy()
218LSQ<Impl>::cachePortBusy(bool is_load)
200{
219{
201 usedStorePorts++;
202 assert(usedStorePorts <= cacheStorePorts);
220 assert(cachePortAvailable(is_load));
221 if (is_load) {
222 usedLoadPorts++;
223 } else {
224 usedStorePorts++;
225 }
203}
204
205template<class Impl>
206void
207LSQ<Impl>::insertLoad(const DynInstPtr &load_inst)
208{
209 ThreadID tid = load_inst->threadNumber;
210

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227
228template<class Impl>
229void
230LSQ<Impl>::insertLoad(const DynInstPtr &load_inst)
231{
232 ThreadID tid = load_inst->threadNumber;
233

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