lsq_impl.hh (13652:45d94ac03a27) lsq_impl.hh (13688:5bb3bf2f2559)
1/*
2 * Copyright (c) 2011-2012, 2014, 2017-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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680Fault
681LSQ<Impl>::pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
682 unsigned int size, Addr addr, Request::Flags flags,
683 uint64_t *res, AtomicOpFunctor *amo_op)
684{
685 // This comming request can be either load, store or atomic.
686 // Atomic request has a corresponding pointer to its atomic memory
687 // operation
1/*
2 * Copyright (c) 2011-2012, 2014, 2017-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 671 unchanged lines hidden (view full) ---

680Fault
681LSQ<Impl>::pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
682 unsigned int size, Addr addr, Request::Flags flags,
683 uint64_t *res, AtomicOpFunctor *amo_op)
684{
685 // This comming request can be either load, store or atomic.
686 // Atomic request has a corresponding pointer to its atomic memory
687 // operation
688 bool isAtomic = !isLoad && amo_op;
688 bool isAtomic M5_VAR_USED = !isLoad && amo_op;
689
690 ThreadID tid = cpu->contextToThread(inst->contextId());
691 auto cacheLineSize = cpu->cacheLineSize();
692 bool needs_burst = transferNeedsBurst(addr, size, cacheLineSize);
693 LSQRequest* req = nullptr;
694
695 // Atomic requests that access data across cache line boundary are
696 // currently not allowed since the cache does not guarantee corresponding

--- 416 unchanged lines hidden --- 		689
690 ThreadID tid = cpu->contextToThread(inst->contextId());
691 auto cacheLineSize = cpu->cacheLineSize();
692 bool needs_burst = transferNeedsBurst(addr, size, cacheLineSize);
693 LSQRequest* req = nullptr;
694
695 // Atomic requests that access data across cache line boundary are
696 // currently not allowed since the cache does not guarantee corresponding

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