1/* 2 * Copyright (c) 2005-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 49 unchanged lines hidden (view full) --- 58 59 panic("O3CPU doesn't expect recvStatusChange callback!"); 60} 61 62template <class Impl> 63bool 64LSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt) 65{ |
66 if (pkt->isResponse()) { 67 lsq->thread[pkt->req->getThreadNum()].completeDataAccess(pkt); 68 } 69 else { 70 //else it is a coherence request, maybe you need to do something 71 warn("Recieved a coherence request (Invalidate??), 03CPU doesn't" 72 "update LSQ for these\n"); 73 } |
74 return true; 75} 76 77template <class Impl> 78void 79LSQ<Impl>::DcachePort::recvRetry() 80{ 81 if (lsq->retryTid == -1) --- 519 unchanged lines hidden --- |