1/* 2 * Copyright (c) 2011-2012, 2014, 2017-2018 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 49 unchanged lines hidden (view full) --- 58 59using namespace std; 60 61template <class Impl> 62LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params) 63 : cpu(cpu_ptr), iewStage(iew_ptr), 64 _cacheBlocked(false), 65 cacheStorePorts(params->cacheStorePorts), usedStorePorts(0), |
66 cacheLoadPorts(params->cacheLoadPorts), usedLoadPorts(0), |
67 lsqPolicy(params->smtLSQPolicy), 68 LQEntries(params->LQEntries), 69 SQEntries(params->SQEntries), 70 maxLQEntries(maxLSQAllocation(lsqPolicy, LQEntries, params->numThreads, 71 params->smtLSQThreshold)), 72 maxSQEntries(maxLSQAllocation(lsqPolicy, SQEntries, params->numThreads, 73 params->smtLSQThreshold)), 74 numThreads(params->numThreads) --- 94 unchanged lines hidden (view full) --- 169 usedStorePorts = 0; 170 _cacheBlocked = false; 171 172 for (ThreadID tid = 0; tid < numThreads; tid++) { 173 thread[tid].takeOverFrom(); 174 } 175} 176 |
177template <class Impl> 178void 179LSQ<Impl>::tick() 180{ 181 // Re-issue loads which got blocked on the per-cycle load ports limit. 182 if (usedLoadPorts == cacheLoadPorts && !_cacheBlocked) 183 iewStage->cacheUnblocked(); 184 185 usedLoadPorts = 0; 186 usedStorePorts = 0; 187} 188 |
189template<class Impl> 190bool 191LSQ<Impl>::cacheBlocked() const 192{ 193 return _cacheBlocked; 194} 195 196template<class Impl> 197void 198LSQ<Impl>::cacheBlocked(bool v) 199{ 200 _cacheBlocked = v; 201} 202 203template<class Impl> 204bool |
205LSQ<Impl>::cachePortAvailable(bool is_load) const |
206{ |
207 bool ret; 208 if (is_load) { 209 ret = usedLoadPorts < cacheLoadPorts; 210 } else { 211 ret = usedStorePorts < cacheStorePorts; 212 } 213 return ret; |
214} 215 216template<class Impl> 217void |
218LSQ<Impl>::cachePortBusy(bool is_load) |
219{ |
220 assert(cachePortAvailable(is_load)); 221 if (is_load) { 222 usedLoadPorts++; 223 } else { 224 usedStorePorts++; 225 } |
226} 227 228template<class Impl> 229void 230LSQ<Impl>::insertLoad(const DynInstPtr &load_inst) 231{ 232 ThreadID tid = load_inst->threadNumber; 233 --- 902 unchanged lines hidden --- |