1/* |
2 * Copyright (c) 2011-2012, 2014 ARM Limited |
3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license --- 46 unchanged lines hidden (view full) --- 57 58using namespace std; 59 60template <class Impl> 61LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params) 62 : cpu(cpu_ptr), iewStage(iew_ptr), 63 LQEntries(params->LQEntries), 64 SQEntries(params->SQEntries), |
65 numThreads(params->numThreads) |
66{ 67 assert(numThreads > 0 && numThreads <= Impl::MaxThreads); 68 69 //**********************************************/ 70 //************ Handle SMT Parameters ***********/ 71 //**********************************************/ 72 std::string policy = params->smtLSQPolicy; 73 --- 95 unchanged lines hidden (view full) --- 169 drained = false; 170 } 171 172 if (!sqEmpty()) { 173 DPRINTF(Drain, "Not drained, SQ not empty.\n"); 174 drained = false; 175 } 176 |
177 return drained; 178} 179 180template <class Impl> 181void 182LSQ<Impl>::takeOverFrom() 183{ 184 for (ThreadID tid = 0; tid < numThreads; tid++) { --- 142 unchanged lines hidden (view full) --- 327 328 return false; 329} 330 331template <class Impl> 332void 333LSQ<Impl>::recvRetry() 334{ |
335 iewStage->cacheUnblocked(); 336 337 for (ThreadID tid : *activeThreads) { 338 thread[tid].recvRetry(); |
339 } |
340} 341 342template <class Impl> 343bool 344LSQ<Impl>::recvTimingResp(PacketPtr pkt) 345{ 346 if (pkt->isError()) 347 DPRINTF(LSQ, "Got error packet back for address: %#X\n", --- 330 unchanged lines hidden --- |