65a66
> cacheLoadPorts(params->cacheLoadPorts), usedLoadPorts(0),
175a177,188
> template <class Impl>
> void
> LSQ<Impl>::tick()
> {
> // Re-issue loads which got blocked on the per-cycle load ports limit.
> if (usedLoadPorts == cacheLoadPorts && !_cacheBlocked)
> iewStage->cacheUnblocked();
>
> usedLoadPorts = 0;
> usedStorePorts = 0;
> }
>
192c205
< LSQ<Impl>::storePortAvailable() const
---
> LSQ<Impl>::cachePortAvailable(bool is_load) const
194c207,213
< return usedStorePorts < cacheStorePorts;
---
> bool ret;
> if (is_load) {
> ret = usedLoadPorts < cacheLoadPorts;
> } else {
> ret = usedStorePorts < cacheStorePorts;
> }
> return ret;
199c218
< LSQ<Impl>::storePortBusy()
---
> LSQ<Impl>::cachePortBusy(bool is_load)
201,202c220,225
< usedStorePorts++;
< assert(usedStorePorts <= cacheStorePorts);
---
> assert(cachePortAvailable(is_load));
> if (is_load) {
> usedLoadPorts++;
> } else {
> usedStorePorts++;
> }