1/*
| 1/*
|
2 * Copyright (c) 2011-2012, 2014 ARM Limited
| 2 * Copyright (c) 2011-2012, 2014, 2017-2018 ARM Limited
|
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2005-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Korey Sewell
42 */
43
44#ifndef __CPU_O3_LSQ_IMPL_HH__
45#define __CPU_O3_LSQ_IMPL_HH__
46
47#include <algorithm>
48#include <list>
49#include <string>
50
51#include "base/logging.hh"
52#include "cpu/o3/lsq.hh"
53#include "debug/Drain.hh"
54#include "debug/Fetch.hh"
55#include "debug/LSQ.hh"
56#include "debug/Writeback.hh"
57#include "params/DerivO3CPU.hh"
58
59using namespace std;
60
61template <class Impl>
62LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params)
63 : cpu(cpu_ptr), iewStage(iew_ptr),
| 3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2005-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Korey Sewell
42 */
43
44#ifndef __CPU_O3_LSQ_IMPL_HH__
45#define __CPU_O3_LSQ_IMPL_HH__
46
47#include <algorithm>
48#include <list>
49#include <string>
50
51#include "base/logging.hh"
52#include "cpu/o3/lsq.hh"
53#include "debug/Drain.hh"
54#include "debug/Fetch.hh"
55#include "debug/LSQ.hh"
56#include "debug/Writeback.hh"
57#include "params/DerivO3CPU.hh"
58
59using namespace std;
60
61template <class Impl>
62LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params)
63 : cpu(cpu_ptr), iewStage(iew_ptr),
|
| 64 _cacheBlocked(false),
65 cacheStorePorts(params->cacheStorePorts), usedStorePorts(0),
|
64 lsqPolicy(params->smtLSQPolicy),
65 LQEntries(params->LQEntries),
66 SQEntries(params->SQEntries),
67 maxLQEntries(maxLSQAllocation(lsqPolicy, LQEntries, params->numThreads,
68 params->smtLSQThreshold)),
69 maxSQEntries(maxLSQAllocation(lsqPolicy, SQEntries, params->numThreads,
70 params->smtLSQThreshold)),
71 numThreads(params->numThreads)
72{
73 assert(numThreads > 0 && numThreads <= Impl::MaxThreads);
74
75 //**********************************************/
76 //************ Handle SMT Parameters ***********/
77 //**********************************************/
78
| 66 lsqPolicy(params->smtLSQPolicy),
67 LQEntries(params->LQEntries),
68 SQEntries(params->SQEntries),
69 maxLQEntries(maxLSQAllocation(lsqPolicy, LQEntries, params->numThreads,
70 params->smtLSQThreshold)),
71 maxSQEntries(maxLSQAllocation(lsqPolicy, SQEntries, params->numThreads,
72 params->smtLSQThreshold)),
73 numThreads(params->numThreads)
74{
75 assert(numThreads > 0 && numThreads <= Impl::MaxThreads);
76
77 //**********************************************/
78 //************ Handle SMT Parameters ***********/
79 //**********************************************/
80
|
79 //Figure out fetch policy
80 if (lsqPolicy == SMTQueuePolicy::Dynamic) {
| 81 /* Run SMT olicy checks. */
82 if (lsqPolicy == SMTQueuePolicy::Dynamic) {
|
81 DPRINTF(LSQ, "LSQ sharing policy set to Dynamic\n");
82 } else if (lsqPolicy == SMTQueuePolicy::Partitioned) {
83 DPRINTF(Fetch, "LSQ sharing policy set to Partitioned: "
84 "%i entries per LQ | %i entries per SQ\n",
85 maxLQEntries,maxSQEntries);
86 } else if (lsqPolicy == SMTQueuePolicy::Threshold) {
87
| 83 DPRINTF(LSQ, "LSQ sharing policy set to Dynamic\n");
84 } else if (lsqPolicy == SMTQueuePolicy::Partitioned) {
85 DPRINTF(Fetch, "LSQ sharing policy set to Partitioned: "
86 "%i entries per LQ | %i entries per SQ\n",
87 maxLQEntries,maxSQEntries);
88 } else if (lsqPolicy == SMTQueuePolicy::Threshold) {
89
|
88 assert(params->smtLSQThreshold > LQEntries);
89 assert(params->smtLSQThreshold > SQEntries);
| 90 assert(params->smtLSQThreshold > params->LQEntries);
91 assert(params->smtLSQThreshold > params->SQEntries);
|
90
91 DPRINTF(LSQ, "LSQ sharing policy set to Threshold: "
92 "%i entries per LQ | %i entries per SQ\n",
93 maxLQEntries,maxSQEntries);
94 } else {
95 panic("Invalid LSQ sharing policy. Options are: Dynamic, "
96 "Partitioned, Threshold");
97 }
98
99 thread.reserve(numThreads);
100 for (ThreadID tid = 0; tid < numThreads; tid++) {
101 thread.emplace_back(maxLQEntries, maxSQEntries);
102 thread[tid].init(cpu, iew_ptr, params, this, tid);
103 thread[tid].setDcachePort(&cpu_ptr->getDataPort());
104 }
105}
106
107
108template<class Impl>
109std::string
110LSQ<Impl>::name() const
111{
112 return iewStage->name() + ".lsq";
113}
114
115template<class Impl>
116void
117LSQ<Impl>::regStats()
118{
119 //Initialize LSQs
120 for (ThreadID tid = 0; tid < numThreads; tid++) {
121 thread[tid].regStats();
122 }
123}
124
125template<class Impl>
126void
127LSQ<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
128{
129 activeThreads = at_ptr;
130 assert(activeThreads != 0);
131}
132
133template <class Impl>
134void
135LSQ<Impl>::drainSanityCheck() const
136{
137 assert(isDrained());
138
139 for (ThreadID tid = 0; tid < numThreads; tid++)
140 thread[tid].drainSanityCheck();
141}
142
143template <class Impl>
144bool
145LSQ<Impl>::isDrained() const
146{
147 bool drained(true);
148
149 if (!lqEmpty()) {
150 DPRINTF(Drain, "Not drained, LQ not empty.\n");
151 drained = false;
152 }
153
154 if (!sqEmpty()) {
155 DPRINTF(Drain, "Not drained, SQ not empty.\n");
156 drained = false;
157 }
158
159 return drained;
160}
161
162template <class Impl>
163void
164LSQ<Impl>::takeOverFrom()
165{
| 92
93 DPRINTF(LSQ, "LSQ sharing policy set to Threshold: "
94 "%i entries per LQ | %i entries per SQ\n",
95 maxLQEntries,maxSQEntries);
96 } else {
97 panic("Invalid LSQ sharing policy. Options are: Dynamic, "
98 "Partitioned, Threshold");
99 }
100
101 thread.reserve(numThreads);
102 for (ThreadID tid = 0; tid < numThreads; tid++) {
103 thread.emplace_back(maxLQEntries, maxSQEntries);
104 thread[tid].init(cpu, iew_ptr, params, this, tid);
105 thread[tid].setDcachePort(&cpu_ptr->getDataPort());
106 }
107}
108
109
110template<class Impl>
111std::string
112LSQ<Impl>::name() const
113{
114 return iewStage->name() + ".lsq";
115}
116
117template<class Impl>
118void
119LSQ<Impl>::regStats()
120{
121 //Initialize LSQs
122 for (ThreadID tid = 0; tid < numThreads; tid++) {
123 thread[tid].regStats();
124 }
125}
126
127template<class Impl>
128void
129LSQ<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
130{
131 activeThreads = at_ptr;
132 assert(activeThreads != 0);
133}
134
135template <class Impl>
136void
137LSQ<Impl>::drainSanityCheck() const
138{
139 assert(isDrained());
140
141 for (ThreadID tid = 0; tid < numThreads; tid++)
142 thread[tid].drainSanityCheck();
143}
144
145template <class Impl>
146bool
147LSQ<Impl>::isDrained() const
148{
149 bool drained(true);
150
151 if (!lqEmpty()) {
152 DPRINTF(Drain, "Not drained, LQ not empty.\n");
153 drained = false;
154 }
155
156 if (!sqEmpty()) {
157 DPRINTF(Drain, "Not drained, SQ not empty.\n");
158 drained = false;
159 }
160
161 return drained;
162}
163
164template <class Impl>
165void
166LSQ<Impl>::takeOverFrom()
167{
|
| 168 usedStorePorts = 0;
169 _cacheBlocked = false;
170
|
166 for (ThreadID tid = 0; tid < numThreads; tid++) {
167 thread[tid].takeOverFrom();
168 }
169}
170
| 171 for (ThreadID tid = 0; tid < numThreads; tid++) {
172 thread[tid].takeOverFrom();
173 }
174}
175
|
171template <class Impl>
172int
173LSQ<Impl>::entryAmount(ThreadID num_threads)
| 176template
177bool
178LSQ<Impl>::cacheBlocked() const
|
174{
| 179{
|
175 if (lsqPolicy == SMTQueuePolicy::Partitioned) {
176 return LQEntries / num_threads;
177 } else {
178 return 0;
179 }
| 180 return _cacheBlocked;
|
180}
181
| 181}
182
|
182template <class Impl>
183void
184LSQ<Impl>::resetEntries()
185{
186 if (lsqPolicy != SMTQueuePolicy::Dynamic || numThreads > 1) {
187 int active_threads = activeThreads->size();
188
189 int maxEntries;
190
191 if (lsqPolicy == SMTQueuePolicy::Partitioned) {
192 maxEntries = LQEntries / active_threads;
193 } else if (lsqPolicy == SMTQueuePolicy::Threshold &&
194 active_threads == 1) {
195 maxEntries = LQEntries;
196 } else {
197 maxEntries = LQEntries;
198 }
199
200 list<ThreadID>::iterator threads = activeThreads->begin();
201 list<ThreadID>::iterator end = activeThreads->end();
202
203 while (threads != end) {
204 ThreadID tid = *threads++;
205
206 resizeEntries(maxEntries, tid);
207 }
208 }
209}
210
| |
211template<class Impl>
212void
| 183template<class Impl>
184void
|
213LSQ<Impl>::removeEntries(ThreadID tid)
| 185LSQ<Impl>::cacheBlocked(bool v)
|
214{
| 186{
|
215 thread[tid].clearLQ();
216 thread[tid].clearSQ();
| 187 _cacheBlocked = v;
|
217}
218
219template<class Impl>
| 188}
189
190template<class Impl>
|
220void
221LSQ<Impl>::resizeEntries(unsigned size, ThreadID tid)
| 191bool
192LSQ<Impl>::storePortAvailable() const
|
222{
| 193{
|
223 thread[tid].resizeLQ(size);
224 thread[tid].resizeSQ(size);
| 194 return usedStorePorts < cacheStorePorts;
|
225}
226
227template<class Impl>
228void
| 195}
196
197template<class Impl>
198void
|
229LSQ<Impl>::tick()
| 199LSQ<Impl>::storePortBusy()
|
230{
| 200{
|
231 list<ThreadID>::iterator threads = activeThreads->begin();
232 list<ThreadID>::iterator end = activeThreads->end();
233
234 while (threads != end) {
235 ThreadID tid = *threads++;
236
237 thread[tid].tick();
238 }
| 201 usedStorePorts++;
202 assert(usedStorePorts <= cacheStorePorts);
|
239}
240
241template<class Impl>
242void
243LSQ<Impl>::insertLoad(const DynInstPtr &load_inst)
244{
245 ThreadID tid = load_inst->threadNumber;
246
247 thread[tid].insertLoad(load_inst);
248}
249
250template<class Impl>
251void
252LSQ<Impl>::insertStore(const DynInstPtr &store_inst)
253{
254 ThreadID tid = store_inst->threadNumber;
255
256 thread[tid].insertStore(store_inst);
257}
258
259template<class Impl>
260Fault
261LSQ<Impl>::executeLoad(const DynInstPtr &inst)
262{
263 ThreadID tid = inst->threadNumber;
264
265 return thread[tid].executeLoad(inst);
266}
267
268template<class Impl>
269Fault
270LSQ<Impl>::executeStore(const DynInstPtr &inst)
271{
272 ThreadID tid = inst->threadNumber;
273
274 return thread[tid].executeStore(inst);
275}
276
277template<class Impl>
278void
279LSQ<Impl>::writebackStores()
280{
281 list<ThreadID>::iterator threads = activeThreads->begin();
282 list<ThreadID>::iterator end = activeThreads->end();
283
284 while (threads != end) {
285 ThreadID tid = *threads++;
286
287 if (numStoresToWB(tid) > 0) {
288 DPRINTF(Writeback,"[tid:%i] Writing back stores. %i stores "
289 "available for Writeback.\n", tid, numStoresToWB(tid));
290 }
291
292 thread[tid].writebackStores();
293 }
294}
295
296template<class Impl>
297bool
298LSQ<Impl>::violation()
299{
300 /* Answers: Does Anybody Have a Violation?*/
301 list<ThreadID>::iterator threads = activeThreads->begin();
302 list<ThreadID>::iterator end = activeThreads->end();
303
304 while (threads != end) {
305 ThreadID tid = *threads++;
306
307 if (thread[tid].violation())
308 return true;
309 }
310
311 return false;
312}
313
314template <class Impl>
315void
316LSQ<Impl>::recvReqRetry()
317{
318 iewStage->cacheUnblocked();
| 203}
204
205template<class Impl>
206void
207LSQ<Impl>::insertLoad(const DynInstPtr &load_inst)
208{
209 ThreadID tid = load_inst->threadNumber;
210
211 thread[tid].insertLoad(load_inst);
212}
213
214template<class Impl>
215void
216LSQ<Impl>::insertStore(const DynInstPtr &store_inst)
217{
218 ThreadID tid = store_inst->threadNumber;
219
220 thread[tid].insertStore(store_inst);
221}
222
223template<class Impl>
224Fault
225LSQ<Impl>::executeLoad(const DynInstPtr &inst)
226{
227 ThreadID tid = inst->threadNumber;
228
229 return thread[tid].executeLoad(inst);
230}
231
232template<class Impl>
233Fault
234LSQ<Impl>::executeStore(const DynInstPtr &inst)
235{
236 ThreadID tid = inst->threadNumber;
237
238 return thread[tid].executeStore(inst);
239}
240
241template<class Impl>
242void
243LSQ<Impl>::writebackStores()
244{
245 list<ThreadID>::iterator threads = activeThreads->begin();
246 list<ThreadID>::iterator end = activeThreads->end();
247
248 while (threads != end) {
249 ThreadID tid = *threads++;
250
251 if (numStoresToWB(tid) > 0) {
252 DPRINTF(Writeback,"[tid:%i] Writing back stores. %i stores "
253 "available for Writeback.\n", tid, numStoresToWB(tid));
254 }
255
256 thread[tid].writebackStores();
257 }
258}
259
260template<class Impl>
261bool
262LSQ<Impl>::violation()
263{
264 /* Answers: Does Anybody Have a Violation?*/
265 list<ThreadID>::iterator threads = activeThreads->begin();
266 list<ThreadID>::iterator end = activeThreads->end();
267
268 while (threads != end) {
269 ThreadID tid = *threads++;
270
271 if (thread[tid].violation())
272 return true;
273 }
274
275 return false;
276}
277
278template <class Impl>
279void
280LSQ<Impl>::recvReqRetry()
281{
282 iewStage->cacheUnblocked();
|
| 283 cacheBlocked(false);
|
319
320 for (ThreadID tid : *activeThreads) {
321 thread[tid].recvRetry();
322 }
323}
324
325template <class Impl>
| 284
285 for (ThreadID tid : *activeThreads) {
286 thread[tid].recvRetry();
287 }
288}
289
290template <class Impl>
|
| 291void
292LSQ<Impl>::completeDataAccess(PacketPtr pkt)
293{
294 auto senderState = dynamic_cast<LSQSenderState*>(pkt->senderState);
295 thread[cpu->contextToThread(senderState->contextId())]
296 .completeDataAccess(pkt);
297}
298
299template <class Impl>
|
326bool
327LSQ<Impl>::recvTimingResp(PacketPtr pkt)
328{
329 if (pkt->isError())
330 DPRINTF(LSQ, "Got error packet back for address: %#X\n",
331 pkt->getAddr());
332
| 300bool
301LSQ<Impl>::recvTimingResp(PacketPtr pkt)
302{
303 if (pkt->isError())
304 DPRINTF(LSQ, "Got error packet back for address: %#X\n",
305 pkt->getAddr());
306
|
333 thread[cpu->contextToThread(pkt->req->contextId())]
334 .completeDataAccess(pkt);
| 307 auto senderState = dynamic_cast<LSQSenderState*>(pkt->senderState);
308 panic_if(!senderState, "Got packet back with unknown sender state\n");
|
335
| 309
|
| 310 thread[cpu->contextToThread(senderState->contextId())].recvTimingResp(pkt);
311
|
336 if (pkt->isInvalidate()) {
337 // This response also contains an invalidate; e.g. this can be the case
338 // if cmd is ReadRespWithInvalidate.
339 //
340 // The calling order between completeDataAccess and checkSnoop matters.
341 // By calling checkSnoop after completeDataAccess, we ensure that the
342 // fault set by checkSnoop is not lost. Calling writeback (more
343 // specifically inst->completeAcc) in completeDataAccess overwrites
344 // fault, and in case this instruction requires squashing (as
345 // determined by checkSnoop), the ReExec fault set by checkSnoop would
346 // be lost otherwise.
347
348 DPRINTF(LSQ, "received invalidation with response for addr:%#x\n",
349 pkt->getAddr());
350
351 for (ThreadID tid = 0; tid < numThreads; tid++) {
352 thread[tid].checkSnoop(pkt);
353 }
354 }
| 312 if (pkt->isInvalidate()) {
313 // This response also contains an invalidate; e.g. this can be the case
314 // if cmd is ReadRespWithInvalidate.
315 //
316 // The calling order between completeDataAccess and checkSnoop matters.
317 // By calling checkSnoop after completeDataAccess, we ensure that the
318 // fault set by checkSnoop is not lost. Calling writeback (more
319 // specifically inst->completeAcc) in completeDataAccess overwrites
320 // fault, and in case this instruction requires squashing (as
321 // determined by checkSnoop), the ReExec fault set by checkSnoop would
322 // be lost otherwise.
323
324 DPRINTF(LSQ, "received invalidation with response for addr:%#x\n",
325 pkt->getAddr());
326
327 for (ThreadID tid = 0; tid < numThreads; tid++) {
328 thread[tid].checkSnoop(pkt);
329 }
330 }
|
| 331 // Update the LSQRequest state (this may delete the request)
332 senderState->request()->packetReplied();
|
355
| 333
|
356 delete pkt;
| |
357 return true;
358}
359
360template <class Impl>
361void
362LSQ<Impl>::recvTimingSnoopReq(PacketPtr pkt)
363{
364 DPRINTF(LSQ, "received pkt for addr:%#x %s\n", pkt->getAddr(),
365 pkt->cmdString());
366
367 // must be a snoop
368 if (pkt->isInvalidate()) {
369 DPRINTF(LSQ, "received invalidation for addr:%#x\n",
370 pkt->getAddr());
371 for (ThreadID tid = 0; tid < numThreads; tid++) {
372 thread[tid].checkSnoop(pkt);
373 }
374 }
375}
376
377template<class Impl>
378int
379LSQ<Impl>::getCount()
380{
381 unsigned total = 0;
382
383 list<ThreadID>::iterator threads = activeThreads->begin();
384 list<ThreadID>::iterator end = activeThreads->end();
385
386 while (threads != end) {
387 ThreadID tid = *threads++;
388
389 total += getCount(tid);
390 }
391
392 return total;
393}
394
395template<class Impl>
396int
397LSQ<Impl>::numLoads()
398{
399 unsigned total = 0;
400
401 list<ThreadID>::iterator threads = activeThreads->begin();
402 list<ThreadID>::iterator end = activeThreads->end();
403
404 while (threads != end) {
405 ThreadID tid = *threads++;
406
407 total += numLoads(tid);
408 }
409
410 return total;
411}
412
413template<class Impl>
414int
415LSQ<Impl>::numStores()
416{
417 unsigned total = 0;
418
419 list<ThreadID>::iterator threads = activeThreads->begin();
420 list<ThreadID>::iterator end = activeThreads->end();
421
422 while (threads != end) {
423 ThreadID tid = *threads++;
424
425 total += thread[tid].numStores();
426 }
427
428 return total;
429}
430
431template<class Impl>
432unsigned
433LSQ<Impl>::numFreeLoadEntries()
434{
435 unsigned total = 0;
436
437 list<ThreadID>::iterator threads = activeThreads->begin();
438 list<ThreadID>::iterator end = activeThreads->end();
439
440 while (threads != end) {
441 ThreadID tid = *threads++;
442
443 total += thread[tid].numFreeLoadEntries();
444 }
445
446 return total;
447}
448
449template<class Impl>
450unsigned
451LSQ<Impl>::numFreeStoreEntries()
452{
453 unsigned total = 0;
454
455 list<ThreadID>::iterator threads = activeThreads->begin();
456 list<ThreadID>::iterator end = activeThreads->end();
457
458 while (threads != end) {
459 ThreadID tid = *threads++;
460
461 total += thread[tid].numFreeStoreEntries();
462 }
463
464 return total;
465}
466
467template<class Impl>
468unsigned
469LSQ<Impl>::numFreeLoadEntries(ThreadID tid)
470{
471 return thread[tid].numFreeLoadEntries();
472}
473
474template<class Impl>
475unsigned
476LSQ<Impl>::numFreeStoreEntries(ThreadID tid)
477{
478 return thread[tid].numFreeStoreEntries();
479}
480
481template<class Impl>
482bool
483LSQ<Impl>::isFull()
484{
485 list<ThreadID>::iterator threads = activeThreads->begin();
486 list<ThreadID>::iterator end = activeThreads->end();
487
488 while (threads != end) {
489 ThreadID tid = *threads++;
490
491 if (!(thread[tid].lqFull() || thread[tid].sqFull()))
492 return false;
493 }
494
495 return true;
496}
497
498template<class Impl>
499bool
500LSQ<Impl>::isFull(ThreadID tid)
501{
502 //@todo: Change to Calculate All Entries for
503 //Dynamic Policy
504 if (lsqPolicy == SMTQueuePolicy::Dynamic)
505 return isFull();
506 else
507 return thread[tid].lqFull() || thread[tid].sqFull();
508}
509
510template<class Impl>
511bool
512LSQ<Impl>::isEmpty() const
513{
514 return lqEmpty() && sqEmpty();
515}
516
517template<class Impl>
518bool
519LSQ<Impl>::lqEmpty() const
520{
521 list<ThreadID>::const_iterator threads = activeThreads->begin();
522 list<ThreadID>::const_iterator end = activeThreads->end();
523
524 while (threads != end) {
525 ThreadID tid = *threads++;
526
527 if (!thread[tid].lqEmpty())
528 return false;
529 }
530
531 return true;
532}
533
534template<class Impl>
535bool
536LSQ<Impl>::sqEmpty() const
537{
538 list<ThreadID>::const_iterator threads = activeThreads->begin();
539 list<ThreadID>::const_iterator end = activeThreads->end();
540
541 while (threads != end) {
542 ThreadID tid = *threads++;
543
544 if (!thread[tid].sqEmpty())
545 return false;
546 }
547
548 return true;
549}
550
551template<class Impl>
552bool
553LSQ<Impl>::lqFull()
554{
555 list<ThreadID>::iterator threads = activeThreads->begin();
556 list<ThreadID>::iterator end = activeThreads->end();
557
558 while (threads != end) {
559 ThreadID tid = *threads++;
560
561 if (!thread[tid].lqFull())
562 return false;
563 }
564
565 return true;
566}
567
568template<class Impl>
569bool
570LSQ<Impl>::lqFull(ThreadID tid)
571{
572 //@todo: Change to Calculate All Entries for
573 //Dynamic Policy
574 if (lsqPolicy == SMTQueuePolicy::Dynamic)
575 return lqFull();
576 else
577 return thread[tid].lqFull();
578}
579
580template<class Impl>
581bool
582LSQ<Impl>::sqFull()
583{
584 list<ThreadID>::iterator threads = activeThreads->begin();
585 list<ThreadID>::iterator end = activeThreads->end();
586
587 while (threads != end) {
588 ThreadID tid = *threads++;
589
590 if (!sqFull(tid))
591 return false;
592 }
593
594 return true;
595}
596
597template<class Impl>
598bool
599LSQ<Impl>::sqFull(ThreadID tid)
600{
601 //@todo: Change to Calculate All Entries for
602 //Dynamic Policy
603 if (lsqPolicy == SMTQueuePolicy::Dynamic)
604 return sqFull();
605 else
606 return thread[tid].sqFull();
607}
608
609template<class Impl>
610bool
611LSQ<Impl>::isStalled()
612{
613 list<ThreadID>::iterator threads = activeThreads->begin();
614 list<ThreadID>::iterator end = activeThreads->end();
615
616 while (threads != end) {
617 ThreadID tid = *threads++;
618
619 if (!thread[tid].isStalled())
620 return false;
621 }
622
623 return true;
624}
625
626template<class Impl>
627bool
628LSQ<Impl>::isStalled(ThreadID tid)
629{
630 if (lsqPolicy == SMTQueuePolicy::Dynamic)
631 return isStalled();
632 else
633 return thread[tid].isStalled();
634}
635
636template<class Impl>
637bool
638LSQ<Impl>::hasStoresToWB()
639{
640 list<ThreadID>::iterator threads = activeThreads->begin();
641 list<ThreadID>::iterator end = activeThreads->end();
642
643 while (threads != end) {
644 ThreadID tid = *threads++;
645
646 if (hasStoresToWB(tid))
647 return true;
648 }
649
650 return false;
651}
652
653template<class Impl>
654bool
655LSQ<Impl>::willWB()
656{
657 list<ThreadID>::iterator threads = activeThreads->begin();
658 list<ThreadID>::iterator end = activeThreads->end();
659
660 while (threads != end) {
661 ThreadID tid = *threads++;
662
663 if (willWB(tid))
664 return true;
665 }
666
667 return false;
668}
669
670template<class Impl>
671void
672LSQ<Impl>::dumpInsts() const
673{
674 list<ThreadID>::const_iterator threads = activeThreads->begin();
675 list<ThreadID>::const_iterator end = activeThreads->end();
676
677 while (threads != end) {
678 ThreadID tid = *threads++;
679
680 thread[tid].dumpInsts();
681 }
682}
683
| 334 return true;
335}
336
337template <class Impl>
338void
339LSQ<Impl>::recvTimingSnoopReq(PacketPtr pkt)
340{
341 DPRINTF(LSQ, "received pkt for addr:%#x %s\n", pkt->getAddr(),
342 pkt->cmdString());
343
344 // must be a snoop
345 if (pkt->isInvalidate()) {
346 DPRINTF(LSQ, "received invalidation for addr:%#x\n",
347 pkt->getAddr());
348 for (ThreadID tid = 0; tid < numThreads; tid++) {
349 thread[tid].checkSnoop(pkt);
350 }
351 }
352}
353
354template<class Impl>
355int
356LSQ<Impl>::getCount()
357{
358 unsigned total = 0;
359
360 list<ThreadID>::iterator threads = activeThreads->begin();
361 list<ThreadID>::iterator end = activeThreads->end();
362
363 while (threads != end) {
364 ThreadID tid = *threads++;
365
366 total += getCount(tid);
367 }
368
369 return total;
370}
371
372template<class Impl>
373int
374LSQ<Impl>::numLoads()
375{
376 unsigned total = 0;
377
378 list<ThreadID>::iterator threads = activeThreads->begin();
379 list<ThreadID>::iterator end = activeThreads->end();
380
381 while (threads != end) {
382 ThreadID tid = *threads++;
383
384 total += numLoads(tid);
385 }
386
387 return total;
388}
389
390template<class Impl>
391int
392LSQ<Impl>::numStores()
393{
394 unsigned total = 0;
395
396 list<ThreadID>::iterator threads = activeThreads->begin();
397 list<ThreadID>::iterator end = activeThreads->end();
398
399 while (threads != end) {
400 ThreadID tid = *threads++;
401
402 total += thread[tid].numStores();
403 }
404
405 return total;
406}
407
408template<class Impl>
409unsigned
410LSQ<Impl>::numFreeLoadEntries()
411{
412 unsigned total = 0;
413
414 list<ThreadID>::iterator threads = activeThreads->begin();
415 list<ThreadID>::iterator end = activeThreads->end();
416
417 while (threads != end) {
418 ThreadID tid = *threads++;
419
420 total += thread[tid].numFreeLoadEntries();
421 }
422
423 return total;
424}
425
426template<class Impl>
427unsigned
428LSQ<Impl>::numFreeStoreEntries()
429{
430 unsigned total = 0;
431
432 list<ThreadID>::iterator threads = activeThreads->begin();
433 list<ThreadID>::iterator end = activeThreads->end();
434
435 while (threads != end) {
436 ThreadID tid = *threads++;
437
438 total += thread[tid].numFreeStoreEntries();
439 }
440
441 return total;
442}
443
444template<class Impl>
445unsigned
446LSQ<Impl>::numFreeLoadEntries(ThreadID tid)
447{
448 return thread[tid].numFreeLoadEntries();
449}
450
451template<class Impl>
452unsigned
453LSQ<Impl>::numFreeStoreEntries(ThreadID tid)
454{
455 return thread[tid].numFreeStoreEntries();
456}
457
458template<class Impl>
459bool
460LSQ<Impl>::isFull()
461{
462 list<ThreadID>::iterator threads = activeThreads->begin();
463 list<ThreadID>::iterator end = activeThreads->end();
464
465 while (threads != end) {
466 ThreadID tid = *threads++;
467
468 if (!(thread[tid].lqFull() || thread[tid].sqFull()))
469 return false;
470 }
471
472 return true;
473}
474
475template<class Impl>
476bool
477LSQ<Impl>::isFull(ThreadID tid)
478{
479 //@todo: Change to Calculate All Entries for
480 //Dynamic Policy
481 if (lsqPolicy == SMTQueuePolicy::Dynamic)
482 return isFull();
483 else
484 return thread[tid].lqFull() || thread[tid].sqFull();
485}
486
487template<class Impl>
488bool
489LSQ<Impl>::isEmpty() const
490{
491 return lqEmpty() && sqEmpty();
492}
493
494template<class Impl>
495bool
496LSQ<Impl>::lqEmpty() const
497{
498 list<ThreadID>::const_iterator threads = activeThreads->begin();
499 list<ThreadID>::const_iterator end = activeThreads->end();
500
501 while (threads != end) {
502 ThreadID tid = *threads++;
503
504 if (!thread[tid].lqEmpty())
505 return false;
506 }
507
508 return true;
509}
510
511template<class Impl>
512bool
513LSQ<Impl>::sqEmpty() const
514{
515 list<ThreadID>::const_iterator threads = activeThreads->begin();
516 list<ThreadID>::const_iterator end = activeThreads->end();
517
518 while (threads != end) {
519 ThreadID tid = *threads++;
520
521 if (!thread[tid].sqEmpty())
522 return false;
523 }
524
525 return true;
526}
527
528template<class Impl>
529bool
530LSQ<Impl>::lqFull()
531{
532 list<ThreadID>::iterator threads = activeThreads->begin();
533 list<ThreadID>::iterator end = activeThreads->end();
534
535 while (threads != end) {
536 ThreadID tid = *threads++;
537
538 if (!thread[tid].lqFull())
539 return false;
540 }
541
542 return true;
543}
544
545template<class Impl>
546bool
547LSQ<Impl>::lqFull(ThreadID tid)
548{
549 //@todo: Change to Calculate All Entries for
550 //Dynamic Policy
551 if (lsqPolicy == SMTQueuePolicy::Dynamic)
552 return lqFull();
553 else
554 return thread[tid].lqFull();
555}
556
557template<class Impl>
558bool
559LSQ<Impl>::sqFull()
560{
561 list<ThreadID>::iterator threads = activeThreads->begin();
562 list<ThreadID>::iterator end = activeThreads->end();
563
564 while (threads != end) {
565 ThreadID tid = *threads++;
566
567 if (!sqFull(tid))
568 return false;
569 }
570
571 return true;
572}
573
574template<class Impl>
575bool
576LSQ<Impl>::sqFull(ThreadID tid)
577{
578 //@todo: Change to Calculate All Entries for
579 //Dynamic Policy
580 if (lsqPolicy == SMTQueuePolicy::Dynamic)
581 return sqFull();
582 else
583 return thread[tid].sqFull();
584}
585
586template<class Impl>
587bool
588LSQ<Impl>::isStalled()
589{
590 list<ThreadID>::iterator threads = activeThreads->begin();
591 list<ThreadID>::iterator end = activeThreads->end();
592
593 while (threads != end) {
594 ThreadID tid = *threads++;
595
596 if (!thread[tid].isStalled())
597 return false;
598 }
599
600 return true;
601}
602
603template<class Impl>
604bool
605LSQ<Impl>::isStalled(ThreadID tid)
606{
607 if (lsqPolicy == SMTQueuePolicy::Dynamic)
608 return isStalled();
609 else
610 return thread[tid].isStalled();
611}
612
613template<class Impl>
614bool
615LSQ<Impl>::hasStoresToWB()
616{
617 list<ThreadID>::iterator threads = activeThreads->begin();
618 list<ThreadID>::iterator end = activeThreads->end();
619
620 while (threads != end) {
621 ThreadID tid = *threads++;
622
623 if (hasStoresToWB(tid))
624 return true;
625 }
626
627 return false;
628}
629
630template<class Impl>
631bool
632LSQ<Impl>::willWB()
633{
634 list<ThreadID>::iterator threads = activeThreads->begin();
635 list<ThreadID>::iterator end = activeThreads->end();
636
637 while (threads != end) {
638 ThreadID tid = *threads++;
639
640 if (willWB(tid))
641 return true;
642 }
643
644 return false;
645}
646
647template<class Impl>
648void
649LSQ<Impl>::dumpInsts() const
650{
651 list<ThreadID>::const_iterator threads = activeThreads->begin();
652 list<ThreadID>::const_iterator end = activeThreads->end();
653
654 while (threads != end) {
655 ThreadID tid = *threads++;
656
657 thread[tid].dumpInsts();
658 }
659}
660
|
| 661static Addr
662addrBlockOffset(Addr addr, unsigned int block_size)
663{
664 return addr & (block_size - 1);
665}
666
667static Addr
668addrBlockAlign(Addr addr, uint64_t block_size)
669{
670 return addr & ~(block_size - 1);
671}
672
673static bool
674transferNeedsBurst(Addr addr, uint64_t size, uint64_t block_size)
675{
676 return (addrBlockOffset(addr, block_size) + size) > block_size;
677}
678
679template<class Impl>
680Fault
681LSQ<Impl>::pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
682 unsigned int size, Addr addr, Request::Flags flags,
683 uint64_t *res)
684{
685 ThreadID tid = cpu->contextToThread(inst->contextId());
686 auto cacheLineSize = cpu->cacheLineSize();
687 bool needs_burst = transferNeedsBurst(addr, size, cacheLineSize);
688 LSQRequest* req = nullptr;
689
690 if (inst->translationStarted()) {
691 req = inst->savedReq;
692 assert(req);
693 } else {
694 if (needs_burst) {
695 req = new SplitDataRequest(&thread[tid], inst, isLoad, addr,
696 size, flags, data, res);
697 } else {
698 req = new SingleDataRequest(&thread[tid], inst, isLoad, addr,
699 size, flags, data, res);
700 }
701 assert(req);
702 inst->setRequest();
703 req->taskId(cpu->taskId());
704
705 req->initiateTranslation();
706 }
707
708 /* This is the place were instructions get the effAddr. */
709 if (req->isTranslationComplete()) {
710 if (inst->getFault() == NoFault) {
711 inst->effAddr = req->getVaddr();
712 inst->effSize = size;
713 inst->effAddrValid(true);
714
715 if (cpu->checker) {
716 inst->reqToVerify = std::make_shared<Request>(*req->request());
717 }
718 if (isLoad)
719 inst->getFault() = cpu->read(req, inst->lqIdx);
720 else
721 inst->getFault() = cpu->write(req, data, inst->sqIdx);
722 } else if (isLoad) {
723 // Commit will have to clean up whatever happened. Set this
724 // instruction as executed.
725 inst->setExecuted();
726 }
727 }
728
729 if (inst->traceData)
730 inst->traceData->setMem(addr, size, flags);
731
732 return inst->getFault();
733}
734
735template<class Impl>
736void
737LSQ<Impl>::SingleDataRequest::finish(const Fault &fault, const RequestPtr &req,
738 ThreadContext* tc, BaseTLB::Mode mode)
739{
740 _fault.push_back(fault);
741 numInTranslationFragments = 0;
742 numTranslatedFragments = 1;
743 /* If the instruction has been squahsed, let the request know
744 * as it may have to self-destruct. */
745 if (_inst->isSquashed()) {
746 this->squashTranslation();
747 } else {
748 _inst->strictlyOrdered(req->isStrictlyOrdered());
749
750 flags.set(Flag::TranslationFinished);
751 if (fault == NoFault) {
752 _inst->physEffAddr = req->getPaddr();
753 _inst->memReqFlags = req->getFlags();
754 if (req->isCondSwap()) {
755 assert(_res);
756 req->setExtraData(*_res);
757 }
758 setState(State::Request);
759 } else {
760 setState(State::Fault);
761 }
762
763 LSQRequest::_inst->fault = fault;
764 LSQRequest::_inst->translationCompleted(true);
765 }
766}
767
768template<class Impl>
769void
770LSQ<Impl>::SplitDataRequest::finish(const Fault &fault, const RequestPtr &req,
771 ThreadContext* tc, BaseTLB::Mode mode)
772{
773 _fault.push_back(fault);
774 assert(req == _requests[numTranslatedFragments] || this->isDelayed());
775
776 numInTranslationFragments--;
777 numTranslatedFragments++;
778
779 mainReq->setFlags(req->getFlags());
780
781 if (numTranslatedFragments == _requests.size()) {
782 if (_inst->isSquashed()) {
783 this->squashTranslation();
784 } else {
785 _inst->strictlyOrdered(mainReq->isStrictlyOrdered());
786 flags.set(Flag::TranslationFinished);
787 auto fault_it = _fault.begin();
788 /* Ffwd to the first NoFault. */
789 while (fault_it != _fault.end() && *fault_it == NoFault)
790 fault_it++;
791 /* If none of the fragments faulted: */
792 if (fault_it == _fault.end()) {
793 _inst->physEffAddr = request(0)->getPaddr();
794
795 _inst->memReqFlags = mainReq->getFlags();
796 if (mainReq->isCondSwap()) {
797 assert(_res);
798 mainReq->setExtraData(*_res);
799 }
800 setState(State::Request);
801 _inst->fault = NoFault;
802 } else {
803 setState(State::Fault);
804 _inst->fault = *fault_it;
805 }
806 _inst->translationCompleted(true);
807 }
808 }
809}
810
811template<class Impl>
812void
813LSQ<Impl>::SingleDataRequest::initiateTranslation()
814{
815 _inst->translationStarted(true);
816 setState(State::Translation);
817 flags.set(Flag::TranslationStarted);
818
819 _inst->savedReq = this;
820 sendFragmentToTranslation(0);
821
822 if (isTranslationComplete()) {
823 }
824}
825
826template<class Impl>
827PacketPtr
828LSQ<Impl>::SplitDataRequest::mainPacket()
829{
830 return _mainPacket;
831}
832
833template<class Impl>
834RequestPtr
835LSQ<Impl>::SplitDataRequest::mainRequest()
836{
837 return mainReq;
838}
839
840template<class Impl>
841void
842LSQ<Impl>::SplitDataRequest::initiateTranslation()
843{
844 _inst->translationStarted(true);
845 setState(State::Translation);
846 flags.set(Flag::TranslationStarted);
847
848 unsigned int cacheLineSize = _port.cacheLineSize();
849 Addr base_addr = _addr;
850 Addr next_addr = addrBlockAlign(_addr + cacheLineSize, cacheLineSize);
851 Addr final_addr = addrBlockAlign(_addr + _size, cacheLineSize);
852 uint32_t size_so_far = 0;
853
854 mainReq = std::make_shared<Request>(_inst->getASID(), base_addr,
855 _size, _flags, _inst->masterId(),
856 _inst->instAddr(), _inst->contextId());
857
858 // Paddr is not used in mainReq. However, we will accumulate the flags
859 // from the sub requests into mainReq by calling setFlags() in finish().
860 // setFlags() assumes that paddr is set so flip the paddr valid bit here to
861 // avoid a potential assert in setFlags() when we call it from finish().
862 mainReq->setPaddr(0);
863
864 /* Get the pre-fix, possibly unaligned. */
865 _requests.push_back(std::make_shared<Request>(_inst->getASID(), base_addr,
866 next_addr - base_addr, _flags, _inst->masterId(),
867 _inst->instAddr(), _inst->contextId()));
868 size_so_far = next_addr - base_addr;
869
870 /* We are block aligned now, reading whole blocks. */
871 base_addr = next_addr;
872 while (base_addr != final_addr) {
873 _requests.push_back(std::make_shared<Request>(_inst->getASID(),
874 base_addr, cacheLineSize, _flags, _inst->masterId(),
875 _inst->instAddr(), _inst->contextId()));
876 size_so_far += cacheLineSize;
877 base_addr += cacheLineSize;
878 }
879
880 /* Deal with the tail. */
881 if (size_so_far < _size) {
882 _requests.push_back(std::make_shared<Request>(_inst->getASID(),
883 base_addr, _size - size_so_far, _flags, _inst->masterId(),
884 _inst->instAddr(), _inst->contextId()));
885 }
886
887 /* Setup the requests and send them to translation. */
888 for (auto& r: _requests) {
889 r->setReqInstSeqNum(_inst->seqNum);
890 r->taskId(_taskId);
891 }
892 this->_inst->savedReq = this;
893 numInTranslationFragments = 0;
894 numTranslatedFragments = 0;
895
896 for (uint32_t i = 0; i < _requests.size(); i++) {
897 sendFragmentToTranslation(i);
898 }
899}
900
901template<class Impl>
902void
903LSQ<Impl>::LSQRequest::sendFragmentToTranslation(int i)
904{
905 numInTranslationFragments++;
906 _port.dTLB()->translateTiming(
907 this->request(i),
908 this->_inst->thread->getTC(), this,
909 this->isLoad() ? BaseTLB::Read : BaseTLB::Write);
910}
911
912template<class Impl>
913bool
914LSQ<Impl>::SingleDataRequest::recvTimingResp(PacketPtr pkt)
915{
916 assert(_numOutstandingPackets == 1);
917 auto state = dynamic_cast<LSQSenderState*>(pkt->senderState);
918 setState(State::Complete);
919 flags.set(Flag::Complete);
920 state->outstanding--;
921 assert(pkt == _packets.front());
922 _port.completeDataAccess(pkt);
923 return true;
924}
925
926template<class Impl>
927bool
928LSQ<Impl>::SplitDataRequest::recvTimingResp(PacketPtr pkt)
929{
930 auto state = dynamic_cast<LSQSenderState*>(pkt->senderState);
931 uint32_t pktIdx = 0;
932 while (pktIdx < _packets.size() && pkt != _packets[pktIdx])
933 pktIdx++;
934 assert(pktIdx < _packets.size());
935 assert(pkt->req == _requests[pktIdx]);
936 assert(pkt == _packets[pktIdx]);
937 numReceivedPackets++;
938 state->outstanding--;
939 if (numReceivedPackets == _packets.size()) {
940 setState(State::Complete);
941 flags.set(Flag::Complete);
942 /* Assemble packets. */
943 PacketPtr resp = isLoad()
944 ? Packet::createRead(mainReq)
945 : Packet::createWrite(mainReq);
946 if (isLoad())
947 resp->dataStatic(_inst->memData);
948 else
949 resp->dataStatic(_data);
950 resp->senderState = _senderState;
951 _port.completeDataAccess(resp);
952 delete resp;
953 }
954 return true;
955}
956
957template<class Impl>
958void
959LSQ<Impl>::SingleDataRequest::buildPackets()
960{
961 assert(_senderState);
962 /* Retries do not create new packets. */
963 if (_packets.size() == 0) {
964 _packets.push_back(
965 isLoad()
966 ? Packet::createRead(request())
967 : Packet::createWrite(request()));
968 _packets.back()->dataStatic(_inst->memData);
969 _packets.back()->senderState = _senderState;
970 }
971 assert(_packets.size() == 1);
972}
973
974template<class Impl>
975void
976LSQ<Impl>::SplitDataRequest::buildPackets()
977{
978 /* Extra data?? */
979 ptrdiff_t offset = 0;
980 if (_packets.size() == 0) {
981 /* New stuff */
982 if (isLoad()) {
983 _mainPacket = Packet::createRead(mainReq);
984 _mainPacket->dataStatic(_inst->memData);
985 }
986 for (auto& r: _requests) {
987 PacketPtr pkt = isLoad() ? Packet::createRead(r)
988 : Packet::createWrite(r);
989 if (isLoad()) {
990 pkt->dataStatic(_inst->memData + offset);
991 } else {
992 uint8_t* req_data = new uint8_t[r->getSize()];
993 std::memcpy(req_data,
994 _inst->memData + offset,
995 r->getSize());
996 pkt->dataDynamic(req_data);
997 }
998 offset += r->getSize();
999 pkt->senderState = _senderState;
1000 _packets.push_back(pkt);
1001 }
1002 }
1003 assert(_packets.size() == _requests.size());
1004}
1005
1006template<class Impl>
1007void
1008LSQ<Impl>::SingleDataRequest::sendPacketToCache()
1009{
1010 assert(_numOutstandingPackets == 0);
1011 if (lsqUnit()->trySendPacket(isLoad(), _packets.at(0)))
1012 _numOutstandingPackets = 1;
1013}
1014
1015template<class Impl>
1016void
1017LSQ<Impl>::SplitDataRequest::sendPacketToCache()
1018{
1019 /* Try to send the packets. */
1020 while (numReceivedPackets + _numOutstandingPackets < _packets.size() &&
1021 lsqUnit()->trySendPacket(isLoad(),
1022 _packets.at(numReceivedPackets + _numOutstandingPackets))) {
1023 _numOutstandingPackets++;
1024 }
1025}
1026
1027template<class Impl>
1028void
1029LSQ<Impl>::SingleDataRequest::handleIprWrite(ThreadContext *thread,
1030 PacketPtr pkt)
1031{
1032 TheISA::handleIprWrite(thread, pkt);
1033}
1034
1035template<class Impl>
1036void
1037LSQ<Impl>::SplitDataRequest::handleIprWrite(ThreadContext *thread,
1038 PacketPtr mainPkt)
1039{
1040 unsigned offset = 0;
1041 for (auto r: _requests) {
1042 PacketPtr pkt = new Packet(r, MemCmd::WriteReq);
1043 pkt->dataStatic(mainPkt->getPtr<uint8_t>() + offset);
1044 TheISA::handleIprWrite(thread, pkt);
1045 offset += r->getSize();
1046 delete pkt;
1047 }
1048}
1049
1050template<class Impl>
1051Cycles
1052LSQ<Impl>::SingleDataRequest::handleIprRead(ThreadContext *thread,
1053 PacketPtr pkt)
1054{
1055 return TheISA::handleIprRead(thread, pkt);
1056}
1057
1058template<class Impl>
1059Cycles
1060LSQ<Impl>::SplitDataRequest::handleIprRead(ThreadContext *thread,
1061 PacketPtr mainPkt)
1062{
1063 Cycles delay(0);
1064 unsigned offset = 0;
1065
1066 for (auto r: _requests) {
1067 PacketPtr pkt = new Packet(r, MemCmd::ReadReq);
1068 pkt->dataStatic(mainPkt->getPtr<uint8_t>() + offset);
1069 Cycles d = TheISA::handleIprRead(thread, pkt);
1070 if (d > delay)
1071 delay = d;
1072 offset += r->getSize();
1073 delete pkt;
1074 }
1075 return delay;
1076}
1077
1078template<class Impl>
1079bool
1080LSQ<Impl>::SingleDataRequest::isCacheBlockHit(Addr blockAddr, Addr blockMask)
1081{
1082 return ( (LSQRequest::_requests[0]->getPaddr() & blockMask) == blockAddr);
1083}
1084
1085template<class Impl>
1086bool
1087LSQ<Impl>::SplitDataRequest::isCacheBlockHit(Addr blockAddr, Addr blockMask)
1088{
1089 bool is_hit = false;
1090 for (auto &r: _requests) {
1091 if ((r->getPaddr() & blockMask) == blockAddr) {
1092 is_hit = true;
1093 break;
1094 }
1095 }
1096 return is_hit;
1097}
1098
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684#endif//__CPU_O3_LSQ_IMPL_HH__
| 1099#endif//__CPU_O3_LSQ_IMPL_HH__
|