lsq_impl.hh (2864:eab7ff8f6d72) | lsq_impl.hh (2907:7b0ababb4166) |
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1/* 2 * Copyright (c) 2005-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 22 unchanged lines hidden (view full) --- 31#include <algorithm> 32#include <string> 33 34#include "cpu/o3/lsq.hh" 35 36using namespace std; 37 38template <class Impl> | 1/* 2 * Copyright (c) 2005-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 22 unchanged lines hidden (view full) --- 31#include <algorithm> 32#include <string> 33 34#include "cpu/o3/lsq.hh" 35 36using namespace std; 37 38template <class Impl> |
39Tick 40LSQ<Impl>::DcachePort::recvAtomic(PacketPtr pkt) 41{ 42 panic("O3CPU model does not work with atomic mode!"); 43 return curTick; 44} 45 46template <class Impl> 47void 48LSQ<Impl>::DcachePort::recvFunctional(PacketPtr pkt) 49{ 50 panic("O3CPU doesn't expect recvFunctional callback!"); 51} 52 53template <class Impl> 54void 55LSQ<Impl>::DcachePort::recvStatusChange(Status status) 56{ 57 if (status == RangeChange) 58 return; 59 60 panic("O3CPU doesn't expect recvStatusChange callback!"); 61} 62 63template <class Impl> 64bool 65LSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt) 66{ 67 lsq->thread[pkt->req->getThreadNum()].completeDataAccess(pkt); 68 return true; 69} 70 71template <class Impl> 72void 73LSQ<Impl>::DcachePort::recvRetry() 74{ 75 lsq->thread[lsq->retryTid].recvRetry(); 76 // Speculatively clear the retry Tid. This will get set again if 77 // the LSQUnit was unable to complete its access. 78 lsq->retryTid = -1; 79} 80 81template <class Impl> |
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39LSQ<Impl>::LSQ(Params *params) | 82LSQ<Impl>::LSQ(Params *params) |
40 : LQEntries(params->LQEntries), SQEntries(params->SQEntries), 41 numThreads(params->numberOfThreads) | 83 : dcachePort(this), LQEntries(params->LQEntries), 84 SQEntries(params->SQEntries), numThreads(params->numberOfThreads), 85 retryTid(-1) |
42{ 43 DPRINTF(LSQ, "Creating LSQ object.\n"); 44 45 //**********************************************/ 46 //************ Handle SMT Parameters ***********/ 47 //**********************************************/ 48 string policy = params->smtLSQPolicy; 49 --- 39 unchanged lines hidden (view full) --- 89 90 } else { 91 assert(0 && "Invalid LSQ Sharing Policy.Options Are:{Dynamic," 92 "Partitioned, Threshold}"); 93 } 94 95 //Initialize LSQs 96 for (int tid=0; tid < numThreads; tid++) { | 86{ 87 DPRINTF(LSQ, "Creating LSQ object.\n"); 88 89 //**********************************************/ 90 //************ Handle SMT Parameters ***********/ 91 //**********************************************/ 92 string policy = params->smtLSQPolicy; 93 --- 39 unchanged lines hidden (view full) --- 133 134 } else { 135 assert(0 && "Invalid LSQ Sharing Policy.Options Are:{Dynamic," 136 "Partitioned, Threshold}"); 137 } 138 139 //Initialize LSQs 140 for (int tid=0; tid < numThreads; tid++) { |
97 thread[tid].init(params, maxLQEntries, maxSQEntries, tid); | 141 thread[tid].init(params, this, maxLQEntries, maxSQEntries, tid); 142 thread[tid].setDcachePort(&dcachePort); |
98 } 99} 100 101 102template<class Impl> 103std::string 104LSQ<Impl>::name() const 105{ --- 19 unchanged lines hidden (view full) --- 125} 126 127template<class Impl> 128void 129LSQ<Impl>::setCPU(O3CPU *cpu_ptr) 130{ 131 cpu = cpu_ptr; 132 | 143 } 144} 145 146 147template<class Impl> 148std::string 149LSQ<Impl>::name() const 150{ --- 19 unchanged lines hidden (view full) --- 170} 171 172template<class Impl> 173void 174LSQ<Impl>::setCPU(O3CPU *cpu_ptr) 175{ 176 cpu = cpu_ptr; 177 |
178 dcachePort.setName(name()); 179 |
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133 for (int tid=0; tid < numThreads; tid++) { 134 thread[tid].setCPU(cpu_ptr); 135 } 136} 137 138template<class Impl> 139void 140LSQ<Impl>::setIEW(IEW *iew_ptr) --- 402 unchanged lines hidden --- | 180 for (int tid=0; tid < numThreads; tid++) { 181 thread[tid].setCPU(cpu_ptr); 182 } 183} 184 185template<class Impl> 186void 187LSQ<Impl>::setIEW(IEW *iew_ptr) --- 402 unchanged lines hidden --- |