1/*
2 * Copyright (c) 2011-2012, 2014, 2017-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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58
59using namespace std;
60
61template <class Impl>
62LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params)
63 : cpu(cpu_ptr), iewStage(iew_ptr),
64 _cacheBlocked(false),
65 cacheStorePorts(params->cacheStorePorts), usedStorePorts(0),
66 lsqPolicy(params->smtLSQPolicy),
67 LQEntries(params->LQEntries),
68 SQEntries(params->SQEntries),
69 maxLQEntries(maxLSQAllocation(lsqPolicy, LQEntries, params->numThreads,
70 params->smtLSQThreshold)),
71 maxSQEntries(maxLSQAllocation(lsqPolicy, SQEntries, params->numThreads,
72 params->smtLSQThreshold)),
73 numThreads(params->numThreads)

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168 usedStorePorts = 0;
169 _cacheBlocked = false;
170
171 for (ThreadID tid = 0; tid < numThreads; tid++) {
172 thread[tid].takeOverFrom();
173 }
174}
175
176template<class Impl>
177bool
178LSQ<Impl>::cacheBlocked() const
179{
180 return _cacheBlocked;
181}
182
183template<class Impl>
184void
185LSQ<Impl>::cacheBlocked(bool v)
186{
187 _cacheBlocked = v;
188}
189
190template<class Impl>
191bool
192LSQ<Impl>::storePortAvailable() const
193{
194 return usedStorePorts < cacheStorePorts;
195}
196
197template<class Impl>
198void
199LSQ<Impl>::storePortBusy()
200{
201 usedStorePorts++;
202 assert(usedStorePorts <= cacheStorePorts);
203}
204
205template<class Impl>
206void
207LSQ<Impl>::insertLoad(const DynInstPtr &load_inst)
208{
209 ThreadID tid = load_inst->threadNumber;
210

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