lsq.hh (8794:e2ac2b7164dd) lsq.hh (8799:dac1e33e07b0)
1/*
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright

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60 LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params);
61
62 /** Returns the name of the LSQ. */
63 std::string name() const;
64
65 /** Registers statistics of each LSQ unit. */
66 void regStats();
67
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright

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72 LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params);
73
74 /** Returns the name of the LSQ. */
75 std::string name() const;
76
77 /** Registers statistics of each LSQ unit. */
78 void regStats();
79
68 /** Returns dcache port.
69 * @todo: Dcache port needs to be moved up to this level for SMT
70 * to work. For now it just returns the port from one of the
71 * threads.
72 */
73 Port *getDcachePort() { return &dcachePort; }
74
75 /** Sets the pointer to the list of active threads. */
76 void setActiveThreads(std::list<ThreadID> *at_ptr);
77 /** Switches out the LSQ. */
78 void switchOut();
79 /** Takes over execution from another CPU's thread. */
80 void takeOverFrom();
81
82 /** Number of entries needed for the given amount of threads.*/

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276 uint8_t *data, int load_idx);
277
278 /** Executes a store operation, using the store specified at the store
279 * index.
280 */
281 Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
282 uint8_t *data, int store_idx);
283
80 /** Sets the pointer to the list of active threads. */
81 void setActiveThreads(std::list<ThreadID> *at_ptr);
82 /** Switches out the LSQ. */
83 void switchOut();
84 /** Takes over execution from another CPU's thread. */
85 void takeOverFrom();
86
87 /** Number of entries needed for the given amount of threads.*/

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281 uint8_t *data, int load_idx);
282
283 /** Executes a store operation, using the store specified at the store
284 * index.
285 */
286 Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
287 uint8_t *data, int store_idx);
288
289 /**
290 * Retry the previous send that failed.
291 */
292 void recvRetry();
293
294 /**
295 * Handles writing back and completing the load or store that has
296 * returned from memory.
297 *
298 * @param pkt Response packet from the memory sub-system
299 */
300 bool recvTiming(PacketPtr pkt);
301
284 /** The CPU pointer. */
285 O3CPU *cpu;
286
287 /** The IEW stage pointer. */
288 IEW *iewStage;
289
302 /** The CPU pointer. */
303 O3CPU *cpu;
304
305 /** The IEW stage pointer. */
306 IEW *iewStage;
307
290 /** DcachePort class for this LSQ. Handles doing the
291 * communication with the cache/memory.
292 */
293 class DcachePort : public Port
294 {
295 protected:
296 /** Pointer to LSQ. */
297 LSQ *lsq;
298
299 public:
300 /** Default constructor. */
301 DcachePort(LSQ *_lsq)
302 : Port(_lsq->name() + "-dport", _lsq->cpu), lsq(_lsq)
303 { }
304
305 bool snoopRangeSent;
306
307 virtual void setPeer(Port *port);
308
309 protected:
310 /** Atomic version of receive. Panics. */
311 virtual Tick recvAtomic(PacketPtr pkt);
312
313 /** Functional version of receive. Panics. */
314 virtual void recvFunctional(PacketPtr pkt);
315
316 /** Receives status change. Other than range changing, panics. */
317 virtual void recvStatusChange(Status status);
318
319 /** Returns the address ranges of this device. */
320 virtual void getDeviceAddressRanges(AddrRangeList &resp,
321 bool &snoop)
322 { resp.clear(); snoop = true; }
323
324 /** Timing version of receive. Handles writing back and
325 * completing the load or store that has returned from
326 * memory. */
327 virtual bool recvTiming(PacketPtr pkt);
328
329 /** Handles doing a retry of the previous send. */
330 virtual void recvRetry();
331 };
332
333 /** D-cache port. */
334 DcachePort dcachePort;
335
336 /** Tell the CPU to update the Phys and Virt ports. */
337 void updateMemPorts() { cpu->updateMemPorts(); }
338
339 protected:
340 /** The LSQ policy for SMT mode. */
341 LSQPolicy lsqPolicy;
342
343 /** The LSQ units for individual threads. */
344 LSQUnit thread[Impl::MaxThreads];
345
346 /** List of Active Threads in System. */

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309 /** The LSQ policy for SMT mode. */
310 LSQPolicy lsqPolicy;
311
312 /** The LSQ units for individual threads. */
313 LSQUnit thread[Impl::MaxThreads];
314
315 /** List of Active Threads in System. */

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