lsq.hh (8737:770ccf3af571) lsq.hh (8793:5f25086326ac)
1/*
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright

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47#include <queue>
48
49#include "config/full_system.hh"
50#include "cpu/o3/lsq_unit.hh"
51#include "cpu/inst_seq.hh"
52#include "mem/port.hh"
53#include "sim/sim_object.hh"
54
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright

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35#include <queue>
36
37#include "config/full_system.hh"
38#include "cpu/o3/lsq_unit.hh"
39#include "cpu/inst_seq.hh"
40#include "mem/port.hh"
41#include "sim/sim_object.hh"
42
55struct DerivO3CPUParams;
43class DerivO3CPUParams;
56
57template <class Impl>
58class LSQ {
59 public:
60 typedef typename Impl::O3CPU O3CPU;
61 typedef typename Impl::DynInstPtr DynInstPtr;
62 typedef typename Impl::CPUPol::IEW IEW;
63 typedef typename Impl::CPUPol::LSQUnit LSQUnit;

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73 LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params);
74
75 /** Returns the name of the LSQ. */
76 std::string name() const;
77
78 /** Registers statistics of each LSQ unit. */
79 void regStats();
80
44
45template <class Impl>
46class LSQ {
47 public:
48 typedef typename Impl::O3CPU O3CPU;
49 typedef typename Impl::DynInstPtr DynInstPtr;
50 typedef typename Impl::CPUPol::IEW IEW;
51 typedef typename Impl::CPUPol::LSQUnit LSQUnit;

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61 LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params);
62
63 /** Returns the name of the LSQ. */
64 std::string name() const;
65
66 /** Registers statistics of each LSQ unit. */
67 void regStats();
68
69 /** Returns dcache port.
70 * @todo: Dcache port needs to be moved up to this level for SMT
71 * to work. For now it just returns the port from one of the
72 * threads.
73 */
74 Port *getDcachePort() { return &dcachePort; }
75
81 /** Sets the pointer to the list of active threads. */
82 void setActiveThreads(std::list<ThreadID> *at_ptr);
83 /** Switches out the LSQ. */
84 void switchOut();
85 /** Takes over execution from another CPU's thread. */
86 void takeOverFrom();
87
88 /** Number of entries needed for the given amount of threads.*/

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282 uint8_t *data, int load_idx);
283
284 /** Executes a store operation, using the store specified at the store
285 * index.
286 */
287 Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
288 uint8_t *data, int store_idx);
289
76 /** Sets the pointer to the list of active threads. */
77 void setActiveThreads(std::list<ThreadID> *at_ptr);
78 /** Switches out the LSQ. */
79 void switchOut();
80 /** Takes over execution from another CPU's thread. */
81 void takeOverFrom();
82
83 /** Number of entries needed for the given amount of threads.*/

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277 uint8_t *data, int load_idx);
278
279 /** Executes a store operation, using the store specified at the store
280 * index.
281 */
282 Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
283 uint8_t *data, int store_idx);
284
290 /**
291 * Retry the previous send that failed.
292 */
293 void recvRetry();
294
295 /**
296 * Handles writing back and completing the load or store that has
297 * returned from memory.
298 *
299 * @param pkt Response packet from the memory sub-system
300 */
301 bool recvTiming(PacketPtr pkt);
302
303 /** The CPU pointer. */
304 O3CPU *cpu;
305
306 /** The IEW stage pointer. */
307 IEW *iewStage;
308
285 /** The CPU pointer. */
286 O3CPU *cpu;
287
288 /** The IEW stage pointer. */
289 IEW *iewStage;
290
291 /** DcachePort class for this LSQ. Handles doing the
292 * communication with the cache/memory.
293 */
294 class DcachePort : public Port
295 {
296 protected:
297 /** Pointer to LSQ. */
298 LSQ *lsq;
299
300 public:
301 /** Default constructor. */
302 DcachePort(LSQ *_lsq)
303 : Port(_lsq->name() + "-dport", _lsq->cpu), lsq(_lsq)
304 { }
305
306 bool snoopRangeSent;
307
308 virtual void setPeer(Port *port);
309
310 protected:
311 /** Atomic version of receive. Panics. */
312 virtual Tick recvAtomic(PacketPtr pkt);
313
314 /** Functional version of receive. Panics. */
315 virtual void recvFunctional(PacketPtr pkt);
316
317 /** Receives status change. Other than range changing, panics. */
318 virtual void recvStatusChange(Status status);
319
320 /** Returns the address ranges of this device. */
321 virtual void getDeviceAddressRanges(AddrRangeList &resp,
322 bool &snoop)
323 { resp.clear(); snoop = true; }
324
325 /** Timing version of receive. Handles writing back and
326 * completing the load or store that has returned from
327 * memory. */
328 virtual bool recvTiming(PacketPtr pkt);
329
330 /** Handles doing a retry of the previous send. */
331 virtual void recvRetry();
332 };
333
334 /** D-cache port. */
335 DcachePort dcachePort;
336
337 /** Tell the CPU to update the Phys and Virt ports. */
338 void updateMemPorts() { cpu->updateMemPorts(); }
339
309 protected:
310 /** The LSQ policy for SMT mode. */
311 LSQPolicy lsqPolicy;
312
313 /** The LSQ units for individual threads. */
314 LSQUnit thread[Impl::MaxThreads];
315
316 /** List of Active Threads in System. */

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341 /** The LSQ policy for SMT mode. */
342 LSQPolicy lsqPolicy;
343
344 /** The LSQ units for individual threads. */
345 LSQUnit thread[Impl::MaxThreads];
346
347 /** List of Active Threads in System. */

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