lsq.hh (8706:b1838faf3bcc) | lsq.hh (8707:489489c67fd9) |
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1/* | 1/* |
2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * |
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2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright --- 51 unchanged lines hidden (view full) --- 61 LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params); 62 63 /** Returns the name of the LSQ. */ 64 std::string name() const; 65 66 /** Registers statistics of each LSQ unit. */ 67 void regStats(); 68 | 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright --- 51 unchanged lines hidden (view full) --- 73 LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params); 74 75 /** Returns the name of the LSQ. */ 76 std::string name() const; 77 78 /** Registers statistics of each LSQ unit. */ 79 void regStats(); 80 |
69 /** Returns dcache port. 70 * @todo: Dcache port needs to be moved up to this level for SMT 71 * to work. For now it just returns the port from one of the 72 * threads. 73 */ 74 Port *getDcachePort() { return &dcachePort; } 75 | |
76 /** Sets the pointer to the list of active threads. */ 77 void setActiveThreads(std::list<ThreadID> *at_ptr); 78 /** Switches out the LSQ. */ 79 void switchOut(); 80 /** Takes over execution from another CPU's thread. */ 81 void takeOverFrom(); 82 83 /** Number of entries needed for the given amount of threads.*/ --- 193 unchanged lines hidden (view full) --- 277 uint8_t *data, int load_idx); 278 279 /** Executes a store operation, using the store specified at the store 280 * index. 281 */ 282 Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 283 uint8_t *data, int store_idx); 284 | 81 /** Sets the pointer to the list of active threads. */ 82 void setActiveThreads(std::list<ThreadID> *at_ptr); 83 /** Switches out the LSQ. */ 84 void switchOut(); 85 /** Takes over execution from another CPU's thread. */ 86 void takeOverFrom(); 87 88 /** Number of entries needed for the given amount of threads.*/ --- 193 unchanged lines hidden (view full) --- 282 uint8_t *data, int load_idx); 283 284 /** Executes a store operation, using the store specified at the store 285 * index. 286 */ 287 Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 288 uint8_t *data, int store_idx); 289 |
290 /** 291 * Retry the previous send that failed. 292 */ 293 void recvRetry(); 294 295 /** 296 * Handles writing back and completing the load or store that has 297 * returned from memory. 298 * 299 * @param pkt Response packet from the memory sub-system 300 */ 301 bool recvTiming(PacketPtr pkt); 302 |
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285 /** The CPU pointer. */ 286 O3CPU *cpu; 287 288 /** The IEW stage pointer. */ 289 IEW *iewStage; 290 | 303 /** The CPU pointer. */ 304 O3CPU *cpu; 305 306 /** The IEW stage pointer. */ 307 IEW *iewStage; 308 |
291 /** DcachePort class for this LSQ. Handles doing the 292 * communication with the cache/memory. 293 */ 294 class DcachePort : public Port 295 { 296 protected: 297 /** Pointer to LSQ. */ 298 LSQ *lsq; 299 300 public: 301 /** Default constructor. */ 302 DcachePort(LSQ *_lsq) 303 : Port(_lsq->name() + "-dport", _lsq->cpu), lsq(_lsq) 304 { } 305 306 bool snoopRangeSent; 307 308 protected: 309 /** Atomic version of receive. Panics. */ 310 virtual Tick recvAtomic(PacketPtr pkt); 311 312 /** Functional version of receive. Panics. */ 313 virtual void recvFunctional(PacketPtr pkt); 314 315 /** Receives status change. Other than range changing, panics. */ 316 virtual void recvStatusChange(Status status); 317 318 /** Returns the address ranges of this device. */ 319 virtual void getDeviceAddressRanges(AddrRangeList &resp, 320 bool &snoop) 321 { resp.clear(); snoop = true; } 322 323 /** Timing version of receive. Handles writing back and 324 * completing the load or store that has returned from 325 * memory. */ 326 virtual bool recvTiming(PacketPtr pkt); 327 328 /** Handles doing a retry of the previous send. */ 329 virtual void recvRetry(); 330 }; 331 332 /** D-cache port. */ 333 DcachePort dcachePort; 334 | |
335 protected: 336 /** The LSQ policy for SMT mode. */ 337 LSQPolicy lsqPolicy; 338 339 /** The LSQ units for individual threads. */ 340 LSQUnit thread[Impl::MaxThreads]; 341 342 /** List of Active Threads in System. */ --- 42 unchanged lines hidden --- | 309 protected: 310 /** The LSQ policy for SMT mode. */ 311 LSQPolicy lsqPolicy; 312 313 /** The LSQ units for individual threads. */ 314 LSQUnit thread[Impl::MaxThreads]; 315 316 /** List of Active Threads in System. */ --- 42 unchanged lines hidden --- |