lsq.hh (6974:4d4903a3e7c5) lsq.hh (7520:67c670459d01)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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268 void dumpInsts();
269 /** Debugging function to print out instructions from a specific thread. */
270 void dumpInsts(ThreadID tid)
271 { thread[tid].dumpInsts(); }
272
273 /** Executes a read operation, using the load specified at the load
274 * index.
275 */
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 259 unchanged lines hidden (view full) ---

268 void dumpInsts();
269 /** Debugging function to print out instructions from a specific thread. */
270 void dumpInsts(ThreadID tid)
271 { thread[tid].dumpInsts(); }
272
273 /** Executes a read operation, using the load specified at the load
274 * index.
275 */
276 template <class T>
277 Fault read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
276 Fault read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
278 T &data, int load_idx);
277 uint8_t *data, int load_idx);
279
280 /** Executes a store operation, using the store specified at the store
281 * index.
282 */
278
279 /** Executes a store operation, using the store specified at the store
280 * index.
281 */
283 template <class T>
284 Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
282 Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
285 T &data, int store_idx);
283 uint8_t *data, int store_idx);
286
287 /** The CPU pointer. */
288 O3CPU *cpu;
289
290 /** The IEW stage pointer. */
291 IEW *iewStage;
292
293 /** DcachePort class for this LSQ. Handles doing the

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366 ThreadID numThreads;
367
368 /** The thread id of the LSQ Unit that is currently waiting for a
369 * retry. */
370 ThreadID retryTid;
371};
372
373template <class Impl>
284
285 /** The CPU pointer. */
286 O3CPU *cpu;
287
288 /** The IEW stage pointer. */
289 IEW *iewStage;
290
291 /** DcachePort class for this LSQ. Handles doing the

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364 ThreadID numThreads;
365
366 /** The thread id of the LSQ Unit that is currently waiting for a
367 * retry. */
368 ThreadID retryTid;
369};
370
371template <class Impl>
374template <class T>
375Fault
376LSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
372Fault
373LSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
377 T &data, int load_idx)
374 uint8_t *data, int load_idx)
378{
379 ThreadID tid = req->threadId();
380
381 return thread[tid].read(req, sreqLow, sreqHigh, data, load_idx);
382}
383
384template <class Impl>
375{
376 ThreadID tid = req->threadId();
377
378 return thread[tid].read(req, sreqLow, sreqHigh, data, load_idx);
379}
380
381template <class Impl>
385template <class T>
386Fault
387LSQ<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
382Fault
383LSQ<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
388 T &data, int store_idx)
384 uint8_t *data, int store_idx)
389{
390 ThreadID tid = req->threadId();
391
392 return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx);
393}
394
395#endif // __CPU_O3_LSQ_HH__
385{
386 ThreadID tid = req->threadId();
387
388 return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx);
389}
390
391#endif // __CPU_O3_LSQ_HH__