lsq.hh (6221:58a3c04e6344) lsq.hh (6974:4d4903a3e7c5)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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265 { retryTid = tid; }
266
267 /** Debugging function to print out all instructions. */
268 void dumpInsts();
269 /** Debugging function to print out instructions from a specific thread. */
270 void dumpInsts(ThreadID tid)
271 { thread[tid].dumpInsts(); }
272
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 256 unchanged lines hidden (view full) ---

265 { retryTid = tid; }
266
267 /** Debugging function to print out all instructions. */
268 void dumpInsts();
269 /** Debugging function to print out instructions from a specific thread. */
270 void dumpInsts(ThreadID tid)
271 { thread[tid].dumpInsts(); }
272
273 /** Executes a read operation, using the load specified at the load index. */
273 /** Executes a read operation, using the load specified at the load
274 * index.
275 */
274 template <class T>
276 template <class T>
275 Fault read(RequestPtr req, T &data, int load_idx);
277 Fault read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
278 T &data, int load_idx);
276
277 /** Executes a store operation, using the store specified at the store
279
280 /** Executes a store operation, using the store specified at the store
278 * index.
281 * index.
279 */
280 template <class T>
282 */
283 template <class T>
281 Fault write(RequestPtr req, T &data, int store_idx);
284 Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
285 T &data, int store_idx);
282
283 /** The CPU pointer. */
284 O3CPU *cpu;
285
286 /** The IEW stage pointer. */
287 IEW *iewStage;
288
289 /** DcachePort class for this LSQ. Handles doing the

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364 /** The thread id of the LSQ Unit that is currently waiting for a
365 * retry. */
366 ThreadID retryTid;
367};
368
369template <class Impl>
370template <class T>
371Fault
286
287 /** The CPU pointer. */
288 O3CPU *cpu;
289
290 /** The IEW stage pointer. */
291 IEW *iewStage;
292
293 /** DcachePort class for this LSQ. Handles doing the

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368 /** The thread id of the LSQ Unit that is currently waiting for a
369 * retry. */
370 ThreadID retryTid;
371};
372
373template <class Impl>
374template <class T>
375Fault
372LSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
376LSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
377 T &data, int load_idx)
373{
374 ThreadID tid = req->threadId();
375
378{
379 ThreadID tid = req->threadId();
380
376 return thread[tid].read(req, data, load_idx);
381 return thread[tid].read(req, sreqLow, sreqHigh, data, load_idx);
377}
378
379template <class Impl>
380template <class T>
381Fault
382}
383
384template <class Impl>
385template <class T>
386Fault
382LSQ<Impl>::write(RequestPtr req, T &data, int store_idx)
387LSQ<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
388 T &data, int store_idx)
383{
384 ThreadID tid = req->threadId();
385
389{
390 ThreadID tid = req->threadId();
391
386 return thread[tid].write(req, data, store_idx);
392 return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx);
387}
388
389#endif // __CPU_O3_LSQ_HH__
393}
394
395#endif // __CPU_O3_LSQ_HH__