lsq.hh (2871:7ed5c9ef3eb6) lsq.hh (2907:7b0ababb4166)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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65 /** Registers statistics of each LSQ unit. */
66 void regStats();
67
68 /** Returns dcache port.
69 * @todo: Dcache port needs to be moved up to this level for SMT
70 * to work. For now it just returns the port from one of the
71 * threads.
72 */
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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65 /** Registers statistics of each LSQ unit. */
66 void regStats();
67
68 /** Returns dcache port.
69 * @todo: Dcache port needs to be moved up to this level for SMT
70 * to work. For now it just returns the port from one of the
71 * threads.
72 */
73 Port *getDcachePort() { return thread[0].getDcachePort(); }
73 Port *getDcachePort() { return &dcachePort; }
74
75 /** Sets the pointer to the list of active threads. */
76 void setActiveThreads(std::list<unsigned> *at_ptr);
77 /** Sets the CPU pointer. */
78 void setCPU(O3CPU *cpu_ptr);
79 /** Sets the IEW stage pointer. */
80 void setIEW(IEW *iew_ptr);
81 /** Switches out the LSQ. */

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253 /** Returns if the LSQ will write back to memory this cycle. */
254 bool willWB();
255 /** Returns if the LSQ of a specific thread will write back to memory this
256 * cycle.
257 */
258 bool willWB(unsigned tid)
259 { return thread[tid].willWB(); }
260
74
75 /** Sets the pointer to the list of active threads. */
76 void setActiveThreads(std::list<unsigned> *at_ptr);
77 /** Sets the CPU pointer. */
78 void setCPU(O3CPU *cpu_ptr);
79 /** Sets the IEW stage pointer. */
80 void setIEW(IEW *iew_ptr);
81 /** Switches out the LSQ. */

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253 /** Returns if the LSQ will write back to memory this cycle. */
254 bool willWB();
255 /** Returns if the LSQ of a specific thread will write back to memory this
256 * cycle.
257 */
258 bool willWB(unsigned tid)
259 { return thread[tid].willWB(); }
260
261 /** Returns if the cache is currently blocked. */
262 bool cacheBlocked()
263 { return retryTid != -1; }
264
265 /** Sets the retry thread id, indicating that one of the LSQUnits
266 * tried to access the cache but the cache was blocked. */
267 void setRetryTid(int tid)
268 { retryTid = tid; }
269
261 /** Debugging function to print out all instructions. */
262 void dumpInsts();
263 /** Debugging function to print out instructions from a specific thread. */
264 void dumpInsts(unsigned tid)
265 { thread[tid].dumpInsts(); }
266
267 /** Executes a read operation, using the load specified at the load index. */
268 template <class T>
269 Fault read(RequestPtr req, T &data, int load_idx);
270
271 /** Executes a store operation, using the store specified at the store
272 * index.
273 */
274 template <class T>
275 Fault write(RequestPtr req, T &data, int store_idx);
276
270 /** Debugging function to print out all instructions. */
271 void dumpInsts();
272 /** Debugging function to print out instructions from a specific thread. */
273 void dumpInsts(unsigned tid)
274 { thread[tid].dumpInsts(); }
275
276 /** Executes a read operation, using the load specified at the load index. */
277 template <class T>
278 Fault read(RequestPtr req, T &data, int load_idx);
279
280 /** Executes a store operation, using the store specified at the store
281 * index.
282 */
283 template <class T>
284 Fault write(RequestPtr req, T &data, int store_idx);
285
277 private:
286 /** DcachePort class for this LSQ. Handles doing the
287 * communication with the cache/memory.
288 */
289 class DcachePort : public Port
290 {
291 protected:
292 /** Pointer to LSQ. */
293 LSQ *lsq;
294
295 public:
296 /** Default constructor. */
297 DcachePort(LSQ *_lsq)
298 : lsq(_lsq)
299 { }
300
301 protected:
302 /** Atomic version of receive. Panics. */
303 virtual Tick recvAtomic(PacketPtr pkt);
304
305 /** Functional version of receive. Panics. */
306 virtual void recvFunctional(PacketPtr pkt);
307
308 /** Receives status change. Other than range changing, panics. */
309 virtual void recvStatusChange(Status status);
310
311 /** Returns the address ranges of this device. */
312 virtual void getDeviceAddressRanges(AddrRangeList &resp,
313 AddrRangeList &snoop)
314 { resp.clear(); snoop.clear(); }
315
316 /** Timing version of receive. Handles writing back and
317 * completing the load or store that has returned from
318 * memory. */
319 virtual bool recvTiming(PacketPtr pkt);
320
321 /** Handles doing a retry of the previous send. */
322 virtual void recvRetry();
323 };
324
325 /** D-cache port. */
326 DcachePort dcachePort;
327
328 protected:
278 /** The LSQ policy for SMT mode. */
279 LSQPolicy lsqPolicy;
280
281 /** The LSQ units for individual threads. */
282 LSQUnit thread[Impl::MaxThreads];
283
284 /** The CPU pointer. */
285 O3CPU *cpu;

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298 /** Max LQ Size - Used to Enforce Sharing Policies. */
299 unsigned maxLQEntries;
300
301 /** Max SQ Size - Used to Enforce Sharing Policies. */
302 unsigned maxSQEntries;
303
304 /** Number of Threads. */
305 unsigned numThreads;
329 /** The LSQ policy for SMT mode. */
330 LSQPolicy lsqPolicy;
331
332 /** The LSQ units for individual threads. */
333 LSQUnit thread[Impl::MaxThreads];
334
335 /** The CPU pointer. */
336 O3CPU *cpu;

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349 /** Max LQ Size - Used to Enforce Sharing Policies. */
350 unsigned maxLQEntries;
351
352 /** Max SQ Size - Used to Enforce Sharing Policies. */
353 unsigned maxSQEntries;
354
355 /** Number of Threads. */
356 unsigned numThreads;
357
358 /** The thread id of the LSQ Unit that is currently waiting for a
359 * retry. */
360 int retryTid;
306};
307
308template <class Impl>
309template <class T>
310Fault
311LSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
312{
313 unsigned tid = req->getThreadNum();

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362
363template <class Impl>
364template <class T>
365Fault
366LSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
367{
368 unsigned tid = req->getThreadNum();

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