lsq.hh (14194:967b9c450b04) lsq.hh (14297:b4519e586f5e)
1/*
2 * Copyright (c) 2011-2012, 2014, 2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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294 std::vector<RequestPtr> _requests;
295 std::vector<Fault> _fault;
296 uint64_t* _res;
297 const Addr _addr;
298 const uint32_t _size;
299 const Request::Flags _flags;
300 std::vector<bool> _byteEnable;
301 uint32_t _numOutstandingPackets;
1/*
2 * Copyright (c) 2011-2012, 2014, 2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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294 std::vector<RequestPtr> _requests;
295 std::vector<Fault> _fault;
296 uint64_t* _res;
297 const Addr _addr;
298 const uint32_t _size;
299 const Request::Flags _flags;
300 std::vector<bool> _byteEnable;
301 uint32_t _numOutstandingPackets;
302 AtomicOpFunctor *_amo_op;
302 AtomicOpFunctorPtr _amo_op;
303 protected:
304 LSQUnit* lsqUnit() { return &_port; }
305 LSQRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad) :
306 _state(State::NotIssued), _senderState(nullptr),
307 _port(*port), _inst(inst), _data(nullptr),
308 _res(nullptr), _addr(0), _size(0), _flags(0),
309 _numOutstandingPackets(0), _amo_op(nullptr)
310 {
311 flags.set(Flag::IsLoad, isLoad);
312 flags.set(Flag::WbStore,
313 _inst->isStoreConditional() || _inst->isAtomic());
314 flags.set(Flag::IsAtomic, _inst->isAtomic());
315 install();
316 }
317 LSQRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad,
318 const Addr& addr, const uint32_t& size,
319 const Request::Flags& flags_,
320 PacketDataPtr data = nullptr, uint64_t* res = nullptr,
303 protected:
304 LSQUnit* lsqUnit() { return &_port; }
305 LSQRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad) :
306 _state(State::NotIssued), _senderState(nullptr),
307 _port(*port), _inst(inst), _data(nullptr),
308 _res(nullptr), _addr(0), _size(0), _flags(0),
309 _numOutstandingPackets(0), _amo_op(nullptr)
310 {
311 flags.set(Flag::IsLoad, isLoad);
312 flags.set(Flag::WbStore,
313 _inst->isStoreConditional() || _inst->isAtomic());
314 flags.set(Flag::IsAtomic, _inst->isAtomic());
315 install();
316 }
317 LSQRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad,
318 const Addr& addr, const uint32_t& size,
319 const Request::Flags& flags_,
320 PacketDataPtr data = nullptr, uint64_t* res = nullptr,
321 AtomicOpFunctor* amo_op = nullptr)
321 AtomicOpFunctorPtr amo_op = nullptr)
322 : _state(State::NotIssued), _senderState(nullptr),
323 numTranslatedFragments(0),
324 numInTranslationFragments(0),
325 _port(*port), _inst(inst), _data(data),
326 _res(res), _addr(addr), _size(size),
327 _flags(flags_),
328 _numOutstandingPackets(0),
322 : _state(State::NotIssued), _senderState(nullptr),
323 numTranslatedFragments(0),
324 numInTranslationFragments(0),
325 _port(*port), _inst(inst), _data(data),
326 _res(res), _addr(addr), _size(size),
327 _flags(flags_),
328 _numOutstandingPackets(0),
329 _amo_op(amo_op)
329 _amo_op(std::move(amo_op))
330 {
331 flags.set(Flag::IsLoad, isLoad);
332 flags.set(Flag::WbStore,
333 _inst->isStoreConditional() || _inst->isAtomic());
334 flags.set(Flag::IsAtomic, _inst->isAtomic());
335 install();
336 }
337

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407 void
408 addRequest(Addr addr, unsigned size,
409 const std::vector<bool>& byteEnable)
410 {
411 if (byteEnable.empty() ||
412 isAnyActiveElement(byteEnable.begin(), byteEnable.end())) {
413 auto request = std::make_shared<Request>(_inst->getASID(),
414 addr, size, _flags, _inst->masterId(),
330 {
331 flags.set(Flag::IsLoad, isLoad);
332 flags.set(Flag::WbStore,
333 _inst->isStoreConditional() || _inst->isAtomic());
334 flags.set(Flag::IsAtomic, _inst->isAtomic());
335 install();
336 }
337

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407 void
408 addRequest(Addr addr, unsigned size,
409 const std::vector<bool>& byteEnable)
410 {
411 if (byteEnable.empty() ||
412 isAnyActiveElement(byteEnable.begin(), byteEnable.end())) {
413 auto request = std::make_shared<Request>(_inst->getASID(),
414 addr, size, _flags, _inst->masterId(),
415 _inst->instAddr(), _inst->contextId(), _amo_op);
415 _inst->instAddr(), _inst->contextId(),
416 std::move(_amo_op));
416 if (!byteEnable.empty()) {
417 request->setByteEnable(byteEnable);
418 }
419 _requests.push_back(request);
420 }
421 }
422
423 /** Destructor.

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716 using LSQRequest::_numOutstandingPackets;
717 using LSQRequest::_amo_op;
718 public:
719 SingleDataRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad,
720 const Addr& addr, const uint32_t& size,
721 const Request::Flags& flags_,
722 PacketDataPtr data = nullptr,
723 uint64_t* res = nullptr,
417 if (!byteEnable.empty()) {
418 request->setByteEnable(byteEnable);
419 }
420 _requests.push_back(request);
421 }
422 }
423
424 /** Destructor.

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717 using LSQRequest::_numOutstandingPackets;
718 using LSQRequest::_amo_op;
719 public:
720 SingleDataRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad,
721 const Addr& addr, const uint32_t& size,
722 const Request::Flags& flags_,
723 PacketDataPtr data = nullptr,
724 uint64_t* res = nullptr,
724 AtomicOpFunctor* amo_op = nullptr) :
725 AtomicOpFunctorPtr amo_op = nullptr) :
725 LSQRequest(port, inst, isLoad, addr, size, flags_, data, res,
726 LSQRequest(port, inst, isLoad, addr, size, flags_, data, res,
726 amo_op) {}
727 std::move(amo_op)) {}
727
728 inline virtual ~SingleDataRequest() {}
729 virtual void initiateTranslation();
730 virtual void finish(const Fault &fault, const RequestPtr &req,
731 ThreadContext* tc, BaseTLB::Mode mode);
732 virtual bool recvTimingResp(PacketPtr pkt);
733 virtual void sendPacketToCache();
734 virtual void buildPackets();

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1027 * @param pkt Response packet from the memory sub-system
1028 */
1029 bool recvTimingResp(PacketPtr pkt);
1030
1031 void recvTimingSnoopReq(PacketPtr pkt);
1032
1033 Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
1034 unsigned int size, Addr addr, Request::Flags flags,
728
729 inline virtual ~SingleDataRequest() {}
730 virtual void initiateTranslation();
731 virtual void finish(const Fault &fault, const RequestPtr &req,
732 ThreadContext* tc, BaseTLB::Mode mode);
733 virtual bool recvTimingResp(PacketPtr pkt);
734 virtual void sendPacketToCache();
735 virtual void buildPackets();

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1028 * @param pkt Response packet from the memory sub-system
1029 */
1030 bool recvTimingResp(PacketPtr pkt);
1031
1032 void recvTimingSnoopReq(PacketPtr pkt);
1033
1034 Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
1035 unsigned int size, Addr addr, Request::Flags flags,
1035 uint64_t *res, AtomicOpFunctor *amo_op,
1036 uint64_t *res, AtomicOpFunctorPtr amo_op,
1036 const std::vector<bool>& byteEnable);
1037
1038 /** The CPU pointer. */
1039 O3CPU *cpu;
1040
1041 /** The IEW stage pointer. */
1042 IEW *iewStage;
1043

--- 93 unchanged lines hidden --- 		1037 const std::vector<bool>& byteEnable);
1038
1039 /** The CPU pointer. */
1040 O3CPU *cpu;
1041
1042 /** The IEW stage pointer. */
1043 IEW *iewStage;
1044

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