lsq.hh (13710:5ba1d8066ef0) lsq.hh (13954:2f400a5f2627)
1/*
2 * Copyright (c) 2011-2012, 2014, 2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 36 unchanged lines hidden (view full) ---

45#define __CPU_O3_LSQ_HH__
46
47#include <map>
48#include <queue>
49
50#include "arch/generic/tlb.hh"
51#include "cpu/inst_seq.hh"
52#include "cpu/o3/lsq_unit.hh"
1/*
2 * Copyright (c) 2011-2012, 2014, 2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 36 unchanged lines hidden (view full) ---

45#define __CPU_O3_LSQ_HH__
46
47#include <map>
48#include <queue>
49
50#include "arch/generic/tlb.hh"
51#include "cpu/inst_seq.hh"
52#include "cpu/o3/lsq_unit.hh"
53#include "cpu/utils.hh"
53#include "enums/SMTQueuePolicy.hh"
54#include "mem/port.hh"
55#include "sim/sim_object.hh"
56
57struct DerivO3CPUParams;
58
59template <class Impl>
60class LSQ

--- 185 unchanged lines hidden (view full) ---

246 PacketDataPtr _data;
247 std::vector<PacketPtr> _packets;
248 std::vector<RequestPtr> _requests;
249 std::vector<Fault> _fault;
250 uint64_t* _res;
251 const Addr _addr;
252 const uint32_t _size;
253 const Request::Flags _flags;
54#include "enums/SMTQueuePolicy.hh"
55#include "mem/port.hh"
56#include "sim/sim_object.hh"
57
58struct DerivO3CPUParams;
59
60template <class Impl>
61class LSQ

--- 185 unchanged lines hidden (view full) ---

247 PacketDataPtr _data;
248 std::vector<PacketPtr> _packets;
249 std::vector<RequestPtr> _requests;
250 std::vector<Fault> _fault;
251 uint64_t* _res;
252 const Addr _addr;
253 const uint32_t _size;
254 const Request::Flags _flags;
255 std::vector<bool> _byteEnable;
254 uint32_t _numOutstandingPackets;
255 AtomicOpFunctor *_amo_op;
256 protected:
257 LSQUnit* lsqUnit() { return &_port; }
258 LSQRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad) :
259 _state(State::NotIssued), _senderState(nullptr),
260 _port(*port), _inst(inst), _data(nullptr),
261 _res(nullptr), _addr(0), _size(0), _flags(0),

--- 84 unchanged lines hidden (view full) ---

346 } else {
347 if (_senderState) {
348 _senderState->deleteRequest();
349 }
350 flags.set(reason);
351 }
352 }
353
256 uint32_t _numOutstandingPackets;
257 AtomicOpFunctor *_amo_op;
258 protected:
259 LSQUnit* lsqUnit() { return &_port; }
260 LSQRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad) :
261 _state(State::NotIssued), _senderState(nullptr),
262 _port(*port), _inst(inst), _data(nullptr),
263 _res(nullptr), _addr(0), _size(0), _flags(0),

--- 84 unchanged lines hidden (view full) ---

348 } else {
349 if (_senderState) {
350 _senderState->deleteRequest();
351 }
352 flags.set(reason);
353 }
354 }
355
356 /** Helper function used to add a (sub)request, given its address
357 * `addr`, size `size` and byte-enable mask `byteEnable`.
358 *
359 * The request is only added if the mask is empty or if there is at
360 * least an active element in it.
361 */
362 void
363 addRequest(Addr addr, unsigned size,
364 const std::vector<bool>& byteEnable)
365 {
366 if (byteEnable.empty() ||
367 isAnyActiveElement(byteEnable.begin(), byteEnable.end())) {
368 auto request = std::make_shared<Request>(_inst->getASID(),
369 addr, size, _flags, _inst->masterId(),
370 _inst->instAddr(), _inst->contextId());
371 if (!byteEnable.empty()) {
372 request->setByteEnable(byteEnable);
373 }
374 _requests.push_back(request);
375 }
376 }
377
354 /** Destructor.
355 * The LSQRequest owns the request. If the packet has already been
356 * sent, the sender state will be deleted upon receiving the reply.
357 */
358 virtual ~LSQRequest()
359 {
360 assert(!isAnyOutstandingRequest());
361 _inst->savedReq = nullptr;

--- 242 unchanged lines hidden (view full) ---

604
605 class SingleDataRequest : public LSQRequest
606 {
607 protected:
608 /* Given that we are inside templates, children need explicit
609 * declaration of the names in the parent class. */
610 using Flag = typename LSQRequest::Flag;
611 using State = typename LSQRequest::State;
378 /** Destructor.
379 * The LSQRequest owns the request. If the packet has already been
380 * sent, the sender state will be deleted upon receiving the reply.
381 */
382 virtual ~LSQRequest()
383 {
384 assert(!isAnyOutstandingRequest());
385 _inst->savedReq = nullptr;

--- 242 unchanged lines hidden (view full) ---

628
629 class SingleDataRequest : public LSQRequest
630 {
631 protected:
632 /* Given that we are inside templates, children need explicit
633 * declaration of the names in the parent class. */
634 using Flag = typename LSQRequest::Flag;
635 using State = typename LSQRequest::State;
636 using LSQRequest::_addr;
612 using LSQRequest::_fault;
637 using LSQRequest::_fault;
638 using LSQRequest::_flags;
639 using LSQRequest::_size;
640 using LSQRequest::_byteEnable;
641 using LSQRequest::_requests;
613 using LSQRequest::_inst;
614 using LSQRequest::_packets;
615 using LSQRequest::_port;
616 using LSQRequest::_res;
642 using LSQRequest::_inst;
643 using LSQRequest::_packets;
644 using LSQRequest::_port;
645 using LSQRequest::_res;
646 using LSQRequest::_taskId;
617 using LSQRequest::_senderState;
618 using LSQRequest::_state;
619 using LSQRequest::flags;
620 using LSQRequest::isLoad;
621 using LSQRequest::isTranslationComplete;
622 using LSQRequest::lsqUnit;
623 using LSQRequest::request;
624 using LSQRequest::sendFragmentToTranslation;

--- 5 unchanged lines hidden (view full) ---

630 public:
631 SingleDataRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad,
632 const Addr& addr, const uint32_t& size,
633 const Request::Flags& flags_,
634 PacketDataPtr data = nullptr,
635 uint64_t* res = nullptr,
636 AtomicOpFunctor* amo_op = nullptr) :
637 LSQRequest(port, inst, isLoad, addr, size, flags_, data, res,
647 using LSQRequest::_senderState;
648 using LSQRequest::_state;
649 using LSQRequest::flags;
650 using LSQRequest::isLoad;
651 using LSQRequest::isTranslationComplete;
652 using LSQRequest::lsqUnit;
653 using LSQRequest::request;
654 using LSQRequest::sendFragmentToTranslation;

--- 5 unchanged lines hidden (view full) ---

660 public:
661 SingleDataRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad,
662 const Addr& addr, const uint32_t& size,
663 const Request::Flags& flags_,
664 PacketDataPtr data = nullptr,
665 uint64_t* res = nullptr,
666 AtomicOpFunctor* amo_op = nullptr) :
667 LSQRequest(port, inst, isLoad, addr, size, flags_, data, res,
638 amo_op)
639 {
640 LSQRequest::_requests.push_back(
641 std::make_shared<Request>(inst->getASID(), addr, size,
642 flags_, inst->masterId(), inst->instAddr(),
643 inst->contextId(), amo_op));
644 LSQRequest::_requests.back()->setReqInstSeqNum(inst->seqNum);
645 }
668 amo_op) {}
669
646 inline virtual ~SingleDataRequest() {}
647 virtual void initiateTranslation();
648 virtual void finish(const Fault &fault, const RequestPtr &req,
649 ThreadContext* tc, BaseTLB::Mode mode);
650 virtual bool recvTimingResp(PacketPtr pkt);
651 virtual void sendPacketToCache();
652 virtual void buildPackets();
653 virtual void handleIprWrite(ThreadContext *thread, PacketPtr pkt);

--- 12 unchanged lines hidden (view full) ---

666 using LSQRequest::_data;
667 using LSQRequest::_fault;
668 using LSQRequest::_flags;
669 using LSQRequest::_inst;
670 using LSQRequest::_packets;
671 using LSQRequest::_port;
672 using LSQRequest::_requests;
673 using LSQRequest::_res;
670 inline virtual ~SingleDataRequest() {}
671 virtual void initiateTranslation();
672 virtual void finish(const Fault &fault, const RequestPtr &req,
673 ThreadContext* tc, BaseTLB::Mode mode);
674 virtual bool recvTimingResp(PacketPtr pkt);
675 virtual void sendPacketToCache();
676 virtual void buildPackets();
677 virtual void handleIprWrite(ThreadContext *thread, PacketPtr pkt);

--- 12 unchanged lines hidden (view full) ---

690 using LSQRequest::_data;
691 using LSQRequest::_fault;
692 using LSQRequest::_flags;
693 using LSQRequest::_inst;
694 using LSQRequest::_packets;
695 using LSQRequest::_port;
696 using LSQRequest::_requests;
697 using LSQRequest::_res;
698 using LSQRequest::_byteEnable;
674 using LSQRequest::_senderState;
675 using LSQRequest::_size;
676 using LSQRequest::_state;
677 using LSQRequest::_taskId;
678 using LSQRequest::flags;
679 using LSQRequest::isLoad;
680 using LSQRequest::isTranslationComplete;
681 using LSQRequest::lsqUnit;

--- 4 unchanged lines hidden (view full) ---

686 using LSQRequest::setState;
687 using LSQRequest::_numOutstandingPackets;
688
689 uint32_t numFragments;
690 uint32_t numReceivedPackets;
691 RequestPtr mainReq;
692 PacketPtr _mainPacket;
693
699 using LSQRequest::_senderState;
700 using LSQRequest::_size;
701 using LSQRequest::_state;
702 using LSQRequest::_taskId;
703 using LSQRequest::flags;
704 using LSQRequest::isLoad;
705 using LSQRequest::isTranslationComplete;
706 using LSQRequest::lsqUnit;

--- 4 unchanged lines hidden (view full) ---

711 using LSQRequest::setState;
712 using LSQRequest::_numOutstandingPackets;
713
714 uint32_t numFragments;
715 uint32_t numReceivedPackets;
716 RequestPtr mainReq;
717 PacketPtr _mainPacket;
718
694
695 public:
696 SplitDataRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad,
697 const Addr& addr, const uint32_t& size,
698 const Request::Flags & flags_,
699 PacketDataPtr data = nullptr,
700 uint64_t* res = nullptr) :
719 public:
720 SplitDataRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad,
721 const Addr& addr, const uint32_t& size,
722 const Request::Flags & flags_,
723 PacketDataPtr data = nullptr,
724 uint64_t* res = nullptr) :
701 LSQRequest(port, inst, isLoad, addr, size, flags_, data, res),
725 LSQRequest(port, inst, isLoad, addr, size, flags_, data, res,
726 nullptr),
702 numFragments(0),
703 numReceivedPackets(0),
704 mainReq(nullptr),
705 _mainPacket(nullptr)
706 {
707 flags.set(Flag::IsSplit);
708 }
709 virtual ~SplitDataRequest()

--- 234 unchanged lines hidden (view full) ---

944 * @param pkt Response packet from the memory sub-system
945 */
946 bool recvTimingResp(PacketPtr pkt);
947
948 void recvTimingSnoopReq(PacketPtr pkt);
949
950 Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
951 unsigned int size, Addr addr, Request::Flags flags,
727 numFragments(0),
728 numReceivedPackets(0),
729 mainReq(nullptr),
730 _mainPacket(nullptr)
731 {
732 flags.set(Flag::IsSplit);
733 }
734 virtual ~SplitDataRequest()

--- 234 unchanged lines hidden (view full) ---

969 * @param pkt Response packet from the memory sub-system
970 */
971 bool recvTimingResp(PacketPtr pkt);
972
973 void recvTimingSnoopReq(PacketPtr pkt);
974
975 Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
976 unsigned int size, Addr addr, Request::Flags flags,
952 uint64_t *res, AtomicOpFunctor *amo_op);
977 uint64_t *res, AtomicOpFunctor *amo_op,
978 const std::vector<bool>& byteEnable);
953
954 /** The CPU pointer. */
955 O3CPU *cpu;
956
957 /** The IEW stage pointer. */
958 IEW *iewStage;
959
960 /** Is D-cache blocked? */

--- 87 unchanged lines hidden --- 		979
980 /** The CPU pointer. */
981 O3CPU *cpu;
982
983 /** The IEW stage pointer. */
984 IEW *iewStage;
985
986 /** Is D-cache blocked? */

--- 87 unchanged lines hidden ---