lsq.hh (13652:45d94ac03a27) lsq.hh (13710:5ba1d8066ef0)
1/*
2 * Copyright (c) 2011-2012, 2014, 2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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750 bool isDrained() const;
751 /** Takes over execution from another CPU's thread. */
752 void takeOverFrom();
753
754 /** Number of entries needed for the given amount of threads.*/
755 int entryAmount(ThreadID num_threads);
756
757 /** Ticks the LSQ. */
1/*
2 * Copyright (c) 2011-2012, 2014, 2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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750 bool isDrained() const;
751 /** Takes over execution from another CPU's thread. */
752 void takeOverFrom();
753
754 /** Number of entries needed for the given amount of threads.*/
755 int entryAmount(ThreadID num_threads);
756
757 /** Ticks the LSQ. */
758 void tick() { usedStorePorts = 0; }
758 void tick();
759
760 /** Inserts a load into the LSQ. */
761 void insertLoad(const DynInstPtr &load_inst);
762 /** Inserts a store into the LSQ. */
763 void insertStore(const DynInstPtr &store_inst);
764
765 /** Executes a load. */
766 Fault executeLoad(const DynInstPtr &inst);

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957 /** The IEW stage pointer. */
958 IEW *iewStage;
959
960 /** Is D-cache blocked? */
961 bool cacheBlocked() const;
962 /** Set D-cache blocked status */
963 void cacheBlocked(bool v);
964 /** Is any store port available to use? */
759
760 /** Inserts a load into the LSQ. */
761 void insertLoad(const DynInstPtr &load_inst);
762 /** Inserts a store into the LSQ. */
763 void insertStore(const DynInstPtr &store_inst);
764
765 /** Executes a load. */
766 Fault executeLoad(const DynInstPtr &inst);

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957 /** The IEW stage pointer. */
958 IEW *iewStage;
959
960 /** Is D-cache blocked? */
961 bool cacheBlocked() const;
962 /** Set D-cache blocked status */
963 void cacheBlocked(bool v);
964 /** Is any store port available to use? */
965 bool storePortAvailable() const;
965 bool cachePortAvailable(bool is_load) const;
966 /** Another store port is in use */
966 /** Another store port is in use */
967 void storePortBusy();
967 void cachePortBusy(bool is_load);
968
969 protected:
970 /** D-cache is blocked */
971 bool _cacheBlocked;
972 /** The number of cache ports available each cycle (stores only). */
973 int cacheStorePorts;
974 /** The number of used cache ports in this cycle by stores. */
975 int usedStorePorts;
968
969 protected:
970 /** D-cache is blocked */
971 bool _cacheBlocked;
972 /** The number of cache ports available each cycle (stores only). */
973 int cacheStorePorts;
974 /** The number of used cache ports in this cycle by stores. */
975 int usedStorePorts;
976 /** The number of cache ports available each cycle (loads only). */
977 int cacheLoadPorts;
978 /** The number of used cache ports in this cycle by loads. */
979 int usedLoadPorts;
976
977
978 /** The LSQ policy for SMT mode. */
979 SMTQueuePolicy lsqPolicy;
980
981 /** Auxiliary function to calculate per-thread max LSQ allocation limit.
982 * Depending on a policy, number of entries and possibly number of threads
983 * and threshold, this function calculates how many resources each thread

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980
981
982 /** The LSQ policy for SMT mode. */
983 SMTQueuePolicy lsqPolicy;
984
985 /** Auxiliary function to calculate per-thread max LSQ allocation limit.
986 * Depending on a policy, number of entries and possibly number of threads
987 * and threshold, this function calculates how many resources each thread

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