lsq.hh (11435:0f1b46dde3fa) | lsq.hh (12749:223c83ed9979) |
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1/* 2 * Copyright (c) 2011-2012, 2014 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 260 unchanged lines hidden (view full) --- 269 void dumpInsts() const; 270 /** Debugging function to print out instructions from a specific thread. */ 271 void dumpInsts(ThreadID tid) const 272 { thread[tid].dumpInsts(); } 273 274 /** Executes a read operation, using the load specified at the load 275 * index. 276 */ | 1/* 2 * Copyright (c) 2011-2012, 2014 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 260 unchanged lines hidden (view full) --- 269 void dumpInsts() const; 270 /** Debugging function to print out instructions from a specific thread. */ 271 void dumpInsts(ThreadID tid) const 272 { thread[tid].dumpInsts(); } 273 274 /** Executes a read operation, using the load specified at the load 275 * index. 276 */ |
277 Fault read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, | 277 Fault read(const RequestPtr &req, 278 RequestPtr &sreqLow, RequestPtr &sreqHigh, |
278 int load_idx); 279 280 /** Executes a store operation, using the store specified at the store 281 * index. 282 */ | 279 int load_idx); 280 281 /** Executes a store operation, using the store specified at the store 282 * index. 283 */ |
283 Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, | 284 Fault write(const RequestPtr &req, 285 const RequestPtr &sreqLow, const RequestPtr &sreqHigh, |
284 uint8_t *data, int store_idx); 285 286 /** 287 * Retry the previous send that failed. 288 */ 289 void recvReqRetry(); 290 291 /** --- 34 unchanged lines hidden (view full) --- 326 unsigned maxSQEntries; 327 328 /** Number of Threads. */ 329 ThreadID numThreads; 330}; 331 332template <class Impl> 333Fault | 286 uint8_t *data, int store_idx); 287 288 /** 289 * Retry the previous send that failed. 290 */ 291 void recvReqRetry(); 292 293 /** --- 34 unchanged lines hidden (view full) --- 328 unsigned maxSQEntries; 329 330 /** Number of Threads. */ 331 ThreadID numThreads; 332}; 333 334template <class Impl> 335Fault |
334LSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, | 336LSQ<Impl>::read(const RequestPtr &req, 337 RequestPtr &sreqLow, RequestPtr &sreqHigh, |
335 int load_idx) 336{ 337 ThreadID tid = cpu->contextToThread(req->contextId()); 338 339 return thread[tid].read(req, sreqLow, sreqHigh, load_idx); 340} 341 342template <class Impl> 343Fault | 338 int load_idx) 339{ 340 ThreadID tid = cpu->contextToThread(req->contextId()); 341 342 return thread[tid].read(req, sreqLow, sreqHigh, load_idx); 343} 344 345template <class Impl> 346Fault |
344LSQ<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, | 347LSQ<Impl>::write(const RequestPtr &req, 348 const RequestPtr &sreqLow, const RequestPtr &sreqHigh, |
345 uint8_t *data, int store_idx) 346{ 347 ThreadID tid = cpu->contextToThread(req->contextId()); 348 349 return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx); 350} 351 352#endif // __CPU_O3_LSQ_HH__ | 349 uint8_t *data, int store_idx) 350{ 351 ThreadID tid = cpu->contextToThread(req->contextId()); 352 353 return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx); 354} 355 356#endif // __CPU_O3_LSQ_HH__ |