| lsq.hh (10713:eddb533708cb) | lsq.hh (11302:bce9037689b0) |
|---|---|
| 1/* 2 * Copyright (c) 2011-2012, 2014 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 261 unchanged lines hidden (view full) --- 270 /** Debugging function to print out instructions from a specific thread. */ 271 void dumpInsts(ThreadID tid) const 272 { thread[tid].dumpInsts(); } 273 274 /** Executes a read operation, using the load specified at the load 275 * index. 276 */ 277 Fault read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, | 1/* 2 * Copyright (c) 2011-2012, 2014 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 261 unchanged lines hidden (view full) --- 270 /** Debugging function to print out instructions from a specific thread. */ 271 void dumpInsts(ThreadID tid) const 272 { thread[tid].dumpInsts(); } 273 274 /** Executes a read operation, using the load specified at the load 275 * index. 276 */ 277 Fault read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, |
| 278 uint8_t *data, int load_idx); | 278 int load_idx); |
| 279 280 /** Executes a store operation, using the store specified at the store 281 * index. 282 */ 283 Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 284 uint8_t *data, int store_idx); 285 286 /** --- 40 unchanged lines hidden (view full) --- 327 328 /** Number of Threads. */ 329 ThreadID numThreads; 330}; 331 332template <class Impl> 333Fault 334LSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, | 279 280 /** Executes a store operation, using the store specified at the store 281 * index. 282 */ 283 Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 284 uint8_t *data, int store_idx); 285 286 /** --- 40 unchanged lines hidden (view full) --- 327 328 /** Number of Threads. */ 329 ThreadID numThreads; 330}; 331 332template <class Impl> 333Fault 334LSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, |
| 335 uint8_t *data, int load_idx) | 335 int load_idx) |
| 336{ 337 ThreadID tid = req->threadId(); 338 | 336{ 337 ThreadID tid = req->threadId(); 338 |
| 339 return thread[tid].read(req, sreqLow, sreqHigh, data, load_idx); | 339 return thread[tid].read(req, sreqLow, sreqHigh, load_idx); |
| 340} 341 342template <class Impl> 343Fault 344LSQ<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 345 uint8_t *data, int store_idx) 346{ 347 ThreadID tid = req->threadId(); 348 349 return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx); 350} 351 352#endif // __CPU_O3_LSQ_HH__ | 340} 341 342template <class Impl> 343Fault 344LSQ<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, 345 uint8_t *data, int store_idx) 346{ 347 ThreadID tid = req->threadId(); 348 349 return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx); 350} 351 352#endif // __CPU_O3_LSQ_HH__ |