1/*
2 * Copyright (c) 2011-2012 ARM Limited
| 1/*
2 * Copyright (c) 2011-2012 ARM Limited
|
| 3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
|
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Korey Sewell
41 */
42
43#ifndef __CPU_O3_LSQ_HH__
44#define __CPU_O3_LSQ_HH__
45
46#include <map>
47#include <queue>
48
49#include "cpu/o3/lsq_unit.hh"
50#include "cpu/inst_seq.hh"
51#include "mem/port.hh"
52#include "sim/sim_object.hh"
53
54struct DerivO3CPUParams;
55
56template <class Impl>
57class LSQ {
58 public:
59 typedef typename Impl::O3CPU O3CPU;
60 typedef typename Impl::DynInstPtr DynInstPtr;
61 typedef typename Impl::CPUPol::IEW IEW;
62 typedef typename Impl::CPUPol::LSQUnit LSQUnit;
63
64 /** SMT policy. */
65 enum LSQPolicy {
66 Dynamic,
67 Partitioned,
68 Threshold
69 };
70
71 /** Constructs an LSQ with the given parameters. */
72 LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params);
73 ~LSQ() {
74 if (thread) delete [] thread;
75 }
76
77 /** Returns the name of the LSQ. */
78 std::string name() const;
79
80 /** Registers statistics of each LSQ unit. */
81 void regStats();
82
83 /** Sets the pointer to the list of active threads. */
84 void setActiveThreads(std::list<ThreadID> *at_ptr);
85
86 /** Perform sanity checks after a drain. */
87 void drainSanityCheck() const;
88 /** Has the LSQ drained? */
89 bool isDrained() const;
90 /** Takes over execution from another CPU's thread. */
91 void takeOverFrom();
92
93 /** Number of entries needed for the given amount of threads.*/
94 int entryAmount(ThreadID num_threads);
95 void removeEntries(ThreadID tid);
96 /** Reset the max entries for each thread. */
97 void resetEntries();
98 /** Resize the max entries for a thread. */
99 void resizeEntries(unsigned size, ThreadID tid);
100
101 /** Ticks the LSQ. */
102 void tick();
103 /** Ticks a specific LSQ Unit. */
104 void tick(ThreadID tid)
105 { thread[tid].tick(); }
106
107 /** Inserts a load into the LSQ. */
108 void insertLoad(DynInstPtr &load_inst);
109 /** Inserts a store into the LSQ. */
110 void insertStore(DynInstPtr &store_inst);
111
112 /** Executes a load. */
113 Fault executeLoad(DynInstPtr &inst);
114
115 /** Executes a store. */
116 Fault executeStore(DynInstPtr &inst);
117
118 /**
119 * Commits loads up until the given sequence number for a specific thread.
120 */
121 void commitLoads(InstSeqNum &youngest_inst, ThreadID tid)
122 { thread[tid].commitLoads(youngest_inst); }
123
124 /**
125 * Commits stores up until the given sequence number for a specific thread.
126 */
127 void commitStores(InstSeqNum &youngest_inst, ThreadID tid)
128 { thread[tid].commitStores(youngest_inst); }
129
130 /**
131 * Attempts to write back stores until all cache ports are used or the
132 * interface becomes blocked.
133 */
134 void writebackStores();
135 /** Same as above, but only for one thread. */
136 void writebackStores(ThreadID tid);
137
138 /**
139 * Squash instructions from a thread until the specified sequence number.
140 */
141 void squash(const InstSeqNum &squashed_num, ThreadID tid)
142 { thread[tid].squash(squashed_num); }
143
144 /** Returns whether or not there was a memory ordering violation. */
145 bool violation();
146 /**
147 * Returns whether or not there was a memory ordering violation for a
148 * specific thread.
149 */
150 bool violation(ThreadID tid)
151 { return thread[tid].violation(); }
152
153 /** Returns if a load is blocked due to the memory system for a specific
154 * thread.
155 */
156 bool loadBlocked(ThreadID tid)
157 { return thread[tid].loadBlocked(); }
158
159 bool isLoadBlockedHandled(ThreadID tid)
160 { return thread[tid].isLoadBlockedHandled(); }
161
162 void setLoadBlockedHandled(ThreadID tid)
163 { thread[tid].setLoadBlockedHandled(); }
164
165 /** Gets the instruction that caused the memory ordering violation. */
166 DynInstPtr getMemDepViolator(ThreadID tid)
167 { return thread[tid].getMemDepViolator(); }
168
169 /** Returns the head index of the load queue for a specific thread. */
170 int getLoadHead(ThreadID tid)
171 { return thread[tid].getLoadHead(); }
172
173 /** Returns the sequence number of the head of the load queue. */
174 InstSeqNum getLoadHeadSeqNum(ThreadID tid)
175 {
176 return thread[tid].getLoadHeadSeqNum();
177 }
178
179 /** Returns the head index of the store queue. */
180 int getStoreHead(ThreadID tid)
181 { return thread[tid].getStoreHead(); }
182
183 /** Returns the sequence number of the head of the store queue. */
184 InstSeqNum getStoreHeadSeqNum(ThreadID tid)
185 {
186 return thread[tid].getStoreHeadSeqNum();
187 }
188
189 /** Returns the number of instructions in all of the queues. */
190 int getCount();
191 /** Returns the number of instructions in the queues of one thread. */
192 int getCount(ThreadID tid)
193 { return thread[tid].getCount(); }
194
195 /** Returns the total number of loads in the load queue. */
196 int numLoads();
197 /** Returns the total number of loads for a single thread. */
198 int numLoads(ThreadID tid)
199 { return thread[tid].numLoads(); }
200
201 /** Returns the total number of stores in the store queue. */
202 int numStores();
203 /** Returns the total number of stores for a single thread. */
204 int numStores(ThreadID tid)
205 { return thread[tid].numStores(); }
206
| 4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Korey Sewell
42 */
43
44#ifndef __CPU_O3_LSQ_HH__
45#define __CPU_O3_LSQ_HH__
46
47#include <map>
48#include <queue>
49
50#include "cpu/o3/lsq_unit.hh"
51#include "cpu/inst_seq.hh"
52#include "mem/port.hh"
53#include "sim/sim_object.hh"
54
55struct DerivO3CPUParams;
56
57template <class Impl>
58class LSQ {
59 public:
60 typedef typename Impl::O3CPU O3CPU;
61 typedef typename Impl::DynInstPtr DynInstPtr;
62 typedef typename Impl::CPUPol::IEW IEW;
63 typedef typename Impl::CPUPol::LSQUnit LSQUnit;
64
65 /** SMT policy. */
66 enum LSQPolicy {
67 Dynamic,
68 Partitioned,
69 Threshold
70 };
71
72 /** Constructs an LSQ with the given parameters. */
73 LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params);
74 ~LSQ() {
75 if (thread) delete [] thread;
76 }
77
78 /** Returns the name of the LSQ. */
79 std::string name() const;
80
81 /** Registers statistics of each LSQ unit. */
82 void regStats();
83
84 /** Sets the pointer to the list of active threads. */
85 void setActiveThreads(std::list<ThreadID> *at_ptr);
86
87 /** Perform sanity checks after a drain. */
88 void drainSanityCheck() const;
89 /** Has the LSQ drained? */
90 bool isDrained() const;
91 /** Takes over execution from another CPU's thread. */
92 void takeOverFrom();
93
94 /** Number of entries needed for the given amount of threads.*/
95 int entryAmount(ThreadID num_threads);
96 void removeEntries(ThreadID tid);
97 /** Reset the max entries for each thread. */
98 void resetEntries();
99 /** Resize the max entries for a thread. */
100 void resizeEntries(unsigned size, ThreadID tid);
101
102 /** Ticks the LSQ. */
103 void tick();
104 /** Ticks a specific LSQ Unit. */
105 void tick(ThreadID tid)
106 { thread[tid].tick(); }
107
108 /** Inserts a load into the LSQ. */
109 void insertLoad(DynInstPtr &load_inst);
110 /** Inserts a store into the LSQ. */
111 void insertStore(DynInstPtr &store_inst);
112
113 /** Executes a load. */
114 Fault executeLoad(DynInstPtr &inst);
115
116 /** Executes a store. */
117 Fault executeStore(DynInstPtr &inst);
118
119 /**
120 * Commits loads up until the given sequence number for a specific thread.
121 */
122 void commitLoads(InstSeqNum &youngest_inst, ThreadID tid)
123 { thread[tid].commitLoads(youngest_inst); }
124
125 /**
126 * Commits stores up until the given sequence number for a specific thread.
127 */
128 void commitStores(InstSeqNum &youngest_inst, ThreadID tid)
129 { thread[tid].commitStores(youngest_inst); }
130
131 /**
132 * Attempts to write back stores until all cache ports are used or the
133 * interface becomes blocked.
134 */
135 void writebackStores();
136 /** Same as above, but only for one thread. */
137 void writebackStores(ThreadID tid);
138
139 /**
140 * Squash instructions from a thread until the specified sequence number.
141 */
142 void squash(const InstSeqNum &squashed_num, ThreadID tid)
143 { thread[tid].squash(squashed_num); }
144
145 /** Returns whether or not there was a memory ordering violation. */
146 bool violation();
147 /**
148 * Returns whether or not there was a memory ordering violation for a
149 * specific thread.
150 */
151 bool violation(ThreadID tid)
152 { return thread[tid].violation(); }
153
154 /** Returns if a load is blocked due to the memory system for a specific
155 * thread.
156 */
157 bool loadBlocked(ThreadID tid)
158 { return thread[tid].loadBlocked(); }
159
160 bool isLoadBlockedHandled(ThreadID tid)
161 { return thread[tid].isLoadBlockedHandled(); }
162
163 void setLoadBlockedHandled(ThreadID tid)
164 { thread[tid].setLoadBlockedHandled(); }
165
166 /** Gets the instruction that caused the memory ordering violation. */
167 DynInstPtr getMemDepViolator(ThreadID tid)
168 { return thread[tid].getMemDepViolator(); }
169
170 /** Returns the head index of the load queue for a specific thread. */
171 int getLoadHead(ThreadID tid)
172 { return thread[tid].getLoadHead(); }
173
174 /** Returns the sequence number of the head of the load queue. */
175 InstSeqNum getLoadHeadSeqNum(ThreadID tid)
176 {
177 return thread[tid].getLoadHeadSeqNum();
178 }
179
180 /** Returns the head index of the store queue. */
181 int getStoreHead(ThreadID tid)
182 { return thread[tid].getStoreHead(); }
183
184 /** Returns the sequence number of the head of the store queue. */
185 InstSeqNum getStoreHeadSeqNum(ThreadID tid)
186 {
187 return thread[tid].getStoreHeadSeqNum();
188 }
189
190 /** Returns the number of instructions in all of the queues. */
191 int getCount();
192 /** Returns the number of instructions in the queues of one thread. */
193 int getCount(ThreadID tid)
194 { return thread[tid].getCount(); }
195
196 /** Returns the total number of loads in the load queue. */
197 int numLoads();
198 /** Returns the total number of loads for a single thread. */
199 int numLoads(ThreadID tid)
200 { return thread[tid].numLoads(); }
201
202 /** Returns the total number of stores in the store queue. */
203 int numStores();
204 /** Returns the total number of stores for a single thread. */
205 int numStores(ThreadID tid)
206 { return thread[tid].numStores(); }
207
|
207 /** Returns the number of free entries. */
208 unsigned numFreeEntries();
| 208 /** Returns the number of free load entries. */
209 unsigned numFreeLoadEntries();
210
211 /** Returns the number of free store entries. */
212 unsigned numFreeStoreEntries();
213
|
209 /** Returns the number of free entries for a specific thread. */
210 unsigned numFreeEntries(ThreadID tid);
211
| 214 /** Returns the number of free entries for a specific thread. */
215 unsigned numFreeEntries(ThreadID tid);
216
|
| 217 /** Returns the number of free entries in the LQ for a specific thread. */
218 unsigned numFreeLoadEntries(ThreadID tid);
219
220 /** Returns the number of free entries in the SQ for a specific thread. */
221 unsigned numFreeStoreEntries(ThreadID tid);
222
|
212 /** Returns if the LSQ is full (either LQ or SQ is full). */
213 bool isFull();
214 /**
215 * Returns if the LSQ is full for a specific thread (either LQ or SQ is
216 * full).
217 */
218 bool isFull(ThreadID tid);
219
220 /** Returns if the LSQ is empty (both LQ and SQ are empty). */
221 bool isEmpty() const;
222 /** Returns if all of the LQs are empty. */
223 bool lqEmpty() const;
224 /** Returns if all of the SQs are empty. */
225 bool sqEmpty() const;
226
227 /** Returns if any of the LQs are full. */
228 bool lqFull();
229 /** Returns if the LQ of a given thread is full. */
230 bool lqFull(ThreadID tid);
231
232 /** Returns if any of the SQs are full. */
233 bool sqFull();
234 /** Returns if the SQ of a given thread is full. */
235 bool sqFull(ThreadID tid);
236
237 /**
238 * Returns if the LSQ is stalled due to a memory operation that must be
239 * replayed.
240 */
241 bool isStalled();
242 /**
243 * Returns if the LSQ of a specific thread is stalled due to a memory
244 * operation that must be replayed.
245 */
246 bool isStalled(ThreadID tid);
247
248 /** Returns whether or not there are any stores to write back to memory. */
249 bool hasStoresToWB();
250
251 /** Returns whether or not a specific thread has any stores to write back
252 * to memory.
253 */
254 bool hasStoresToWB(ThreadID tid)
255 { return thread[tid].hasStoresToWB(); }
256
257 /** Returns the number of stores a specific thread has to write back. */
258 int numStoresToWB(ThreadID tid)
259 { return thread[tid].numStoresToWB(); }
260
261 /** Returns if the LSQ will write back to memory this cycle. */
262 bool willWB();
263 /** Returns if the LSQ of a specific thread will write back to memory this
264 * cycle.
265 */
266 bool willWB(ThreadID tid)
267 { return thread[tid].willWB(); }
268
269 /** Returns if the cache is currently blocked. */
270 bool cacheBlocked() const
271 { return retryTid != InvalidThreadID; }
272
273 /** Sets the retry thread id, indicating that one of the LSQUnits
274 * tried to access the cache but the cache was blocked. */
275 void setRetryTid(ThreadID tid)
276 { retryTid = tid; }
277
278 /** Debugging function to print out all instructions. */
279 void dumpInsts() const;
280 /** Debugging function to print out instructions from a specific thread. */
281 void dumpInsts(ThreadID tid) const
282 { thread[tid].dumpInsts(); }
283
284 /** Executes a read operation, using the load specified at the load
285 * index.
286 */
287 Fault read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
288 uint8_t *data, int load_idx);
289
290 /** Executes a store operation, using the store specified at the store
291 * index.
292 */
293 Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
294 uint8_t *data, int store_idx);
295
296 /**
297 * Retry the previous send that failed.
298 */
299 void recvRetry();
300
301 /**
302 * Handles writing back and completing the load or store that has
303 * returned from memory.
304 *
305 * @param pkt Response packet from the memory sub-system
306 */
307 bool recvTimingResp(PacketPtr pkt);
308
309 void recvTimingSnoopReq(PacketPtr pkt);
310
311 /** The CPU pointer. */
312 O3CPU *cpu;
313
314 /** The IEW stage pointer. */
315 IEW *iewStage;
316
317 protected:
318 /** The LSQ policy for SMT mode. */
319 LSQPolicy lsqPolicy;
320
321 /** The LSQ units for individual threads. */
322 LSQUnit *thread;
323
324 /** List of Active Threads in System. */
325 std::list<ThreadID> *activeThreads;
326
327 /** Total Size of LQ Entries. */
328 unsigned LQEntries;
329 /** Total Size of SQ Entries. */
330 unsigned SQEntries;
331
332 /** Max LQ Size - Used to Enforce Sharing Policies. */
333 unsigned maxLQEntries;
334
335 /** Max SQ Size - Used to Enforce Sharing Policies. */
336 unsigned maxSQEntries;
337
338 /** Number of Threads. */
339 ThreadID numThreads;
340
341 /** The thread id of the LSQ Unit that is currently waiting for a
342 * retry. */
343 ThreadID retryTid;
344};
345
346template <class Impl>
347Fault
348LSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
349 uint8_t *data, int load_idx)
350{
351 ThreadID tid = req->threadId();
352
353 return thread[tid].read(req, sreqLow, sreqHigh, data, load_idx);
354}
355
356template <class Impl>
357Fault
358LSQ<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
359 uint8_t *data, int store_idx)
360{
361 ThreadID tid = req->threadId();
362
363 return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx);
364}
365
366#endif // __CPU_O3_LSQ_HH__
| 223 /** Returns if the LSQ is full (either LQ or SQ is full). */
224 bool isFull();
225 /**
226 * Returns if the LSQ is full for a specific thread (either LQ or SQ is
227 * full).
228 */
229 bool isFull(ThreadID tid);
230
231 /** Returns if the LSQ is empty (both LQ and SQ are empty). */
232 bool isEmpty() const;
233 /** Returns if all of the LQs are empty. */
234 bool lqEmpty() const;
235 /** Returns if all of the SQs are empty. */
236 bool sqEmpty() const;
237
238 /** Returns if any of the LQs are full. */
239 bool lqFull();
240 /** Returns if the LQ of a given thread is full. */
241 bool lqFull(ThreadID tid);
242
243 /** Returns if any of the SQs are full. */
244 bool sqFull();
245 /** Returns if the SQ of a given thread is full. */
246 bool sqFull(ThreadID tid);
247
248 /**
249 * Returns if the LSQ is stalled due to a memory operation that must be
250 * replayed.
251 */
252 bool isStalled();
253 /**
254 * Returns if the LSQ of a specific thread is stalled due to a memory
255 * operation that must be replayed.
256 */
257 bool isStalled(ThreadID tid);
258
259 /** Returns whether or not there are any stores to write back to memory. */
260 bool hasStoresToWB();
261
262 /** Returns whether or not a specific thread has any stores to write back
263 * to memory.
264 */
265 bool hasStoresToWB(ThreadID tid)
266 { return thread[tid].hasStoresToWB(); }
267
268 /** Returns the number of stores a specific thread has to write back. */
269 int numStoresToWB(ThreadID tid)
270 { return thread[tid].numStoresToWB(); }
271
272 /** Returns if the LSQ will write back to memory this cycle. */
273 bool willWB();
274 /** Returns if the LSQ of a specific thread will write back to memory this
275 * cycle.
276 */
277 bool willWB(ThreadID tid)
278 { return thread[tid].willWB(); }
279
280 /** Returns if the cache is currently blocked. */
281 bool cacheBlocked() const
282 { return retryTid != InvalidThreadID; }
283
284 /** Sets the retry thread id, indicating that one of the LSQUnits
285 * tried to access the cache but the cache was blocked. */
286 void setRetryTid(ThreadID tid)
287 { retryTid = tid; }
288
289 /** Debugging function to print out all instructions. */
290 void dumpInsts() const;
291 /** Debugging function to print out instructions from a specific thread. */
292 void dumpInsts(ThreadID tid) const
293 { thread[tid].dumpInsts(); }
294
295 /** Executes a read operation, using the load specified at the load
296 * index.
297 */
298 Fault read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
299 uint8_t *data, int load_idx);
300
301 /** Executes a store operation, using the store specified at the store
302 * index.
303 */
304 Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
305 uint8_t *data, int store_idx);
306
307 /**
308 * Retry the previous send that failed.
309 */
310 void recvRetry();
311
312 /**
313 * Handles writing back and completing the load or store that has
314 * returned from memory.
315 *
316 * @param pkt Response packet from the memory sub-system
317 */
318 bool recvTimingResp(PacketPtr pkt);
319
320 void recvTimingSnoopReq(PacketPtr pkt);
321
322 /** The CPU pointer. */
323 O3CPU *cpu;
324
325 /** The IEW stage pointer. */
326 IEW *iewStage;
327
328 protected:
329 /** The LSQ policy for SMT mode. */
330 LSQPolicy lsqPolicy;
331
332 /** The LSQ units for individual threads. */
333 LSQUnit *thread;
334
335 /** List of Active Threads in System. */
336 std::list<ThreadID> *activeThreads;
337
338 /** Total Size of LQ Entries. */
339 unsigned LQEntries;
340 /** Total Size of SQ Entries. */
341 unsigned SQEntries;
342
343 /** Max LQ Size - Used to Enforce Sharing Policies. */
344 unsigned maxLQEntries;
345
346 /** Max SQ Size - Used to Enforce Sharing Policies. */
347 unsigned maxSQEntries;
348
349 /** Number of Threads. */
350 ThreadID numThreads;
351
352 /** The thread id of the LSQ Unit that is currently waiting for a
353 * retry. */
354 ThreadID retryTid;
355};
356
357template <class Impl>
358Fault
359LSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
360 uint8_t *data, int load_idx)
361{
362 ThreadID tid = req->threadId();
363
364 return thread[tid].read(req, sreqLow, sreqHigh, data, load_idx);
365}
366
367template <class Impl>
368Fault
369LSQ<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
370 uint8_t *data, int store_idx)
371{
372 ThreadID tid = req->threadId();
373
374 return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx);
375}
376
377#endif // __CPU_O3_LSQ_HH__
|