1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Korey Sewell
29 */
30
31#ifndef __CPU_O3_LSQ_HH__
32#define __CPU_O3_LSQ_HH__
33
34#include <map>
35#include <queue>
36
37#include "config/full_system.hh"
38#include "cpu/inst_seq.hh"
39#include "cpu/o3/lsq_unit.hh"
40#include "mem/port.hh"
41#include "sim/sim_object.hh"
42
43class DerivO3CPUParams;
44
45template <class Impl>
46class LSQ {
47 public:
48 typedef typename Impl::O3CPU O3CPU;
49 typedef typename Impl::DynInstPtr DynInstPtr;
50 typedef typename Impl::CPUPol::IEW IEW;
51 typedef typename Impl::CPUPol::LSQUnit LSQUnit;
52
53 /** SMT policy. */
54 enum LSQPolicy {
55 Dynamic,
56 Partitioned,
57 Threshold
58 };
59
60 /** Constructs an LSQ with the given parameters. */
61 LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params);
62
63 /** Returns the name of the LSQ. */
64 std::string name() const;
65
66 /** Registers statistics of each LSQ unit. */
67 void regStats();
68
69 /** Returns dcache port.
70 * @todo: Dcache port needs to be moved up to this level for SMT
71 * to work. For now it just returns the port from one of the
72 * threads.
73 */
74 Port *getDcachePort() { return &dcachePort; }
75
76 /** Sets the pointer to the list of active threads. */
77 void setActiveThreads(std::list<unsigned> *at_ptr);
78 /** Switches out the LSQ. */
79 void switchOut();
80 /** Takes over execution from another CPU's thread. */
81 void takeOverFrom();
82
83 /** Number of entries needed for the given amount of threads.*/
84 int entryAmount(int num_threads);
85 void removeEntries(unsigned tid);
86 /** Reset the max entries for each thread. */
87 void resetEntries();
88 /** Resize the max entries for a thread. */
89 void resizeEntries(unsigned size, unsigned tid);
90
91 /** Ticks the LSQ. */
92 void tick();
93 /** Ticks a specific LSQ Unit. */
94 void tick(unsigned tid)
95 { thread[tid].tick(); }
96
97 /** Inserts a load into the LSQ. */
98 void insertLoad(DynInstPtr &load_inst);
99 /** Inserts a store into the LSQ. */
100 void insertStore(DynInstPtr &store_inst);
101
102 /** Executes a load. */
103 Fault executeLoad(DynInstPtr &inst);
104
105 /** Executes a store. */
106 Fault executeStore(DynInstPtr &inst);
107
108 /**
109 * Commits loads up until the given sequence number for a specific thread.
110 */
111 void commitLoads(InstSeqNum &youngest_inst, unsigned tid)
112 { thread[tid].commitLoads(youngest_inst); }
113
114 /**
115 * Commits stores up until the given sequence number for a specific thread.
116 */
117 void commitStores(InstSeqNum &youngest_inst, unsigned tid)
118 { thread[tid].commitStores(youngest_inst); }
119
120 /**
121 * Attempts to write back stores until all cache ports are used or the
122 * interface becomes blocked.
123 */
124 void writebackStores();
125 /** Same as above, but only for one thread. */
126 void writebackStores(unsigned tid);
127
128 /**
129 * Squash instructions from a thread until the specified sequence number.
130 */
131 void squash(const InstSeqNum &squashed_num, unsigned tid)
132 { thread[tid].squash(squashed_num); }
133
134 /** Returns whether or not there was a memory ordering violation. */
135 bool violation();
136 /**
137 * Returns whether or not there was a memory ordering violation for a
138 * specific thread.
139 */
140 bool violation(unsigned tid)
141 { return thread[tid].violation(); }
142
143 /** Returns if a load is blocked due to the memory system for a specific
144 * thread.
145 */
146 bool loadBlocked(unsigned tid)
147 { return thread[tid].loadBlocked(); }
148
149 bool isLoadBlockedHandled(unsigned tid)
150 { return thread[tid].isLoadBlockedHandled(); }
151
152 void setLoadBlockedHandled(unsigned tid)
153 { thread[tid].setLoadBlockedHandled(); }
154
155 /** Gets the instruction that caused the memory ordering violation. */
156 DynInstPtr getMemDepViolator(unsigned tid)
157 { return thread[tid].getMemDepViolator(); }
158
159 /** Returns the head index of the load queue for a specific thread. */
160 int getLoadHead(unsigned tid)
161 { return thread[tid].getLoadHead(); }
162
163 /** Returns the sequence number of the head of the load queue. */
164 InstSeqNum getLoadHeadSeqNum(unsigned tid)
165 {
166 return thread[tid].getLoadHeadSeqNum();
167 }
168
169 /** Returns the head index of the store queue. */
170 int getStoreHead(unsigned tid)
171 { return thread[tid].getStoreHead(); }
172
173 /** Returns the sequence number of the head of the store queue. */
174 InstSeqNum getStoreHeadSeqNum(unsigned tid)
175 {
176 return thread[tid].getStoreHeadSeqNum();
177 }
178
179 /** Returns the number of instructions in all of the queues. */
180 int getCount();
181 /** Returns the number of instructions in the queues of one thread. */
182 int getCount(unsigned tid)
183 { return thread[tid].getCount(); }
184
185 /** Returns the total number of loads in the load queue. */
186 int numLoads();
187 /** Returns the total number of loads for a single thread. */
188 int numLoads(unsigned tid)
189 { return thread[tid].numLoads(); }
190
191 /** Returns the total number of stores in the store queue. */
192 int numStores();
193 /** Returns the total number of stores for a single thread. */
194 int numStores(unsigned tid)
195 { return thread[tid].numStores(); }
196
197 /** Returns the total number of loads that are ready. */
198 int numLoadsReady();
199 /** Returns the number of loads that are ready for a single thread. */
200 int numLoadsReady(unsigned tid)
201 { return thread[tid].numLoadsReady(); }
202
203 /** Returns the number of free entries. */
204 unsigned numFreeEntries();
205 /** Returns the number of free entries for a specific thread. */
206 unsigned numFreeEntries(unsigned tid);
207
208 /** Returns if the LSQ is full (either LQ or SQ is full). */
209 bool isFull();
210 /**
211 * Returns if the LSQ is full for a specific thread (either LQ or SQ is
212 * full).
213 */
214 bool isFull(unsigned tid);
215
216 /** Returns if any of the LQs are full. */
217 bool lqFull();
218 /** Returns if the LQ of a given thread is full. */
219 bool lqFull(unsigned tid);
220
221 /** Returns if any of the SQs are full. */
222 bool sqFull();
223 /** Returns if the SQ of a given thread is full. */
224 bool sqFull(unsigned tid);
225
226 /**
227 * Returns if the LSQ is stalled due to a memory operation that must be
228 * replayed.
229 */
230 bool isStalled();
231 /**
232 * Returns if the LSQ of a specific thread is stalled due to a memory
233 * operation that must be replayed.
234 */
235 bool isStalled(unsigned tid);
236
237 /** Returns whether or not there are any stores to write back to memory. */
238 bool hasStoresToWB();
239
240 /** Returns whether or not a specific thread has any stores to write back
241 * to memory.
242 */
243 bool hasStoresToWB(unsigned tid)
244 { return thread[tid].hasStoresToWB(); }
245
246 /** Returns the number of stores a specific thread has to write back. */
247 int numStoresToWB(unsigned tid)
248 { return thread[tid].numStoresToWB(); }
249
250 /** Returns if the LSQ will write back to memory this cycle. */
251 bool willWB();
252 /** Returns if the LSQ of a specific thread will write back to memory this
253 * cycle.
254 */
255 bool willWB(unsigned tid)
256 { return thread[tid].willWB(); }
257
258 /** Returns if the cache is currently blocked. */
259 bool cacheBlocked()
260 { return retryTid != -1; }
261
262 /** Sets the retry thread id, indicating that one of the LSQUnits
263 * tried to access the cache but the cache was blocked. */
264 void setRetryTid(int tid)
265 { retryTid = tid; }
266
267 /** Debugging function to print out all instructions. */
268 void dumpInsts();
269 /** Debugging function to print out instructions from a specific thread. */
270 void dumpInsts(unsigned tid)
271 { thread[tid].dumpInsts(); }
272
273 /** Executes a read operation, using the load specified at the load index. */
274 template <class T>
275 Fault read(RequestPtr req, T &data, int load_idx);
276
277 /** Executes a store operation, using the store specified at the store
278 * index.
279 */
280 template <class T>
281 Fault write(RequestPtr req, T &data, int store_idx);
282
283 /** The CPU pointer. */
284 O3CPU *cpu;
285
286 /** The IEW stage pointer. */
287 IEW *iewStage;
288
289 /** DcachePort class for this LSQ. Handles doing the
290 * communication with the cache/memory.
291 */
292 class DcachePort : public Port
293 {
294 protected:
295 /** Pointer to LSQ. */
296 LSQ *lsq;
297
298 public:
299 /** Default constructor. */
300 DcachePort(LSQ *_lsq)
301 : Port(_lsq->name() + "-dport", _lsq->cpu), lsq(_lsq)
302 { }
303
304 bool snoopRangeSent;
305
306 virtual void setPeer(Port *port);
307
308 protected:
309 /** Atomic version of receive. Panics. */
310 virtual Tick recvAtomic(PacketPtr pkt);
311
312 /** Functional version of receive. Panics. */
313 virtual void recvFunctional(PacketPtr pkt);
314
315 /** Receives status change. Other than range changing, panics. */
316 virtual void recvStatusChange(Status status);
317
318 /** Returns the address ranges of this device. */
319 virtual void getDeviceAddressRanges(AddrRangeList &resp,
320 bool &snoop)
321 { resp.clear(); snoop = true; }
322
323 /** Timing version of receive. Handles writing back and
324 * completing the load or store that has returned from
325 * memory. */
326 virtual bool recvTiming(PacketPtr pkt);
327
328 /** Handles doing a retry of the previous send. */
329 virtual void recvRetry();
330 };
331
332 /** D-cache port. */
333 DcachePort dcachePort;
334
335#if FULL_SYSTEM
336 /** Tell the CPU to update the Phys and Virt ports. */
337 void updateMemPorts() { cpu->updateMemPorts(); }
338#endif
339
340 protected:
341 /** The LSQ policy for SMT mode. */
342 LSQPolicy lsqPolicy;
343
344 /** The LSQ units for individual threads. */
345 LSQUnit thread[Impl::MaxThreads];
346
347 /** List of Active Threads in System. */
348 std::list<unsigned> *activeThreads;
349
350 /** Total Size of LQ Entries. */
351 unsigned LQEntries;
352 /** Total Size of SQ Entries. */
353 unsigned SQEntries;
354
355 /** Max LQ Size - Used to Enforce Sharing Policies. */
356 unsigned maxLQEntries;
357
358 /** Max SQ Size - Used to Enforce Sharing Policies. */
359 unsigned maxSQEntries;
360
361 /** Number of Threads. */
362 unsigned numThreads;
363
364 /** The thread id of the LSQ Unit that is currently waiting for a
365 * retry. */
366 int retryTid;
367};
368
369template <class Impl>
370template <class T>
371Fault
372LSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
373{
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Korey Sewell
29 */
30
31#ifndef __CPU_O3_LSQ_HH__
32#define __CPU_O3_LSQ_HH__
33
34#include <map>
35#include <queue>
36
37#include "config/full_system.hh"
38#include "cpu/inst_seq.hh"
39#include "cpu/o3/lsq_unit.hh"
40#include "mem/port.hh"
41#include "sim/sim_object.hh"
42
43class DerivO3CPUParams;
44
45template <class Impl>
46class LSQ {
47 public:
48 typedef typename Impl::O3CPU O3CPU;
49 typedef typename Impl::DynInstPtr DynInstPtr;
50 typedef typename Impl::CPUPol::IEW IEW;
51 typedef typename Impl::CPUPol::LSQUnit LSQUnit;
52
53 /** SMT policy. */
54 enum LSQPolicy {
55 Dynamic,
56 Partitioned,
57 Threshold
58 };
59
60 /** Constructs an LSQ with the given parameters. */
61 LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params);
62
63 /** Returns the name of the LSQ. */
64 std::string name() const;
65
66 /** Registers statistics of each LSQ unit. */
67 void regStats();
68
69 /** Returns dcache port.
70 * @todo: Dcache port needs to be moved up to this level for SMT
71 * to work. For now it just returns the port from one of the
72 * threads.
73 */
74 Port *getDcachePort() { return &dcachePort; }
75
76 /** Sets the pointer to the list of active threads. */
77 void setActiveThreads(std::list<unsigned> *at_ptr);
78 /** Switches out the LSQ. */
79 void switchOut();
80 /** Takes over execution from another CPU's thread. */
81 void takeOverFrom();
82
83 /** Number of entries needed for the given amount of threads.*/
84 int entryAmount(int num_threads);
85 void removeEntries(unsigned tid);
86 /** Reset the max entries for each thread. */
87 void resetEntries();
88 /** Resize the max entries for a thread. */
89 void resizeEntries(unsigned size, unsigned tid);
90
91 /** Ticks the LSQ. */
92 void tick();
93 /** Ticks a specific LSQ Unit. */
94 void tick(unsigned tid)
95 { thread[tid].tick(); }
96
97 /** Inserts a load into the LSQ. */
98 void insertLoad(DynInstPtr &load_inst);
99 /** Inserts a store into the LSQ. */
100 void insertStore(DynInstPtr &store_inst);
101
102 /** Executes a load. */
103 Fault executeLoad(DynInstPtr &inst);
104
105 /** Executes a store. */
106 Fault executeStore(DynInstPtr &inst);
107
108 /**
109 * Commits loads up until the given sequence number for a specific thread.
110 */
111 void commitLoads(InstSeqNum &youngest_inst, unsigned tid)
112 { thread[tid].commitLoads(youngest_inst); }
113
114 /**
115 * Commits stores up until the given sequence number for a specific thread.
116 */
117 void commitStores(InstSeqNum &youngest_inst, unsigned tid)
118 { thread[tid].commitStores(youngest_inst); }
119
120 /**
121 * Attempts to write back stores until all cache ports are used or the
122 * interface becomes blocked.
123 */
124 void writebackStores();
125 /** Same as above, but only for one thread. */
126 void writebackStores(unsigned tid);
127
128 /**
129 * Squash instructions from a thread until the specified sequence number.
130 */
131 void squash(const InstSeqNum &squashed_num, unsigned tid)
132 { thread[tid].squash(squashed_num); }
133
134 /** Returns whether or not there was a memory ordering violation. */
135 bool violation();
136 /**
137 * Returns whether or not there was a memory ordering violation for a
138 * specific thread.
139 */
140 bool violation(unsigned tid)
141 { return thread[tid].violation(); }
142
143 /** Returns if a load is blocked due to the memory system for a specific
144 * thread.
145 */
146 bool loadBlocked(unsigned tid)
147 { return thread[tid].loadBlocked(); }
148
149 bool isLoadBlockedHandled(unsigned tid)
150 { return thread[tid].isLoadBlockedHandled(); }
151
152 void setLoadBlockedHandled(unsigned tid)
153 { thread[tid].setLoadBlockedHandled(); }
154
155 /** Gets the instruction that caused the memory ordering violation. */
156 DynInstPtr getMemDepViolator(unsigned tid)
157 { return thread[tid].getMemDepViolator(); }
158
159 /** Returns the head index of the load queue for a specific thread. */
160 int getLoadHead(unsigned tid)
161 { return thread[tid].getLoadHead(); }
162
163 /** Returns the sequence number of the head of the load queue. */
164 InstSeqNum getLoadHeadSeqNum(unsigned tid)
165 {
166 return thread[tid].getLoadHeadSeqNum();
167 }
168
169 /** Returns the head index of the store queue. */
170 int getStoreHead(unsigned tid)
171 { return thread[tid].getStoreHead(); }
172
173 /** Returns the sequence number of the head of the store queue. */
174 InstSeqNum getStoreHeadSeqNum(unsigned tid)
175 {
176 return thread[tid].getStoreHeadSeqNum();
177 }
178
179 /** Returns the number of instructions in all of the queues. */
180 int getCount();
181 /** Returns the number of instructions in the queues of one thread. */
182 int getCount(unsigned tid)
183 { return thread[tid].getCount(); }
184
185 /** Returns the total number of loads in the load queue. */
186 int numLoads();
187 /** Returns the total number of loads for a single thread. */
188 int numLoads(unsigned tid)
189 { return thread[tid].numLoads(); }
190
191 /** Returns the total number of stores in the store queue. */
192 int numStores();
193 /** Returns the total number of stores for a single thread. */
194 int numStores(unsigned tid)
195 { return thread[tid].numStores(); }
196
197 /** Returns the total number of loads that are ready. */
198 int numLoadsReady();
199 /** Returns the number of loads that are ready for a single thread. */
200 int numLoadsReady(unsigned tid)
201 { return thread[tid].numLoadsReady(); }
202
203 /** Returns the number of free entries. */
204 unsigned numFreeEntries();
205 /** Returns the number of free entries for a specific thread. */
206 unsigned numFreeEntries(unsigned tid);
207
208 /** Returns if the LSQ is full (either LQ or SQ is full). */
209 bool isFull();
210 /**
211 * Returns if the LSQ is full for a specific thread (either LQ or SQ is
212 * full).
213 */
214 bool isFull(unsigned tid);
215
216 /** Returns if any of the LQs are full. */
217 bool lqFull();
218 /** Returns if the LQ of a given thread is full. */
219 bool lqFull(unsigned tid);
220
221 /** Returns if any of the SQs are full. */
222 bool sqFull();
223 /** Returns if the SQ of a given thread is full. */
224 bool sqFull(unsigned tid);
225
226 /**
227 * Returns if the LSQ is stalled due to a memory operation that must be
228 * replayed.
229 */
230 bool isStalled();
231 /**
232 * Returns if the LSQ of a specific thread is stalled due to a memory
233 * operation that must be replayed.
234 */
235 bool isStalled(unsigned tid);
236
237 /** Returns whether or not there are any stores to write back to memory. */
238 bool hasStoresToWB();
239
240 /** Returns whether or not a specific thread has any stores to write back
241 * to memory.
242 */
243 bool hasStoresToWB(unsigned tid)
244 { return thread[tid].hasStoresToWB(); }
245
246 /** Returns the number of stores a specific thread has to write back. */
247 int numStoresToWB(unsigned tid)
248 { return thread[tid].numStoresToWB(); }
249
250 /** Returns if the LSQ will write back to memory this cycle. */
251 bool willWB();
252 /** Returns if the LSQ of a specific thread will write back to memory this
253 * cycle.
254 */
255 bool willWB(unsigned tid)
256 { return thread[tid].willWB(); }
257
258 /** Returns if the cache is currently blocked. */
259 bool cacheBlocked()
260 { return retryTid != -1; }
261
262 /** Sets the retry thread id, indicating that one of the LSQUnits
263 * tried to access the cache but the cache was blocked. */
264 void setRetryTid(int tid)
265 { retryTid = tid; }
266
267 /** Debugging function to print out all instructions. */
268 void dumpInsts();
269 /** Debugging function to print out instructions from a specific thread. */
270 void dumpInsts(unsigned tid)
271 { thread[tid].dumpInsts(); }
272
273 /** Executes a read operation, using the load specified at the load index. */
274 template <class T>
275 Fault read(RequestPtr req, T &data, int load_idx);
276
277 /** Executes a store operation, using the store specified at the store
278 * index.
279 */
280 template <class T>
281 Fault write(RequestPtr req, T &data, int store_idx);
282
283 /** The CPU pointer. */
284 O3CPU *cpu;
285
286 /** The IEW stage pointer. */
287 IEW *iewStage;
288
289 /** DcachePort class for this LSQ. Handles doing the
290 * communication with the cache/memory.
291 */
292 class DcachePort : public Port
293 {
294 protected:
295 /** Pointer to LSQ. */
296 LSQ *lsq;
297
298 public:
299 /** Default constructor. */
300 DcachePort(LSQ *_lsq)
301 : Port(_lsq->name() + "-dport", _lsq->cpu), lsq(_lsq)
302 { }
303
304 bool snoopRangeSent;
305
306 virtual void setPeer(Port *port);
307
308 protected:
309 /** Atomic version of receive. Panics. */
310 virtual Tick recvAtomic(PacketPtr pkt);
311
312 /** Functional version of receive. Panics. */
313 virtual void recvFunctional(PacketPtr pkt);
314
315 /** Receives status change. Other than range changing, panics. */
316 virtual void recvStatusChange(Status status);
317
318 /** Returns the address ranges of this device. */
319 virtual void getDeviceAddressRanges(AddrRangeList &resp,
320 bool &snoop)
321 { resp.clear(); snoop = true; }
322
323 /** Timing version of receive. Handles writing back and
324 * completing the load or store that has returned from
325 * memory. */
326 virtual bool recvTiming(PacketPtr pkt);
327
328 /** Handles doing a retry of the previous send. */
329 virtual void recvRetry();
330 };
331
332 /** D-cache port. */
333 DcachePort dcachePort;
334
335#if FULL_SYSTEM
336 /** Tell the CPU to update the Phys and Virt ports. */
337 void updateMemPorts() { cpu->updateMemPorts(); }
338#endif
339
340 protected:
341 /** The LSQ policy for SMT mode. */
342 LSQPolicy lsqPolicy;
343
344 /** The LSQ units for individual threads. */
345 LSQUnit thread[Impl::MaxThreads];
346
347 /** List of Active Threads in System. */
348 std::list<unsigned> *activeThreads;
349
350 /** Total Size of LQ Entries. */
351 unsigned LQEntries;
352 /** Total Size of SQ Entries. */
353 unsigned SQEntries;
354
355 /** Max LQ Size - Used to Enforce Sharing Policies. */
356 unsigned maxLQEntries;
357
358 /** Max SQ Size - Used to Enforce Sharing Policies. */
359 unsigned maxSQEntries;
360
361 /** Number of Threads. */
362 unsigned numThreads;
363
364 /** The thread id of the LSQ Unit that is currently waiting for a
365 * retry. */
366 int retryTid;
367};
368
369template <class Impl>
370template <class T>
371Fault
372LSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
373{
|