1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Korey Sewell
29 */
30
31#ifndef __CPU_O3_LSQ_HH__
32#define __CPU_O3_LSQ_HH__
33
34#include <map>
35#include <queue>
36
37#include "config/full_system.hh"
38#include "cpu/inst_seq.hh"
39#include "cpu/o3/lsq_unit.hh"
40#include "mem/port.hh"
41#include "sim/sim_object.hh"
42
43template <class Impl>
44class LSQ {
45 public:
46 typedef typename Impl::Params Params;
47 typedef typename Impl::O3CPU O3CPU;
48 typedef typename Impl::DynInstPtr DynInstPtr;
49 typedef typename Impl::CPUPol::IEW IEW;
50 typedef typename Impl::CPUPol::LSQUnit LSQUnit;
51
52 /** SMT policy. */
53 enum LSQPolicy {
54 Dynamic,
55 Partitioned,
56 Threshold
57 };
58
59 /** Constructs an LSQ with the given parameters. */
60 LSQ(Params *params);
61
62 /** Returns the name of the LSQ. */
63 std::string name() const;
64
65 /** Registers statistics of each LSQ unit. */
66 void regStats();
67
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Korey Sewell
29 */
30
31#ifndef __CPU_O3_LSQ_HH__
32#define __CPU_O3_LSQ_HH__
33
34#include <map>
35#include <queue>
36
37#include "config/full_system.hh"
38#include "cpu/inst_seq.hh"
39#include "cpu/o3/lsq_unit.hh"
40#include "mem/port.hh"
41#include "sim/sim_object.hh"
42
43template <class Impl>
44class LSQ {
45 public:
46 typedef typename Impl::Params Params;
47 typedef typename Impl::O3CPU O3CPU;
48 typedef typename Impl::DynInstPtr DynInstPtr;
49 typedef typename Impl::CPUPol::IEW IEW;
50 typedef typename Impl::CPUPol::LSQUnit LSQUnit;
51
52 /** SMT policy. */
53 enum LSQPolicy {
54 Dynamic,
55 Partitioned,
56 Threshold
57 };
58
59 /** Constructs an LSQ with the given parameters. */
60 LSQ(Params *params);
61
62 /** Returns the name of the LSQ. */
63 std::string name() const;
64
65 /** Registers statistics of each LSQ unit. */
66 void regStats();
67
|
68 /** Sets the pointer to the list of active threads. */
69 void setActiveThreads(std::list<unsigned> *at_ptr);
70 /** Sets the CPU pointer. */
71 void setCPU(O3CPU *cpu_ptr);
72 /** Sets the IEW stage pointer. */
73 void setIEW(IEW *iew_ptr);
74 /** Switches out the LSQ. */
75 void switchOut();
76 /** Takes over execution from another CPU's thread. */
77 void takeOverFrom();
78
79 /** Number of entries needed for the given amount of threads.*/
80 int entryAmount(int num_threads);
81 void removeEntries(unsigned tid);
82 /** Reset the max entries for each thread. */
83 void resetEntries();
84 /** Resize the max entries for a thread. */
85 void resizeEntries(unsigned size, unsigned tid);
86
87 /** Ticks the LSQ. */
88 void tick();
89 /** Ticks a specific LSQ Unit. */
90 void tick(unsigned tid)
91 { thread[tid].tick(); }
92
93 /** Inserts a load into the LSQ. */
94 void insertLoad(DynInstPtr &load_inst);
95 /** Inserts a store into the LSQ. */
96 void insertStore(DynInstPtr &store_inst);
97
98 /** Executes a load. */
99 Fault executeLoad(DynInstPtr &inst);
100
101 /** Executes a store. */
102 Fault executeStore(DynInstPtr &inst);
103
104 /**
105 * Commits loads up until the given sequence number for a specific thread.
106 */
107 void commitLoads(InstSeqNum &youngest_inst, unsigned tid)
108 { thread[tid].commitLoads(youngest_inst); }
109
110 /**
111 * Commits stores up until the given sequence number for a specific thread.
112 */
113 void commitStores(InstSeqNum &youngest_inst, unsigned tid)
114 { thread[tid].commitStores(youngest_inst); }
115
116 /**
117 * Attempts to write back stores until all cache ports are used or the
118 * interface becomes blocked.
119 */
120 void writebackStores();
121 /** Same as above, but only for one thread. */
122 void writebackStores(unsigned tid);
123
124 /**
125 * Squash instructions from a thread until the specified sequence number.
126 */
127 void squash(const InstSeqNum &squashed_num, unsigned tid)
128 { thread[tid].squash(squashed_num); }
129
130 /** Returns whether or not there was a memory ordering violation. */
131 bool violation();
132 /**
133 * Returns whether or not there was a memory ordering violation for a
134 * specific thread.
135 */
136 bool violation(unsigned tid)
137 { return thread[tid].violation(); }
138
139 /** Returns if a load is blocked due to the memory system for a specific
140 * thread.
141 */
142 bool loadBlocked(unsigned tid)
143 { return thread[tid].loadBlocked(); }
144
145 bool isLoadBlockedHandled(unsigned tid)
146 { return thread[tid].isLoadBlockedHandled(); }
147
148 void setLoadBlockedHandled(unsigned tid)
149 { thread[tid].setLoadBlockedHandled(); }
150
151 /** Gets the instruction that caused the memory ordering violation. */
152 DynInstPtr getMemDepViolator(unsigned tid)
153 { return thread[tid].getMemDepViolator(); }
154
155 /** Returns the head index of the load queue for a specific thread. */
156 int getLoadHead(unsigned tid)
157 { return thread[tid].getLoadHead(); }
158
159 /** Returns the sequence number of the head of the load queue. */
160 InstSeqNum getLoadHeadSeqNum(unsigned tid)
161 {
162 return thread[tid].getLoadHeadSeqNum();
163 }
164
165 /** Returns the head index of the store queue. */
166 int getStoreHead(unsigned tid)
167 { return thread[tid].getStoreHead(); }
168
169 /** Returns the sequence number of the head of the store queue. */
170 InstSeqNum getStoreHeadSeqNum(unsigned tid)
171 {
172 return thread[tid].getStoreHeadSeqNum();
173 }
174
175 /** Returns the number of instructions in all of the queues. */
176 int getCount();
177 /** Returns the number of instructions in the queues of one thread. */
178 int getCount(unsigned tid)
179 { return thread[tid].getCount(); }
180
181 /** Returns the total number of loads in the load queue. */
182 int numLoads();
183 /** Returns the total number of loads for a single thread. */
184 int numLoads(unsigned tid)
185 { return thread[tid].numLoads(); }
186
187 /** Returns the total number of stores in the store queue. */
188 int numStores();
189 /** Returns the total number of stores for a single thread. */
190 int numStores(unsigned tid)
191 { return thread[tid].numStores(); }
192
193 /** Returns the total number of loads that are ready. */
194 int numLoadsReady();
195 /** Returns the number of loads that are ready for a single thread. */
196 int numLoadsReady(unsigned tid)
197 { return thread[tid].numLoadsReady(); }
198
199 /** Returns the number of free entries. */
200 unsigned numFreeEntries();
201 /** Returns the number of free entries for a specific thread. */
202 unsigned numFreeEntries(unsigned tid);
203
204 /** Returns if the LSQ is full (either LQ or SQ is full). */
205 bool isFull();
206 /**
207 * Returns if the LSQ is full for a specific thread (either LQ or SQ is
208 * full).
209 */
210 bool isFull(unsigned tid);
211
212 /** Returns if any of the LQs are full. */
213 bool lqFull();
214 /** Returns if the LQ of a given thread is full. */
215 bool lqFull(unsigned tid);
216
217 /** Returns if any of the SQs are full. */
218 bool sqFull();
219 /** Returns if the SQ of a given thread is full. */
220 bool sqFull(unsigned tid);
221
222 /**
223 * Returns if the LSQ is stalled due to a memory operation that must be
224 * replayed.
225 */
226 bool isStalled();
227 /**
228 * Returns if the LSQ of a specific thread is stalled due to a memory
229 * operation that must be replayed.
230 */
231 bool isStalled(unsigned tid);
232
233 /** Returns whether or not there are any stores to write back to memory. */
234 bool hasStoresToWB();
235
236 /** Returns whether or not a specific thread has any stores to write back
237 * to memory.
238 */
239 bool hasStoresToWB(unsigned tid)
240 { return thread[tid].hasStoresToWB(); }
241
242 /** Returns the number of stores a specific thread has to write back. */
243 int numStoresToWB(unsigned tid)
244 { return thread[tid].numStoresToWB(); }
245
246 /** Returns if the LSQ will write back to memory this cycle. */
247 bool willWB();
248 /** Returns if the LSQ of a specific thread will write back to memory this
249 * cycle.
250 */
251 bool willWB(unsigned tid)
252 { return thread[tid].willWB(); }
253
254 /** Debugging function to print out all instructions. */
255 void dumpInsts();
256 /** Debugging function to print out instructions from a specific thread. */
257 void dumpInsts(unsigned tid)
258 { thread[tid].dumpInsts(); }
259
260 /** Executes a read operation, using the load specified at the load index. */
261 template <class T>
262 Fault read(RequestPtr req, T &data, int load_idx);
263
264 /** Executes a store operation, using the store specified at the store
265 * index.
266 */
267 template <class T>
268 Fault write(RequestPtr req, T &data, int store_idx);
269
270 private:
271 /** The LSQ policy for SMT mode. */
272 LSQPolicy lsqPolicy;
273
274 /** The LSQ units for individual threads. */
275 LSQUnit thread[Impl::MaxThreads];
276
277 /** The CPU pointer. */
278 O3CPU *cpu;
279
280 /** The IEW stage pointer. */
281 IEW *iewStage;
282
283 /** List of Active Threads in System. */
284 std::list<unsigned> *activeThreads;
285
286 /** Total Size of LQ Entries. */
287 unsigned LQEntries;
288 /** Total Size of SQ Entries. */
289 unsigned SQEntries;
290
291 /** Max LQ Size - Used to Enforce Sharing Policies. */
292 unsigned maxLQEntries;
293
294 /** Max SQ Size - Used to Enforce Sharing Policies. */
295 unsigned maxSQEntries;
296
297 /** Number of Threads. */
298 unsigned numThreads;
299};
300
301template <class Impl>
302template <class T>
303Fault
304LSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
305{
306 unsigned tid = req->getThreadNum();
307
308 return thread[tid].read(req, data, load_idx);
309}
310
311template <class Impl>
312template <class T>
313Fault
314LSQ<Impl>::write(RequestPtr req, T &data, int store_idx)
315{
316 unsigned tid = req->getThreadNum();
317
318 return thread[tid].write(req, data, store_idx);
319}
320
321#endif // __CPU_O3_LSQ_HH__
| 75 /** Sets the pointer to the list of active threads. */
76 void setActiveThreads(std::list<unsigned> *at_ptr);
77 /** Sets the CPU pointer. */
78 void setCPU(O3CPU *cpu_ptr);
79 /** Sets the IEW stage pointer. */
80 void setIEW(IEW *iew_ptr);
81 /** Switches out the LSQ. */
82 void switchOut();
83 /** Takes over execution from another CPU's thread. */
84 void takeOverFrom();
85
86 /** Number of entries needed for the given amount of threads.*/
87 int entryAmount(int num_threads);
88 void removeEntries(unsigned tid);
89 /** Reset the max entries for each thread. */
90 void resetEntries();
91 /** Resize the max entries for a thread. */
92 void resizeEntries(unsigned size, unsigned tid);
93
94 /** Ticks the LSQ. */
95 void tick();
96 /** Ticks a specific LSQ Unit. */
97 void tick(unsigned tid)
98 { thread[tid].tick(); }
99
100 /** Inserts a load into the LSQ. */
101 void insertLoad(DynInstPtr &load_inst);
102 /** Inserts a store into the LSQ. */
103 void insertStore(DynInstPtr &store_inst);
104
105 /** Executes a load. */
106 Fault executeLoad(DynInstPtr &inst);
107
108 /** Executes a store. */
109 Fault executeStore(DynInstPtr &inst);
110
111 /**
112 * Commits loads up until the given sequence number for a specific thread.
113 */
114 void commitLoads(InstSeqNum &youngest_inst, unsigned tid)
115 { thread[tid].commitLoads(youngest_inst); }
116
117 /**
118 * Commits stores up until the given sequence number for a specific thread.
119 */
120 void commitStores(InstSeqNum &youngest_inst, unsigned tid)
121 { thread[tid].commitStores(youngest_inst); }
122
123 /**
124 * Attempts to write back stores until all cache ports are used or the
125 * interface becomes blocked.
126 */
127 void writebackStores();
128 /** Same as above, but only for one thread. */
129 void writebackStores(unsigned tid);
130
131 /**
132 * Squash instructions from a thread until the specified sequence number.
133 */
134 void squash(const InstSeqNum &squashed_num, unsigned tid)
135 { thread[tid].squash(squashed_num); }
136
137 /** Returns whether or not there was a memory ordering violation. */
138 bool violation();
139 /**
140 * Returns whether or not there was a memory ordering violation for a
141 * specific thread.
142 */
143 bool violation(unsigned tid)
144 { return thread[tid].violation(); }
145
146 /** Returns if a load is blocked due to the memory system for a specific
147 * thread.
148 */
149 bool loadBlocked(unsigned tid)
150 { return thread[tid].loadBlocked(); }
151
152 bool isLoadBlockedHandled(unsigned tid)
153 { return thread[tid].isLoadBlockedHandled(); }
154
155 void setLoadBlockedHandled(unsigned tid)
156 { thread[tid].setLoadBlockedHandled(); }
157
158 /** Gets the instruction that caused the memory ordering violation. */
159 DynInstPtr getMemDepViolator(unsigned tid)
160 { return thread[tid].getMemDepViolator(); }
161
162 /** Returns the head index of the load queue for a specific thread. */
163 int getLoadHead(unsigned tid)
164 { return thread[tid].getLoadHead(); }
165
166 /** Returns the sequence number of the head of the load queue. */
167 InstSeqNum getLoadHeadSeqNum(unsigned tid)
168 {
169 return thread[tid].getLoadHeadSeqNum();
170 }
171
172 /** Returns the head index of the store queue. */
173 int getStoreHead(unsigned tid)
174 { return thread[tid].getStoreHead(); }
175
176 /** Returns the sequence number of the head of the store queue. */
177 InstSeqNum getStoreHeadSeqNum(unsigned tid)
178 {
179 return thread[tid].getStoreHeadSeqNum();
180 }
181
182 /** Returns the number of instructions in all of the queues. */
183 int getCount();
184 /** Returns the number of instructions in the queues of one thread. */
185 int getCount(unsigned tid)
186 { return thread[tid].getCount(); }
187
188 /** Returns the total number of loads in the load queue. */
189 int numLoads();
190 /** Returns the total number of loads for a single thread. */
191 int numLoads(unsigned tid)
192 { return thread[tid].numLoads(); }
193
194 /** Returns the total number of stores in the store queue. */
195 int numStores();
196 /** Returns the total number of stores for a single thread. */
197 int numStores(unsigned tid)
198 { return thread[tid].numStores(); }
199
200 /** Returns the total number of loads that are ready. */
201 int numLoadsReady();
202 /** Returns the number of loads that are ready for a single thread. */
203 int numLoadsReady(unsigned tid)
204 { return thread[tid].numLoadsReady(); }
205
206 /** Returns the number of free entries. */
207 unsigned numFreeEntries();
208 /** Returns the number of free entries for a specific thread. */
209 unsigned numFreeEntries(unsigned tid);
210
211 /** Returns if the LSQ is full (either LQ or SQ is full). */
212 bool isFull();
213 /**
214 * Returns if the LSQ is full for a specific thread (either LQ or SQ is
215 * full).
216 */
217 bool isFull(unsigned tid);
218
219 /** Returns if any of the LQs are full. */
220 bool lqFull();
221 /** Returns if the LQ of a given thread is full. */
222 bool lqFull(unsigned tid);
223
224 /** Returns if any of the SQs are full. */
225 bool sqFull();
226 /** Returns if the SQ of a given thread is full. */
227 bool sqFull(unsigned tid);
228
229 /**
230 * Returns if the LSQ is stalled due to a memory operation that must be
231 * replayed.
232 */
233 bool isStalled();
234 /**
235 * Returns if the LSQ of a specific thread is stalled due to a memory
236 * operation that must be replayed.
237 */
238 bool isStalled(unsigned tid);
239
240 /** Returns whether or not there are any stores to write back to memory. */
241 bool hasStoresToWB();
242
243 /** Returns whether or not a specific thread has any stores to write back
244 * to memory.
245 */
246 bool hasStoresToWB(unsigned tid)
247 { return thread[tid].hasStoresToWB(); }
248
249 /** Returns the number of stores a specific thread has to write back. */
250 int numStoresToWB(unsigned tid)
251 { return thread[tid].numStoresToWB(); }
252
253 /** Returns if the LSQ will write back to memory this cycle. */
254 bool willWB();
255 /** Returns if the LSQ of a specific thread will write back to memory this
256 * cycle.
257 */
258 bool willWB(unsigned tid)
259 { return thread[tid].willWB(); }
260
261 /** Debugging function to print out all instructions. */
262 void dumpInsts();
263 /** Debugging function to print out instructions from a specific thread. */
264 void dumpInsts(unsigned tid)
265 { thread[tid].dumpInsts(); }
266
267 /** Executes a read operation, using the load specified at the load index. */
268 template <class T>
269 Fault read(RequestPtr req, T &data, int load_idx);
270
271 /** Executes a store operation, using the store specified at the store
272 * index.
273 */
274 template <class T>
275 Fault write(RequestPtr req, T &data, int store_idx);
276
277 private:
278 /** The LSQ policy for SMT mode. */
279 LSQPolicy lsqPolicy;
280
281 /** The LSQ units for individual threads. */
282 LSQUnit thread[Impl::MaxThreads];
283
284 /** The CPU pointer. */
285 O3CPU *cpu;
286
287 /** The IEW stage pointer. */
288 IEW *iewStage;
289
290 /** List of Active Threads in System. */
291 std::list<unsigned> *activeThreads;
292
293 /** Total Size of LQ Entries. */
294 unsigned LQEntries;
295 /** Total Size of SQ Entries. */
296 unsigned SQEntries;
297
298 /** Max LQ Size - Used to Enforce Sharing Policies. */
299 unsigned maxLQEntries;
300
301 /** Max SQ Size - Used to Enforce Sharing Policies. */
302 unsigned maxSQEntries;
303
304 /** Number of Threads. */
305 unsigned numThreads;
306};
307
308template <class Impl>
309template <class T>
310Fault
311LSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
312{
313 unsigned tid = req->getThreadNum();
314
315 return thread[tid].read(req, data, load_idx);
316}
317
318template <class Impl>
319template <class T>
320Fault
321LSQ<Impl>::write(RequestPtr req, T &data, int store_idx)
322{
323 unsigned tid = req->getThreadNum();
324
325 return thread[tid].write(req, data, store_idx);
326}
327
328#endif // __CPU_O3_LSQ_HH__
|