1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Korey Sewell
42 */
43
44#ifndef __CPU_O3_LSQ_HH__
45#define __CPU_O3_LSQ_HH__
46
47#include <map>
48#include <queue>
49
50#include "cpu/o3/lsq_unit.hh"
51#include "cpu/inst_seq.hh"
52#include "mem/port.hh"
53#include "sim/sim_object.hh"
54
55struct DerivO3CPUParams;
56
57template <class Impl>
58class LSQ {
59 public:
60 typedef typename Impl::O3CPU O3CPU;
61 typedef typename Impl::DynInstPtr DynInstPtr;
62 typedef typename Impl::CPUPol::IEW IEW;
63 typedef typename Impl::CPUPol::LSQUnit LSQUnit;
64
65 /** SMT policy. */
66 enum LSQPolicy {
67 Dynamic,
68 Partitioned,
69 Threshold
70 };
71
72 /** Constructs an LSQ with the given parameters. */
73 LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params);
| 1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Korey Sewell
42 */
43
44#ifndef __CPU_O3_LSQ_HH__
45#define __CPU_O3_LSQ_HH__
46
47#include <map>
48#include <queue>
49
50#include "cpu/o3/lsq_unit.hh"
51#include "cpu/inst_seq.hh"
52#include "mem/port.hh"
53#include "sim/sim_object.hh"
54
55struct DerivO3CPUParams;
56
57template <class Impl>
58class LSQ {
59 public:
60 typedef typename Impl::O3CPU O3CPU;
61 typedef typename Impl::DynInstPtr DynInstPtr;
62 typedef typename Impl::CPUPol::IEW IEW;
63 typedef typename Impl::CPUPol::LSQUnit LSQUnit;
64
65 /** SMT policy. */
66 enum LSQPolicy {
67 Dynamic,
68 Partitioned,
69 Threshold
70 };
71
72 /** Constructs an LSQ with the given parameters. */
73 LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params);
|
74 ~LSQ() {
75 if (thread) delete [] thread;
76 }
| 74 ~LSQ() { }
|
77
78 /** Returns the name of the LSQ. */
79 std::string name() const;
80
81 /** Registers statistics of each LSQ unit. */
82 void regStats();
83
84 /** Sets the pointer to the list of active threads. */
85 void setActiveThreads(std::list<ThreadID> *at_ptr);
86
87 /** Perform sanity checks after a drain. */
88 void drainSanityCheck() const;
89 /** Has the LSQ drained? */
90 bool isDrained() const;
91 /** Takes over execution from another CPU's thread. */
92 void takeOverFrom();
93
94 /** Number of entries needed for the given amount of threads.*/
95 int entryAmount(ThreadID num_threads);
96 void removeEntries(ThreadID tid);
97 /** Reset the max entries for each thread. */
98 void resetEntries();
99 /** Resize the max entries for a thread. */
100 void resizeEntries(unsigned size, ThreadID tid);
101
102 /** Ticks the LSQ. */
103 void tick();
104 /** Ticks a specific LSQ Unit. */
105 void tick(ThreadID tid)
106 { thread[tid].tick(); }
107
108 /** Inserts a load into the LSQ. */
109 void insertLoad(const DynInstPtr &load_inst);
110 /** Inserts a store into the LSQ. */
111 void insertStore(const DynInstPtr &store_inst);
112
113 /** Executes a load. */
114 Fault executeLoad(const DynInstPtr &inst);
115
116 /** Executes a store. */
117 Fault executeStore(const DynInstPtr &inst);
118
119 /**
120 * Commits loads up until the given sequence number for a specific thread.
121 */
122 void commitLoads(InstSeqNum &youngest_inst, ThreadID tid)
123 { thread[tid].commitLoads(youngest_inst); }
124
125 /**
126 * Commits stores up until the given sequence number for a specific thread.
127 */
128 void commitStores(InstSeqNum &youngest_inst, ThreadID tid)
129 { thread[tid].commitStores(youngest_inst); }
130
131 /**
132 * Attempts to write back stores until all cache ports are used or the
133 * interface becomes blocked.
134 */
135 void writebackStores();
136 /** Same as above, but only for one thread. */
137 void writebackStores(ThreadID tid);
138
139 /**
140 * Squash instructions from a thread until the specified sequence number.
141 */
142 void squash(const InstSeqNum &squashed_num, ThreadID tid)
143 { thread[tid].squash(squashed_num); }
144
145 /** Returns whether or not there was a memory ordering violation. */
146 bool violation();
147 /**
148 * Returns whether or not there was a memory ordering violation for a
149 * specific thread.
150 */
151 bool violation(ThreadID tid)
152 { return thread[tid].violation(); }
153
154 /** Gets the instruction that caused the memory ordering violation. */
155 DynInstPtr getMemDepViolator(ThreadID tid)
156 { return thread[tid].getMemDepViolator(); }
157
158 /** Returns the head index of the load queue for a specific thread. */
159 int getLoadHead(ThreadID tid)
160 { return thread[tid].getLoadHead(); }
161
162 /** Returns the sequence number of the head of the load queue. */
163 InstSeqNum getLoadHeadSeqNum(ThreadID tid)
164 {
165 return thread[tid].getLoadHeadSeqNum();
166 }
167
168 /** Returns the head index of the store queue. */
169 int getStoreHead(ThreadID tid)
170 { return thread[tid].getStoreHead(); }
171
172 /** Returns the sequence number of the head of the store queue. */
173 InstSeqNum getStoreHeadSeqNum(ThreadID tid)
174 {
175 return thread[tid].getStoreHeadSeqNum();
176 }
177
178 /** Returns the number of instructions in all of the queues. */
179 int getCount();
180 /** Returns the number of instructions in the queues of one thread. */
181 int getCount(ThreadID tid)
182 { return thread[tid].getCount(); }
183
184 /** Returns the total number of loads in the load queue. */
185 int numLoads();
186 /** Returns the total number of loads for a single thread. */
187 int numLoads(ThreadID tid)
188 { return thread[tid].numLoads(); }
189
190 /** Returns the total number of stores in the store queue. */
191 int numStores();
192 /** Returns the total number of stores for a single thread. */
193 int numStores(ThreadID tid)
194 { return thread[tid].numStores(); }
195
196 /** Returns the number of free load entries. */
197 unsigned numFreeLoadEntries();
198
199 /** Returns the number of free store entries. */
200 unsigned numFreeStoreEntries();
201
202 /** Returns the number of free entries for a specific thread. */
203 unsigned numFreeEntries(ThreadID tid);
204
205 /** Returns the number of free entries in the LQ for a specific thread. */
206 unsigned numFreeLoadEntries(ThreadID tid);
207
208 /** Returns the number of free entries in the SQ for a specific thread. */
209 unsigned numFreeStoreEntries(ThreadID tid);
210
211 /** Returns if the LSQ is full (either LQ or SQ is full). */
212 bool isFull();
213 /**
214 * Returns if the LSQ is full for a specific thread (either LQ or SQ is
215 * full).
216 */
217 bool isFull(ThreadID tid);
218
219 /** Returns if the LSQ is empty (both LQ and SQ are empty). */
220 bool isEmpty() const;
221 /** Returns if all of the LQs are empty. */
222 bool lqEmpty() const;
223 /** Returns if all of the SQs are empty. */
224 bool sqEmpty() const;
225
226 /** Returns if any of the LQs are full. */
227 bool lqFull();
228 /** Returns if the LQ of a given thread is full. */
229 bool lqFull(ThreadID tid);
230
231 /** Returns if any of the SQs are full. */
232 bool sqFull();
233 /** Returns if the SQ of a given thread is full. */
234 bool sqFull(ThreadID tid);
235
236 /**
237 * Returns if the LSQ is stalled due to a memory operation that must be
238 * replayed.
239 */
240 bool isStalled();
241 /**
242 * Returns if the LSQ of a specific thread is stalled due to a memory
243 * operation that must be replayed.
244 */
245 bool isStalled(ThreadID tid);
246
247 /** Returns whether or not there are any stores to write back to memory. */
248 bool hasStoresToWB();
249
250 /** Returns whether or not a specific thread has any stores to write back
251 * to memory.
252 */
253 bool hasStoresToWB(ThreadID tid)
254 { return thread[tid].hasStoresToWB(); }
255
256 /** Returns the number of stores a specific thread has to write back. */
257 int numStoresToWB(ThreadID tid)
258 { return thread[tid].numStoresToWB(); }
259
260 /** Returns if the LSQ will write back to memory this cycle. */
261 bool willWB();
262 /** Returns if the LSQ of a specific thread will write back to memory this
263 * cycle.
264 */
265 bool willWB(ThreadID tid)
266 { return thread[tid].willWB(); }
267
268 /** Debugging function to print out all instructions. */
269 void dumpInsts() const;
270 /** Debugging function to print out instructions from a specific thread. */
271 void dumpInsts(ThreadID tid) const
272 { thread[tid].dumpInsts(); }
273
274 /** Executes a read operation, using the load specified at the load
275 * index.
276 */
277 Fault read(const RequestPtr &req,
278 RequestPtr &sreqLow, RequestPtr &sreqHigh,
279 int load_idx);
280
281 /** Executes a store operation, using the store specified at the store
282 * index.
283 */
284 Fault write(const RequestPtr &req,
285 const RequestPtr &sreqLow, const RequestPtr &sreqHigh,
286 uint8_t *data, int store_idx);
287
288 /**
289 * Retry the previous send that failed.
290 */
291 void recvReqRetry();
292
293 /**
294 * Handles writing back and completing the load or store that has
295 * returned from memory.
296 *
297 * @param pkt Response packet from the memory sub-system
298 */
299 bool recvTimingResp(PacketPtr pkt);
300
301 void recvTimingSnoopReq(PacketPtr pkt);
302
303 /** The CPU pointer. */
304 O3CPU *cpu;
305
306 /** The IEW stage pointer. */
307 IEW *iewStage;
308
309 protected:
310 /** The LSQ policy for SMT mode. */
311 LSQPolicy lsqPolicy;
312
| 75
76 /** Returns the name of the LSQ. */
77 std::string name() const;
78
79 /** Registers statistics of each LSQ unit. */
80 void regStats();
81
82 /** Sets the pointer to the list of active threads. */
83 void setActiveThreads(std::list<ThreadID> *at_ptr);
84
85 /** Perform sanity checks after a drain. */
86 void drainSanityCheck() const;
87 /** Has the LSQ drained? */
88 bool isDrained() const;
89 /** Takes over execution from another CPU's thread. */
90 void takeOverFrom();
91
92 /** Number of entries needed for the given amount of threads.*/
93 int entryAmount(ThreadID num_threads);
94 void removeEntries(ThreadID tid);
95 /** Reset the max entries for each thread. */
96 void resetEntries();
97 /** Resize the max entries for a thread. */
98 void resizeEntries(unsigned size, ThreadID tid);
99
100 /** Ticks the LSQ. */
101 void tick();
102 /** Ticks a specific LSQ Unit. */
103 void tick(ThreadID tid)
104 { thread[tid].tick(); }
105
106 /** Inserts a load into the LSQ. */
107 void insertLoad(const DynInstPtr &load_inst);
108 /** Inserts a store into the LSQ. */
109 void insertStore(const DynInstPtr &store_inst);
110
111 /** Executes a load. */
112 Fault executeLoad(const DynInstPtr &inst);
113
114 /** Executes a store. */
115 Fault executeStore(const DynInstPtr &inst);
116
117 /**
118 * Commits loads up until the given sequence number for a specific thread.
119 */
120 void commitLoads(InstSeqNum &youngest_inst, ThreadID tid)
121 { thread[tid].commitLoads(youngest_inst); }
122
123 /**
124 * Commits stores up until the given sequence number for a specific thread.
125 */
126 void commitStores(InstSeqNum &youngest_inst, ThreadID tid)
127 { thread[tid].commitStores(youngest_inst); }
128
129 /**
130 * Attempts to write back stores until all cache ports are used or the
131 * interface becomes blocked.
132 */
133 void writebackStores();
134 /** Same as above, but only for one thread. */
135 void writebackStores(ThreadID tid);
136
137 /**
138 * Squash instructions from a thread until the specified sequence number.
139 */
140 void squash(const InstSeqNum &squashed_num, ThreadID tid)
141 { thread[tid].squash(squashed_num); }
142
143 /** Returns whether or not there was a memory ordering violation. */
144 bool violation();
145 /**
146 * Returns whether or not there was a memory ordering violation for a
147 * specific thread.
148 */
149 bool violation(ThreadID tid)
150 { return thread[tid].violation(); }
151
152 /** Gets the instruction that caused the memory ordering violation. */
153 DynInstPtr getMemDepViolator(ThreadID tid)
154 { return thread[tid].getMemDepViolator(); }
155
156 /** Returns the head index of the load queue for a specific thread. */
157 int getLoadHead(ThreadID tid)
158 { return thread[tid].getLoadHead(); }
159
160 /** Returns the sequence number of the head of the load queue. */
161 InstSeqNum getLoadHeadSeqNum(ThreadID tid)
162 {
163 return thread[tid].getLoadHeadSeqNum();
164 }
165
166 /** Returns the head index of the store queue. */
167 int getStoreHead(ThreadID tid)
168 { return thread[tid].getStoreHead(); }
169
170 /** Returns the sequence number of the head of the store queue. */
171 InstSeqNum getStoreHeadSeqNum(ThreadID tid)
172 {
173 return thread[tid].getStoreHeadSeqNum();
174 }
175
176 /** Returns the number of instructions in all of the queues. */
177 int getCount();
178 /** Returns the number of instructions in the queues of one thread. */
179 int getCount(ThreadID tid)
180 { return thread[tid].getCount(); }
181
182 /** Returns the total number of loads in the load queue. */
183 int numLoads();
184 /** Returns the total number of loads for a single thread. */
185 int numLoads(ThreadID tid)
186 { return thread[tid].numLoads(); }
187
188 /** Returns the total number of stores in the store queue. */
189 int numStores();
190 /** Returns the total number of stores for a single thread. */
191 int numStores(ThreadID tid)
192 { return thread[tid].numStores(); }
193
194 /** Returns the number of free load entries. */
195 unsigned numFreeLoadEntries();
196
197 /** Returns the number of free store entries. */
198 unsigned numFreeStoreEntries();
199
200 /** Returns the number of free entries for a specific thread. */
201 unsigned numFreeEntries(ThreadID tid);
202
203 /** Returns the number of free entries in the LQ for a specific thread. */
204 unsigned numFreeLoadEntries(ThreadID tid);
205
206 /** Returns the number of free entries in the SQ for a specific thread. */
207 unsigned numFreeStoreEntries(ThreadID tid);
208
209 /** Returns if the LSQ is full (either LQ or SQ is full). */
210 bool isFull();
211 /**
212 * Returns if the LSQ is full for a specific thread (either LQ or SQ is
213 * full).
214 */
215 bool isFull(ThreadID tid);
216
217 /** Returns if the LSQ is empty (both LQ and SQ are empty). */
218 bool isEmpty() const;
219 /** Returns if all of the LQs are empty. */
220 bool lqEmpty() const;
221 /** Returns if all of the SQs are empty. */
222 bool sqEmpty() const;
223
224 /** Returns if any of the LQs are full. */
225 bool lqFull();
226 /** Returns if the LQ of a given thread is full. */
227 bool lqFull(ThreadID tid);
228
229 /** Returns if any of the SQs are full. */
230 bool sqFull();
231 /** Returns if the SQ of a given thread is full. */
232 bool sqFull(ThreadID tid);
233
234 /**
235 * Returns if the LSQ is stalled due to a memory operation that must be
236 * replayed.
237 */
238 bool isStalled();
239 /**
240 * Returns if the LSQ of a specific thread is stalled due to a memory
241 * operation that must be replayed.
242 */
243 bool isStalled(ThreadID tid);
244
245 /** Returns whether or not there are any stores to write back to memory. */
246 bool hasStoresToWB();
247
248 /** Returns whether or not a specific thread has any stores to write back
249 * to memory.
250 */
251 bool hasStoresToWB(ThreadID tid)
252 { return thread[tid].hasStoresToWB(); }
253
254 /** Returns the number of stores a specific thread has to write back. */
255 int numStoresToWB(ThreadID tid)
256 { return thread[tid].numStoresToWB(); }
257
258 /** Returns if the LSQ will write back to memory this cycle. */
259 bool willWB();
260 /** Returns if the LSQ of a specific thread will write back to memory this
261 * cycle.
262 */
263 bool willWB(ThreadID tid)
264 { return thread[tid].willWB(); }
265
266 /** Debugging function to print out all instructions. */
267 void dumpInsts() const;
268 /** Debugging function to print out instructions from a specific thread. */
269 void dumpInsts(ThreadID tid) const
270 { thread[tid].dumpInsts(); }
271
272 /** Executes a read operation, using the load specified at the load
273 * index.
274 */
275 Fault read(const RequestPtr &req,
276 RequestPtr &sreqLow, RequestPtr &sreqHigh,
277 int load_idx);
278
279 /** Executes a store operation, using the store specified at the store
280 * index.
281 */
282 Fault write(const RequestPtr &req,
283 const RequestPtr &sreqLow, const RequestPtr &sreqHigh,
284 uint8_t *data, int store_idx);
285
286 /**
287 * Retry the previous send that failed.
288 */
289 void recvReqRetry();
290
291 /**
292 * Handles writing back and completing the load or store that has
293 * returned from memory.
294 *
295 * @param pkt Response packet from the memory sub-system
296 */
297 bool recvTimingResp(PacketPtr pkt);
298
299 void recvTimingSnoopReq(PacketPtr pkt);
300
301 /** The CPU pointer. */
302 O3CPU *cpu;
303
304 /** The IEW stage pointer. */
305 IEW *iewStage;
306
307 protected:
308 /** The LSQ policy for SMT mode. */
309 LSQPolicy lsqPolicy;
310
|
313 /** The LSQ units for individual threads. */
314 LSQUnit *thread;
| 311 /** Transform a SMT sharing policy string into a LSQPolicy value. */
312 static LSQPolicy readLSQPolicy(const std::string& policy) {
313 std::string policy_ = policy;
314 std::transform(policy_.begin(), policy_.end(), policy_.begin(),
315 (int(*)(int)) tolower);
316 if (policy_ == "dynamic") {
317 return Dynamic;
318 } else if (policy_ == "partitioned") {
319 return Partitioned;
320 } else if (policy_ == "threshold") {
321 return Threshold;
322 }
323 assert(0 && "Invalid LSQ Sharing Policy.Options Are:{Dynamic,"
324 "Partitioned, Threshold}");
|
315
| 325
|
| 326 // Some compilers complain if there is no return.
327 return Dynamic;
328 }
329
330 /** Auxiliary function to calculate per-thread max LSQ allocation limit.
331 * Depending on a policy, number of entries and possibly number of threads
332 * and threshold, this function calculates how many resources each thread
333 * can occupy at most.
334 */
335 static uint32_t maxLSQAllocation(const LSQPolicy& pol, uint32_t entries,
336 uint32_t numThreads, uint32_t SMTThreshold) {
337 if (pol == Dynamic) {
338 return entries;
339 } else if (pol == Partitioned) {
340 //@todo:make work if part_amt doesnt divide evenly.
341 return entries / numThreads;
342 } else if (pol == Threshold) {
343 //Divide up by threshold amount
344 //@todo: Should threads check the max and the total
345 //amount of the LSQ
346 return SMTThreshold;
347 }
348 return 0;
349 }
350
|
316 /** List of Active Threads in System. */
317 std::list<ThreadID> *activeThreads;
318
319 /** Total Size of LQ Entries. */
320 unsigned LQEntries;
321 /** Total Size of SQ Entries. */
322 unsigned SQEntries;
323
324 /** Max LQ Size - Used to Enforce Sharing Policies. */
325 unsigned maxLQEntries;
326
327 /** Max SQ Size - Used to Enforce Sharing Policies. */
328 unsigned maxSQEntries;
329
| 351 /** List of Active Threads in System. */
352 std::list<ThreadID> *activeThreads;
353
354 /** Total Size of LQ Entries. */
355 unsigned LQEntries;
356 /** Total Size of SQ Entries. */
357 unsigned SQEntries;
358
359 /** Max LQ Size - Used to Enforce Sharing Policies. */
360 unsigned maxLQEntries;
361
362 /** Max SQ Size - Used to Enforce Sharing Policies. */
363 unsigned maxSQEntries;
364
|
| 365 /** The LSQ units for individual threads. */
366 std::vector<LSQUnit> thread;
367
|
330 /** Number of Threads. */
331 ThreadID numThreads;
332};
333
334template <class Impl>
335Fault
336LSQ<Impl>::read(const RequestPtr &req,
337 RequestPtr &sreqLow, RequestPtr &sreqHigh,
338 int load_idx)
339{
340 ThreadID tid = cpu->contextToThread(req->contextId());
341
342 return thread[tid].read(req, sreqLow, sreqHigh, load_idx);
343}
344
345template <class Impl>
346Fault
347LSQ<Impl>::write(const RequestPtr &req,
348 const RequestPtr &sreqLow, const RequestPtr &sreqHigh,
349 uint8_t *data, int store_idx)
350{
351 ThreadID tid = cpu->contextToThread(req->contextId());
352
353 return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx);
354}
355
356#endif // __CPU_O3_LSQ_HH__
| 368 /** Number of Threads. */
369 ThreadID numThreads;
370};
371
372template <class Impl>
373Fault
374LSQ<Impl>::read(const RequestPtr &req,
375 RequestPtr &sreqLow, RequestPtr &sreqHigh,
376 int load_idx)
377{
378 ThreadID tid = cpu->contextToThread(req->contextId());
379
380 return thread[tid].read(req, sreqLow, sreqHigh, load_idx);
381}
382
383template <class Impl>
384Fault
385LSQ<Impl>::write(const RequestPtr &req,
386 const RequestPtr &sreqLow, const RequestPtr &sreqHigh,
387 uint8_t *data, int store_idx)
388{
389 ThreadID tid = cpu->contextToThread(req->contextId());
390
391 return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx);
392}
393
394#endif // __CPU_O3_LSQ_HH__
|