1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Korey Sewell
41 */
42
43#ifndef __CPU_O3_LSQ_HH__
44#define __CPU_O3_LSQ_HH__
45
46#include <map>
47#include <queue>
48
49#include "cpu/o3/lsq_unit.hh"
50#include "cpu/inst_seq.hh"
51#include "mem/port.hh"
52#include "sim/sim_object.hh"
53
54struct DerivO3CPUParams;
55
56template <class Impl>
57class LSQ {
58 public:
59 typedef typename Impl::O3CPU O3CPU;
60 typedef typename Impl::DynInstPtr DynInstPtr;
61 typedef typename Impl::CPUPol::IEW IEW;
62 typedef typename Impl::CPUPol::LSQUnit LSQUnit;
63
64 /** SMT policy. */
65 enum LSQPolicy {
66 Dynamic,
67 Partitioned,
68 Threshold
69 };
70
71 /** Constructs an LSQ with the given parameters. */
72 LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params);
73 ~LSQ() {
74 if (thread) delete [] thread;
75 }
76
77 /** Returns the name of the LSQ. */
78 std::string name() const;
79
80 /** Registers statistics of each LSQ unit. */
81 void regStats();
82
83 /** Sets the pointer to the list of active threads. */
84 void setActiveThreads(std::list<ThreadID> *at_ptr);
85
86 /** Perform sanity checks after a drain. */
87 void drainSanityCheck() const;
88 /** Has the LSQ drained? */
89 bool isDrained() const;
90 /** Takes over execution from another CPU's thread. */
91 void takeOverFrom();
92
93 /** Number of entries needed for the given amount of threads.*/
94 int entryAmount(ThreadID num_threads);
95 void removeEntries(ThreadID tid);
96 /** Reset the max entries for each thread. */
97 void resetEntries();
98 /** Resize the max entries for a thread. */
99 void resizeEntries(unsigned size, ThreadID tid);
100
101 /** Ticks the LSQ. */
102 void tick();
103 /** Ticks a specific LSQ Unit. */
104 void tick(ThreadID tid)
105 { thread[tid].tick(); }
106
107 /** Inserts a load into the LSQ. */
108 void insertLoad(DynInstPtr &load_inst);
109 /** Inserts a store into the LSQ. */
110 void insertStore(DynInstPtr &store_inst);
111
112 /** Executes a load. */
113 Fault executeLoad(DynInstPtr &inst);
114
115 /** Executes a store. */
116 Fault executeStore(DynInstPtr &inst);
117
118 /**
119 * Commits loads up until the given sequence number for a specific thread.
120 */
121 void commitLoads(InstSeqNum &youngest_inst, ThreadID tid)
122 { thread[tid].commitLoads(youngest_inst); }
123
124 /**
125 * Commits stores up until the given sequence number for a specific thread.
126 */
127 void commitStores(InstSeqNum &youngest_inst, ThreadID tid)
128 { thread[tid].commitStores(youngest_inst); }
129
130 /**
131 * Attempts to write back stores until all cache ports are used or the
132 * interface becomes blocked.
133 */
134 void writebackStores();
135 /** Same as above, but only for one thread. */
136 void writebackStores(ThreadID tid);
137
138 /**
139 * Squash instructions from a thread until the specified sequence number.
140 */
141 void squash(const InstSeqNum &squashed_num, ThreadID tid)
142 { thread[tid].squash(squashed_num); }
143
144 /** Returns whether or not there was a memory ordering violation. */
145 bool violation();
146 /**
147 * Returns whether or not there was a memory ordering violation for a
148 * specific thread.
149 */
150 bool violation(ThreadID tid)
151 { return thread[tid].violation(); }
152
153 /** Returns if a load is blocked due to the memory system for a specific
154 * thread.
155 */
156 bool loadBlocked(ThreadID tid)
157 { return thread[tid].loadBlocked(); }
158
159 bool isLoadBlockedHandled(ThreadID tid)
160 { return thread[tid].isLoadBlockedHandled(); }
161
162 void setLoadBlockedHandled(ThreadID tid)
163 { thread[tid].setLoadBlockedHandled(); }
164
165 /** Gets the instruction that caused the memory ordering violation. */
166 DynInstPtr getMemDepViolator(ThreadID tid)
167 { return thread[tid].getMemDepViolator(); }
168
169 /** Returns the head index of the load queue for a specific thread. */
170 int getLoadHead(ThreadID tid)
171 { return thread[tid].getLoadHead(); }
172
173 /** Returns the sequence number of the head of the load queue. */
174 InstSeqNum getLoadHeadSeqNum(ThreadID tid)
175 {
176 return thread[tid].getLoadHeadSeqNum();
177 }
178
179 /** Returns the head index of the store queue. */
180 int getStoreHead(ThreadID tid)
181 { return thread[tid].getStoreHead(); }
182
183 /** Returns the sequence number of the head of the store queue. */
184 InstSeqNum getStoreHeadSeqNum(ThreadID tid)
185 {
186 return thread[tid].getStoreHeadSeqNum();
187 }
188
189 /** Returns the number of instructions in all of the queues. */
190 int getCount();
191 /** Returns the number of instructions in the queues of one thread. */
192 int getCount(ThreadID tid)
193 { return thread[tid].getCount(); }
194
195 /** Returns the total number of loads in the load queue. */
196 int numLoads();
197 /** Returns the total number of loads for a single thread. */
198 int numLoads(ThreadID tid)
199 { return thread[tid].numLoads(); }
200
201 /** Returns the total number of stores in the store queue. */
202 int numStores();
203 /** Returns the total number of stores for a single thread. */
204 int numStores(ThreadID tid)
205 { return thread[tid].numStores(); }
206
207 /** Returns the number of free entries. */
208 unsigned numFreeEntries();
209 /** Returns the number of free entries for a specific thread. */
210 unsigned numFreeEntries(ThreadID tid);
211
212 /** Returns if the LSQ is full (either LQ or SQ is full). */
213 bool isFull();
214 /**
215 * Returns if the LSQ is full for a specific thread (either LQ or SQ is
216 * full).
217 */
218 bool isFull(ThreadID tid);
219
220 /** Returns if the LSQ is empty (both LQ and SQ are empty). */
221 bool isEmpty() const;
222 /** Returns if all of the LQs are empty. */
223 bool lqEmpty() const;
224 /** Returns if all of the SQs are empty. */
225 bool sqEmpty() const;
226
227 /** Returns if any of the LQs are full. */
228 bool lqFull();
229 /** Returns if the LQ of a given thread is full. */
230 bool lqFull(ThreadID tid);
231
232 /** Returns if any of the SQs are full. */
233 bool sqFull();
234 /** Returns if the SQ of a given thread is full. */
235 bool sqFull(ThreadID tid);
236
237 /**
238 * Returns if the LSQ is stalled due to a memory operation that must be
239 * replayed.
240 */
241 bool isStalled();
242 /**
243 * Returns if the LSQ of a specific thread is stalled due to a memory
244 * operation that must be replayed.
245 */
246 bool isStalled(ThreadID tid);
247
248 /** Returns whether or not there are any stores to write back to memory. */
249 bool hasStoresToWB();
250
251 /** Returns whether or not a specific thread has any stores to write back
252 * to memory.
253 */
254 bool hasStoresToWB(ThreadID tid)
255 { return thread[tid].hasStoresToWB(); }
256
257 /** Returns the number of stores a specific thread has to write back. */
258 int numStoresToWB(ThreadID tid)
259 { return thread[tid].numStoresToWB(); }
260
261 /** Returns if the LSQ will write back to memory this cycle. */
262 bool willWB();
263 /** Returns if the LSQ of a specific thread will write back to memory this
264 * cycle.
265 */
266 bool willWB(ThreadID tid)
267 { return thread[tid].willWB(); }
268
269 /** Returns if the cache is currently blocked. */
270 bool cacheBlocked() const
271 { return retryTid != InvalidThreadID; }
272
273 /** Sets the retry thread id, indicating that one of the LSQUnits
274 * tried to access the cache but the cache was blocked. */
275 void setRetryTid(ThreadID tid)
276 { retryTid = tid; }
277
278 /** Debugging function to print out all instructions. */
279 void dumpInsts() const;
280 /** Debugging function to print out instructions from a specific thread. */
281 void dumpInsts(ThreadID tid) const
282 { thread[tid].dumpInsts(); }
283
284 /** Executes a read operation, using the load specified at the load
285 * index.
286 */
287 Fault read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
288 uint8_t *data, int load_idx);
289
290 /** Executes a store operation, using the store specified at the store
291 * index.
292 */
293 Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
294 uint8_t *data, int store_idx);
295
296 /**
297 * Retry the previous send that failed.
298 */
299 void recvRetry();
300
301 /**
302 * Handles writing back and completing the load or store that has
303 * returned from memory.
304 *
305 * @param pkt Response packet from the memory sub-system
306 */
307 bool recvTimingResp(PacketPtr pkt);
308
309 void recvTimingSnoopReq(PacketPtr pkt);
310
311 /** The CPU pointer. */
312 O3CPU *cpu;
313
314 /** The IEW stage pointer. */
315 IEW *iewStage;
316
317 protected:
318 /** The LSQ policy for SMT mode. */
319 LSQPolicy lsqPolicy;
320
321 /** The LSQ units for individual threads. */
322 LSQUnit *thread;
323
324 /** List of Active Threads in System. */
325 std::list<ThreadID> *activeThreads;
326
327 /** Total Size of LQ Entries. */
328 unsigned LQEntries;
329 /** Total Size of SQ Entries. */
330 unsigned SQEntries;
331
332 /** Max LQ Size - Used to Enforce Sharing Policies. */
333 unsigned maxLQEntries;
334
335 /** Max SQ Size - Used to Enforce Sharing Policies. */
336 unsigned maxSQEntries;
337
338 /** Number of Threads. */
339 ThreadID numThreads;
340
341 /** The thread id of the LSQ Unit that is currently waiting for a
342 * retry. */
343 ThreadID retryTid;
344};
345
346template <class Impl>
347Fault
348LSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
349 uint8_t *data, int load_idx)
350{
351 ThreadID tid = req->threadId();
352
353 return thread[tid].read(req, sreqLow, sreqHigh, data, load_idx);
354}
355
356template <class Impl>
357Fault
358LSQ<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
359 uint8_t *data, int store_idx)
360{
361 ThreadID tid = req->threadId();
362
363 return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx);
364}
365
366#endif // __CPU_O3_LSQ_HH__