1/*
2 * Copyright (c) 2011-2012, 2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Korey Sewell
42 */
43
44#ifndef __CPU_O3_LSQ_HH__
45#define __CPU_O3_LSQ_HH__
46
47#include <map>
48#include <queue>
49
50#include "cpu/o3/lsq_unit.hh"
51#include "cpu/inst_seq.hh"
52#include "enums/SMTQueuePolicy.hh"
53#include "mem/port.hh"
54#include "sim/sim_object.hh"
55
56struct DerivO3CPUParams;
57
58template <class Impl>
59class LSQ {
60 public:
61 typedef typename Impl::O3CPU O3CPU;
62 typedef typename Impl::DynInstPtr DynInstPtr;
63 typedef typename Impl::CPUPol::IEW IEW;
64 typedef typename Impl::CPUPol::LSQUnit LSQUnit;
65
66 /** Constructs an LSQ with the given parameters. */
67 LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params);
68 ~LSQ() { }
69
70 /** Returns the name of the LSQ. */
71 std::string name() const;
72
73 /** Registers statistics of each LSQ unit. */
74 void regStats();
75
76 /** Sets the pointer to the list of active threads. */
77 void setActiveThreads(std::list<ThreadID> *at_ptr);
78
79 /** Perform sanity checks after a drain. */
80 void drainSanityCheck() const;
81 /** Has the LSQ drained? */
82 bool isDrained() const;
83 /** Takes over execution from another CPU's thread. */
84 void takeOverFrom();
85
86 /** Number of entries needed for the given amount of threads.*/
87 int entryAmount(ThreadID num_threads);
88 void removeEntries(ThreadID tid);
89 /** Reset the max entries for each thread. */
90 void resetEntries();
91 /** Resize the max entries for a thread. */
92 void resizeEntries(unsigned size, ThreadID tid);
93
94 /** Ticks the LSQ. */
95 void tick();
96 /** Ticks a specific LSQ Unit. */
97 void tick(ThreadID tid)
98 { thread[tid].tick(); }
99
100 /** Inserts a load into the LSQ. */
101 void insertLoad(const DynInstPtr &load_inst);
102 /** Inserts a store into the LSQ. */
103 void insertStore(const DynInstPtr &store_inst);
104
105 /** Executes a load. */
106 Fault executeLoad(const DynInstPtr &inst);
107
108 /** Executes a store. */
109 Fault executeStore(const DynInstPtr &inst);
110
111 /**
112 * Commits loads up until the given sequence number for a specific thread.
113 */
114 void commitLoads(InstSeqNum &youngest_inst, ThreadID tid)
115 { thread[tid].commitLoads(youngest_inst); }
116
117 /**
118 * Commits stores up until the given sequence number for a specific thread.
119 */
120 void commitStores(InstSeqNum &youngest_inst, ThreadID tid)
121 { thread[tid].commitStores(youngest_inst); }
122
123 /**
124 * Attempts to write back stores until all cache ports are used or the
125 * interface becomes blocked.
126 */
127 void writebackStores();
128 /** Same as above, but only for one thread. */
129 void writebackStores(ThreadID tid);
130
131 /**
132 * Squash instructions from a thread until the specified sequence number.
133 */
134 void squash(const InstSeqNum &squashed_num, ThreadID tid)
135 { thread[tid].squash(squashed_num); }
136
137 /** Returns whether or not there was a memory ordering violation. */
138 bool violation();
139 /**
140 * Returns whether or not there was a memory ordering violation for a
141 * specific thread.
142 */
143 bool violation(ThreadID tid)
144 { return thread[tid].violation(); }
145
146 /** Gets the instruction that caused the memory ordering violation. */
147 DynInstPtr getMemDepViolator(ThreadID tid)
148 { return thread[tid].getMemDepViolator(); }
149
150 /** Returns the head index of the load queue for a specific thread. */
151 int getLoadHead(ThreadID tid)
152 { return thread[tid].getLoadHead(); }
153
154 /** Returns the sequence number of the head of the load queue. */
155 InstSeqNum getLoadHeadSeqNum(ThreadID tid)
156 {
157 return thread[tid].getLoadHeadSeqNum();
158 }
159
160 /** Returns the head index of the store queue. */
161 int getStoreHead(ThreadID tid)
162 { return thread[tid].getStoreHead(); }
163
164 /** Returns the sequence number of the head of the store queue. */
165 InstSeqNum getStoreHeadSeqNum(ThreadID tid)
166 {
167 return thread[tid].getStoreHeadSeqNum();
168 }
169
170 /** Returns the number of instructions in all of the queues. */
171 int getCount();
172 /** Returns the number of instructions in the queues of one thread. */
173 int getCount(ThreadID tid)
174 { return thread[tid].getCount(); }
175
176 /** Returns the total number of loads in the load queue. */
177 int numLoads();
178 /** Returns the total number of loads for a single thread. */
179 int numLoads(ThreadID tid)
180 { return thread[tid].numLoads(); }
181
182 /** Returns the total number of stores in the store queue. */
183 int numStores();
184 /** Returns the total number of stores for a single thread. */
185 int numStores(ThreadID tid)
186 { return thread[tid].numStores(); }
187
188 /** Returns the number of free load entries. */
189 unsigned numFreeLoadEntries();
190
191 /** Returns the number of free store entries. */
192 unsigned numFreeStoreEntries();
193
194 /** Returns the number of free entries for a specific thread. */
195 unsigned numFreeEntries(ThreadID tid);
196
197 /** Returns the number of free entries in the LQ for a specific thread. */
198 unsigned numFreeLoadEntries(ThreadID tid);
199
200 /** Returns the number of free entries in the SQ for a specific thread. */
201 unsigned numFreeStoreEntries(ThreadID tid);
202
203 /** Returns if the LSQ is full (either LQ or SQ is full). */
204 bool isFull();
205 /**
206 * Returns if the LSQ is full for a specific thread (either LQ or SQ is
207 * full).
208 */
209 bool isFull(ThreadID tid);
210
211 /** Returns if the LSQ is empty (both LQ and SQ are empty). */
212 bool isEmpty() const;
213 /** Returns if all of the LQs are empty. */
214 bool lqEmpty() const;
215 /** Returns if all of the SQs are empty. */
216 bool sqEmpty() const;
217
218 /** Returns if any of the LQs are full. */
219 bool lqFull();
220 /** Returns if the LQ of a given thread is full. */
221 bool lqFull(ThreadID tid);
222
223 /** Returns if any of the SQs are full. */
224 bool sqFull();
225 /** Returns if the SQ of a given thread is full. */
226 bool sqFull(ThreadID tid);
227
228 /**
229 * Returns if the LSQ is stalled due to a memory operation that must be
230 * replayed.
231 */
232 bool isStalled();
233 /**
234 * Returns if the LSQ of a specific thread is stalled due to a memory
235 * operation that must be replayed.
236 */
237 bool isStalled(ThreadID tid);
238
239 /** Returns whether or not there are any stores to write back to memory. */
240 bool hasStoresToWB();
241
242 /** Returns whether or not a specific thread has any stores to write back
243 * to memory.
244 */
245 bool hasStoresToWB(ThreadID tid)
246 { return thread[tid].hasStoresToWB(); }
247
248 /** Returns the number of stores a specific thread has to write back. */
249 int numStoresToWB(ThreadID tid)
250 { return thread[tid].numStoresToWB(); }
251
252 /** Returns if the LSQ will write back to memory this cycle. */
253 bool willWB();
254 /** Returns if the LSQ of a specific thread will write back to memory this
255 * cycle.
256 */
257 bool willWB(ThreadID tid)
258 { return thread[tid].willWB(); }
259
260 /** Debugging function to print out all instructions. */
261 void dumpInsts() const;
262 /** Debugging function to print out instructions from a specific thread. */
263 void dumpInsts(ThreadID tid) const
264 { thread[tid].dumpInsts(); }
265
266 /** Executes a read operation, using the load specified at the load
267 * index.
268 */
269 Fault read(const RequestPtr &req,
270 RequestPtr &sreqLow, RequestPtr &sreqHigh,
271 int load_idx);
272
273 /** Executes a store operation, using the store specified at the store
274 * index.
275 */
276 Fault write(const RequestPtr &req,
277 const RequestPtr &sreqLow, const RequestPtr &sreqHigh,
278 uint8_t *data, int store_idx);
279
280 /**
281 * Retry the previous send that failed.
282 */
283 void recvReqRetry();
284
285 /**
286 * Handles writing back and completing the load or store that has
287 * returned from memory.
288 *
289 * @param pkt Response packet from the memory sub-system
290 */
291 bool recvTimingResp(PacketPtr pkt);
292
293 void recvTimingSnoopReq(PacketPtr pkt);
294
295 /** The CPU pointer. */
296 O3CPU *cpu;
297
298 /** The IEW stage pointer. */
299 IEW *iewStage;
300
301 protected:
302 /** The LSQ policy for SMT mode. */
303 SMTQueuePolicy lsqPolicy;
304
305 /** Auxiliary function to calculate per-thread max LSQ allocation limit.
306 * Depending on a policy, number of entries and possibly number of threads
307 * and threshold, this function calculates how many resources each thread
308 * can occupy at most.
309 */
310 static uint32_t maxLSQAllocation(SMTQueuePolicy pol, uint32_t entries,
311 uint32_t numThreads, uint32_t SMTThreshold) {
312 if (pol == SMTQueuePolicy::Dynamic) {
313 return entries;
314 } else if (pol == SMTQueuePolicy::Partitioned) {
315 //@todo:make work if part_amt doesnt divide evenly.
316 return entries / numThreads;
317 } else if (pol == SMTQueuePolicy::Threshold) {
318 //Divide up by threshold amount
319 //@todo: Should threads check the max and the total
320 //amount of the LSQ
321 return SMTThreshold;
322 }
323 return 0;
324 }
325
326 /** List of Active Threads in System. */
327 std::list<ThreadID> *activeThreads;
328
329 /** Total Size of LQ Entries. */
330 unsigned LQEntries;
331 /** Total Size of SQ Entries. */
332 unsigned SQEntries;
333
334 /** Max LQ Size - Used to Enforce Sharing Policies. */
335 unsigned maxLQEntries;
336
337 /** Max SQ Size - Used to Enforce Sharing Policies. */
338 unsigned maxSQEntries;
339
340 /** The LSQ units for individual threads. */
341 std::vector<LSQUnit> thread;
342
343 /** Number of Threads. */
344 ThreadID numThreads;
345};
346
347template <class Impl>
348Fault
349LSQ<Impl>::read(const RequestPtr &req,
350 RequestPtr &sreqLow, RequestPtr &sreqHigh,
351 int load_idx)
352{
353 ThreadID tid = cpu->contextToThread(req->contextId());
354
355 return thread[tid].read(req, sreqLow, sreqHigh, load_idx);
356}
357
358template <class Impl>
359Fault
360LSQ<Impl>::write(const RequestPtr &req,
361 const RequestPtr &sreqLow, const RequestPtr &sreqHigh,
362 uint8_t *data, int store_idx)
363{
364 ThreadID tid = cpu->contextToThread(req->contextId());
365
366 return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx);
367}
368
369#endif // __CPU_O3_LSQ_HH__