1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright

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73 LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params);
74
75 /** Returns the name of the LSQ. */
76 std::string name() const;
77
78 /** Registers statistics of each LSQ unit. */
79 void regStats();
80
81 /** Sets the pointer to the list of active threads. */
82 void setActiveThreads(std::list<ThreadID> *at_ptr);
83 /** Switches out the LSQ. */
84 void switchOut();
85 /** Takes over execution from another CPU's thread. */
86 void takeOverFrom();
87
88 /** Number of entries needed for the given amount of threads.*/

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282 uint8_t *data, int load_idx);
283
284 /** Executes a store operation, using the store specified at the store
285 * index.
286 */
287 Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
288 uint8_t *data, int store_idx);
289
290 /**
291 * Retry the previous send that failed.
292 */
293 void recvRetry();
294
295 /**
296 * Handles writing back and completing the load or store that has
297 * returned from memory.
298 *
299 * @param pkt Response packet from the memory sub-system
300 */
301 bool recvTiming(PacketPtr pkt);
302
303 /** The CPU pointer. */
304 O3CPU *cpu;
305
306 /** The IEW stage pointer. */
307 IEW *iewStage;
308
309 protected:
310 /** The LSQ policy for SMT mode. */
311 LSQPolicy lsqPolicy;
312
313 /** The LSQ units for individual threads. */
314 LSQUnit thread[Impl::MaxThreads];
315
316 /** List of Active Threads in System. */

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