inst_queue_impl.hh (9184:a1a8f137b796) inst_queue_impl.hh (9444:ab47fe7f03f0)
1/*
1/*
2 * Copyright (c) 2011 ARM Limited
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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88 numEntries(params->numIQEntries),
89 totalWidth(params->issueWidth),
90 numPhysIntRegs(params->numPhysIntRegs),
91 numPhysFloatRegs(params->numPhysFloatRegs),
92 commitToIEWDelay(params->commitToIEWDelay)
93{
94 assert(fuPool);
95
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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88 numEntries(params->numIQEntries),
89 totalWidth(params->issueWidth),
90 numPhysIntRegs(params->numPhysIntRegs),
91 numPhysFloatRegs(params->numPhysFloatRegs),
92 commitToIEWDelay(params->commitToIEWDelay)
93{
94 assert(fuPool);
95
96 switchedOut = false;
97
98 numThreads = params->numThreads;
99
100 // Set the number of physical registers as the number of int + float
101 numPhysRegs = numPhysIntRegs + numPhysFloatRegs;
102
103 //Create an entry for each physical register within the
104 //dependency graph.
105 dependGraph.resize(numPhysRegs);

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434{
435 timeBuffer = tb_ptr;
436
437 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
438}
439
440template <class Impl>
441void
96 numThreads = params->numThreads;
97
98 // Set the number of physical registers as the number of int + float
99 numPhysRegs = numPhysIntRegs + numPhysFloatRegs;
100
101 //Create an entry for each physical register within the
102 //dependency graph.
103 dependGraph.resize(numPhysRegs);

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432{
433 timeBuffer = tb_ptr;
434
435 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
436}
437
438template <class Impl>
439void
442InstructionQueue<Impl>::switchOut()
440InstructionQueue<Impl>::drainSanityCheck() const
443{
441{
444/*
445 if (!instList[0].empty() || (numEntries != freeEntries) ||
446 !readyInsts[0].empty() || !nonSpecInsts.empty() || !listOrder.empty()) {
447 dumpInsts();
448// assert(0);
449 }
450*/
451 resetState();
452 dependGraph.reset();
453 instsToExecute.clear();
454 switchedOut = true;
455 for (ThreadID tid = 0; tid < numThreads; ++tid) {
456 memDepUnit[tid].switchOut();
457 }
442 assert(dependGraph.empty());
443 assert(instsToExecute.empty());
444 for (ThreadID tid = 0; tid < numThreads; ++tid)
445 memDepUnit[tid].drainSanityCheck();
458}
459
460template <class Impl>
461void
462InstructionQueue<Impl>::takeOverFrom()
463{
446}
447
448template <class Impl>
449void
450InstructionQueue<Impl>::takeOverFrom()
451{
464 switchedOut = false;
452 resetState();
465}
466
467template <class Impl>
468int
469InstructionQueue<Impl>::entryAmount(ThreadID num_threads)
470{
471 if (iqPolicy == Partitioned) {
472 return numEntries / num_threads;

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711 readyIt[op_class] = listOrder.insert(next_it, queue_entry);
712}
713
714template <class Impl>
715void
716InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx)
717{
718 DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum);
453}
454
455template <class Impl>
456int
457InstructionQueue<Impl>::entryAmount(ThreadID num_threads)
458{
459 if (iqPolicy == Partitioned) {
460 return numEntries / num_threads;

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699 readyIt[op_class] = listOrder.insert(next_it, queue_entry);
700}
701
702template <class Impl>
703void
704InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx)
705{
706 DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum);
707 assert(!cpu->switchedOut());
719 // The CPU could have been sleeping until this op completed (*extremely*
720 // long latency op). Wake it if it was. This may be overkill.
708 // The CPU could have been sleeping until this op completed (*extremely*
709 // long latency op). Wake it if it was. This may be overkill.
721 if (isSwitchedOut()) {
722 DPRINTF(IQ, "FU completion not processed, IQ is switched out [sn:%lli]\n",
723 inst->seqNum);
724 return;
725 }
726
727 iewStage->wakeCPU();
728
729 if (fu_idx > -1)
730 fuPool->freeUnitNextCycle(fu_idx);
731
732 // @todo: Ensure that these FU Completions happen at the beginning
733 // of a cycle, otherwise they could add too many instructions to
734 // the queue.

--- 793 unchanged lines hidden --- 		710 iewStage->wakeCPU();
711
712 if (fu_idx > -1)
713 fuPool->freeUnitNextCycle(fu_idx);
714
715 // @todo: Ensure that these FU Completions happen at the beginning
716 // of a cycle, otherwise they could add too many instructions to
717 // the queue.

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