inst_queue_impl.hh (9180:ee8d7a51651d) inst_queue_impl.hh (9184:a1a8f137b796)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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795 listOrder.erase(order_it++);
796
797 ++iqSquashedInstsIssued;
798
799 continue;
800 }
801
802 int idx = -2;
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 786 unchanged lines hidden (view full) ---

795 listOrder.erase(order_it++);
796
797 ++iqSquashedInstsIssued;
798
799 continue;
800 }
801
802 int idx = -2;
803 int op_latency = 1;
803 Cycles op_latency = Cycles(1);
804 ThreadID tid = issuing_inst->threadNumber;
805
806 if (op_class != No_OpClass) {
807 idx = fuPool->getUnit(op_class);
808 issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++;
809 if (idx > -1) {
810 op_latency = fuPool->getOpLatency(op_class);
811 }
812 }
813
814 // If we have an instruction that doesn't require a FU, or a
815 // valid FU, then schedule for execution.
816 if (idx == -2 || idx != -1) {
804 ThreadID tid = issuing_inst->threadNumber;
805
806 if (op_class != No_OpClass) {
807 idx = fuPool->getUnit(op_class);
808 issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++;
809 if (idx > -1) {
810 op_latency = fuPool->getOpLatency(op_class);
811 }
812 }
813
814 // If we have an instruction that doesn't require a FU, or a
815 // valid FU, then schedule for execution.
816 if (idx == -2 || idx != -1) {
817 if (op_latency == 1) {
817 if (op_latency == Cycles(1)) {
818 i2e_info->size++;
819 instsToExecute.push_back(issuing_inst);
820
821 // Add the FU onto the list of FU's to be freed next
822 // cycle if we used one.
823 if (idx >= 0)
824 fuPool->freeUnitNextCycle(idx);
825 } else {
818 i2e_info->size++;
819 instsToExecute.push_back(issuing_inst);
820
821 // Add the FU onto the list of FU's to be freed next
822 // cycle if we used one.
823 if (idx >= 0)
824 fuPool->freeUnitNextCycle(idx);
825 } else {
826 int issue_latency = fuPool->getIssueLatency(op_class);
826 Cycles issue_latency = fuPool->getIssueLatency(op_class);
827 // Generate completion event for the FU
828 FUCompletion *execution = new FUCompletion(issuing_inst,
829 idx, this);
830
831 cpu->schedule(execution,
832 cpu->clockEdge(Cycles(op_latency - 1)));
833
834 // @todo: Enforce that issue_latency == 1 or op_latency
827 // Generate completion event for the FU
828 FUCompletion *execution = new FUCompletion(issuing_inst,
829 idx, this);
830
831 cpu->schedule(execution,
832 cpu->clockEdge(Cycles(op_latency - 1)));
833
834 // @todo: Enforce that issue_latency == 1 or op_latency
835 if (issue_latency > 1) {
835 if (issue_latency > Cycles(1)) {
836 // If FU isn't pipelined, then it must be freed
837 // upon the execution completing.
838 execution->setFreeFU();
839 } else {
840 // Add the FU onto the list of FU's to be freed next cycle.
841 fuPool->freeUnitNextCycle(idx);
842 }
843 }

--- 684 unchanged lines hidden --- 		836 // If FU isn't pipelined, then it must be freed
837 // upon the execution completing.
838 execution->setFreeFU();
839 } else {
840 // Add the FU onto the list of FU's to be freed next cycle.
841 fuPool->freeUnitNextCycle(idx);
842 }
843 }

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