inst_queue_impl.hh (2831:0a42b294727c) inst_queue_impl.hh (2836:c8f549058964)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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682 // Increment the iterator.
683 // This will avoid trying to schedule a certain op class if there are no
684 // FUs that handle it.
685 ListOrderIt order_it = listOrder.begin();
686 ListOrderIt order_end_it = listOrder.end();
687 int total_issued = 0;
688
689 while (total_issued < totalWidth &&
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 673 unchanged lines hidden (view full) ---

682 // Increment the iterator.
683 // This will avoid trying to schedule a certain op class if there are no
684 // FUs that handle it.
685 ListOrderIt order_it = listOrder.begin();
686 ListOrderIt order_end_it = listOrder.end();
687 int total_issued = 0;
688
689 while (total_issued < totalWidth &&
690 iewStage->canIssue() &&
690 order_it != order_end_it) {
691 OpClass op_class = (*order_it).queueType;
692
693 assert(!readyInsts[op_class].empty());
694
695 DynInstPtr issuing_inst = readyInsts[op_class].top();
696
697 assert(issuing_inst->seqNum == (*order_it).oldestInst);

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779 count[tid]--;
780 issuing_inst->clearInIQ();
781 } else {
782 memDepUnit[tid].issue(issuing_inst);
783 }
784
785 listOrder.erase(order_it++);
786 statIssuedInstType[tid][op_class]++;
691 order_it != order_end_it) {
692 OpClass op_class = (*order_it).queueType;
693
694 assert(!readyInsts[op_class].empty());
695
696 DynInstPtr issuing_inst = readyInsts[op_class].top();
697
698 assert(issuing_inst->seqNum == (*order_it).oldestInst);

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780 count[tid]--;
781 issuing_inst->clearInIQ();
782 } else {
783 memDepUnit[tid].issue(issuing_inst);
784 }
785
786 listOrder.erase(order_it++);
787 statIssuedInstType[tid][op_class]++;
788 iewStage->incrWb(issuing_inst->seqNum);
787 } else {
788 statFuBusy[op_class]++;
789 fuBusy[tid]++;
790 ++order_it;
791 }
792 }
793
794 numIssuedDist.sample(total_issued);

--- 595 unchanged lines hidden --- 		789 } else {
790 statFuBusy[op_class]++;
791 fuBusy[tid]++;
792 ++order_it;
793 }
794 }
795
796 numIssuedDist.sample(total_issued);

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