inst_queue_impl.hh (2820:7fde0b0f8f78) inst_queue_impl.hh (2831:0a42b294727c)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
29 */
30
31#include <limits>
32#include <vector>
33
34#include "sim/root.hh"
35
36#include "cpu/o3/fu_pool.hh"

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120 //@todo:make work if part_amt doesnt divide evenly.
121 int part_amt = numEntries / numThreads;
122
123 //Divide ROB up evenly
124 for (int i = 0; i < numThreads; i++) {
125 maxEntries[i] = part_amt;
126 }
127
30 */
31
32#include <limits>
33#include <vector>
34
35#include "sim/root.hh"
36
37#include "cpu/o3/fu_pool.hh"

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121 //@todo:make work if part_amt doesnt divide evenly.
122 int part_amt = numEntries / numThreads;
123
124 //Divide ROB up evenly
125 for (int i = 0; i < numThreads; i++) {
126 maxEntries[i] = part_amt;
127 }
128
128 DPRINTF(Fetch, "IQ sharing policy set to Partitioned:"
129 DPRINTF(IQ, "IQ sharing policy set to Partitioned:"
129 "%i entries per thread.\n",part_amt);
130
131 } else if (policy == "threshold") {
132 iqPolicy = Threshold;
133
134 double threshold = (double)params->smtIQThreshold / 100;
135
136 int thresholdIQ = (int)((double)threshold * numEntries);
137
138 //Divide up by threshold amount
139 for (int i = 0; i < numThreads; i++) {
140 maxEntries[i] = thresholdIQ;
141 }
142
130 "%i entries per thread.\n",part_amt);
131
132 } else if (policy == "threshold") {
133 iqPolicy = Threshold;
134
135 double threshold = (double)params->smtIQThreshold / 100;
136
137 int thresholdIQ = (int)((double)threshold * numEntries);
138
139 //Divide up by threshold amount
140 for (int i = 0; i < numThreads; i++) {
141 maxEntries[i] = thresholdIQ;
142 }
143
143 DPRINTF(Fetch, "IQ sharing policy set to Threshold:"
144 DPRINTF(IQ, "IQ sharing policy set to Threshold:"
144 "%i entries per thread.\n",thresholdIQ);
145 } else {
146 assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
147 "Partitioned, Threshold}");
148 }
149}
150
151template <class Impl>

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681 // Increment the iterator.
682 // This will avoid trying to schedule a certain op class if there are no
683 // FUs that handle it.
684 ListOrderIt order_it = listOrder.begin();
685 ListOrderIt order_end_it = listOrder.end();
686 int total_issued = 0;
687
688 while (total_issued < totalWidth &&
145 "%i entries per thread.\n",thresholdIQ);
146 } else {
147 assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
148 "Partitioned, Threshold}");
149 }
150}
151
152template <class Impl>

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682 // Increment the iterator.
683 // This will avoid trying to schedule a certain op class if there are no
684 // FUs that handle it.
685 ListOrderIt order_it = listOrder.begin();
686 ListOrderIt order_end_it = listOrder.end();
687 int total_issued = 0;
688
689 while (total_issued < totalWidth &&
689 iewStage->canIssue() &&
690 order_it != order_end_it) {
691 OpClass op_class = (*order_it).queueType;
692
693 assert(!readyInsts[op_class].empty());
694
695 DynInstPtr issuing_inst = readyInsts[op_class].top();
696
697 assert(issuing_inst->seqNum == (*order_it).oldestInst);

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779 count[tid]--;
780 issuing_inst->clearInIQ();
781 } else {
782 memDepUnit[tid].issue(issuing_inst);
783 }
784
785 listOrder.erase(order_it++);
786 statIssuedInstType[tid][op_class]++;
690 order_it != order_end_it) {
691 OpClass op_class = (*order_it).queueType;
692
693 assert(!readyInsts[op_class].empty());
694
695 DynInstPtr issuing_inst = readyInsts[op_class].top();
696
697 assert(issuing_inst->seqNum == (*order_it).oldestInst);

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779 count[tid]--;
780 issuing_inst->clearInIQ();
781 } else {
782 memDepUnit[tid].issue(issuing_inst);
783 }
784
785 listOrder.erase(order_it++);
786 statIssuedInstType[tid][op_class]++;
787 iewStage->incrWb(issuing_inst->seqNum);
788 } else {
789 statFuBusy[op_class]++;
790 fuBusy[tid]++;
791 ++order_it;
792 }
793 }
794
795 numIssuedDist.sample(total_issued);

--- 595 unchanged lines hidden --- 		787 } else {
788 statFuBusy[op_class]++;
789 fuBusy[tid]++;
790 ++order_it;
791 }
792 }
793
794 numIssuedDist.sample(total_issued);

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