inst_queue_impl.hh (2731:822b96578fba) inst_queue_impl.hh (2820:7fde0b0f8f78)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 672 unchanged lines hidden (view full) ---

681 // Increment the iterator.
682 // This will avoid trying to schedule a certain op class if there are no
683 // FUs that handle it.
684 ListOrderIt order_it = listOrder.begin();
685 ListOrderIt order_end_it = listOrder.end();
686 int total_issued = 0;
687
688 while (total_issued < totalWidth &&
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 672 unchanged lines hidden (view full) ---

681 // Increment the iterator.
682 // This will avoid trying to schedule a certain op class if there are no
683 // FUs that handle it.
684 ListOrderIt order_it = listOrder.begin();
685 ListOrderIt order_end_it = listOrder.end();
686 int total_issued = 0;
687
688 while (total_issued < totalWidth &&
689 iewStage->canIssue() &&
689 order_it != order_end_it) {
690 OpClass op_class = (*order_it).queueType;
691
692 assert(!readyInsts[op_class].empty());
693
694 DynInstPtr issuing_inst = readyInsts[op_class].top();
695
696 assert(issuing_inst->seqNum == (*order_it).oldestInst);

--- 81 unchanged lines hidden (view full) ---

778 count[tid]--;
779 issuing_inst->clearInIQ();
780 } else {
781 memDepUnit[tid].issue(issuing_inst);
782 }
783
784 listOrder.erase(order_it++);
785 statIssuedInstType[tid][op_class]++;
690 order_it != order_end_it) {
691 OpClass op_class = (*order_it).queueType;
692
693 assert(!readyInsts[op_class].empty());
694
695 DynInstPtr issuing_inst = readyInsts[op_class].top();
696
697 assert(issuing_inst->seqNum == (*order_it).oldestInst);

--- 81 unchanged lines hidden (view full) ---

779 count[tid]--;
780 issuing_inst->clearInIQ();
781 } else {
782 memDepUnit[tid].issue(issuing_inst);
783 }
784
785 listOrder.erase(order_it++);
786 statIssuedInstType[tid][op_class]++;
787 iewStage->incrWb(issuing_inst->seqNum);
786 } else {
787 statFuBusy[op_class]++;
788 fuBusy[tid]++;
789 ++order_it;
790 }
791 }
792
793 numIssuedDist.sample(total_issued);

--- 595 unchanged lines hidden --- 		788 } else {
789 statFuBusy[op_class]++;
790 fuBusy[tid]++;
791 ++order_it;
792 }
793 }
794
795 numIssuedDist.sample(total_issued);

--- 595 unchanged lines hidden ---