inst_queue_impl.hh (2665:a124942bacb8) | inst_queue_impl.hh (2669:f2b336e89d2a) |
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1/* | 1/* |
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan | 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan |
3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the --- 8 unchanged lines hidden (view full) --- 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the --- 8 unchanged lines hidden (view full) --- 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 * 28 * Authors: Kevin Lim | |
29 */ 30 | 27 */ 28 |
31// Todo: 32// Current ordering allows for 0 cycle added-to-scheduled. Could maybe fake 33// it; either do in reverse order, or have added instructions put into a 34// different ready queue that, in scheduleRreadyInsts(), gets put onto the 35// normal ready queue. This would however give only a one cycle delay, 36// but probably is more flexible to actually add in a delay parameter than 37// just running it backwards. 38 | |
39#include <limits> 40#include <vector> 41 42#include "sim/root.hh" 43 | 29#include <limits> 30#include <vector> 31 32#include "sim/root.hh" 33 |
34#include "cpu/o3/fu_pool.hh" |
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44#include "cpu/o3/inst_queue.hh" 45 | 35#include "cpu/o3/inst_queue.hh" 36 |
46// Either compile error or max int due to sign extension. 47// Hack to avoid compile warnings. 48const InstSeqNum MaxInstSeqNum = std::numeric_limits<InstSeqNum>::max(); | 37using namespace std; |
49 50template <class Impl> | 38 39template <class Impl> |
51InstructionQueue<Impl>::InstructionQueue(Params ¶ms) 52 : memDepUnit(params), 53 numEntries(params.numIQEntries), 54 intWidth(params.executeIntWidth), 55 floatWidth(params.executeFloatWidth), 56 branchWidth(params.executeBranchWidth), 57 memoryWidth(params.executeMemoryWidth), 58 totalWidth(params.issueWidth), 59 numPhysIntRegs(params.numPhysIntRegs), 60 numPhysFloatRegs(params.numPhysFloatRegs), 61 commitToIEWDelay(params.commitToIEWDelay) | 40InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 41 int fu_idx, 42 InstructionQueue<Impl> *iq_ptr) 43 : Event(&mainEventQueue, Stat_Event_Pri), 44 inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) |
62{ | 45{ |
63 // Initialize the number of free IQ entries. 64 freeEntries = numEntries; | 46 this->setFlags(Event::AutoDelete); 47} |
65 | 48 |
49template <class Impl> 50void 51InstructionQueue<Impl>::FUCompletion::process() 52{ 53 iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 54 inst = NULL; 55} 56 57 58template <class Impl> 59const char * 60InstructionQueue<Impl>::FUCompletion::description() 61{ 62 return "Functional unit completion event"; 63} 64 65template <class Impl> 66InstructionQueue<Impl>::InstructionQueue(Params *params) 67 : fuPool(params->fuPool), 68 numEntries(params->numIQEntries), 69 totalWidth(params->issueWidth), 70 numPhysIntRegs(params->numPhysIntRegs), 71 numPhysFloatRegs(params->numPhysFloatRegs), 72 commitToIEWDelay(params->commitToIEWDelay) 73{ 74 assert(fuPool); 75 76 switchedOut = false; 77 78 numThreads = params->numberOfThreads; 79 |
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66 // Set the number of physical registers as the number of int + float 67 numPhysRegs = numPhysIntRegs + numPhysFloatRegs; 68 | 80 // Set the number of physical registers as the number of int + float 81 numPhysRegs = numPhysIntRegs + numPhysFloatRegs; 82 |
69 DPRINTF(IQ, "IQ: There are %i physical registers.\n", numPhysRegs); | 83 DPRINTF(IQ, "There are %i physical registers.\n", numPhysRegs); |
70 71 //Create an entry for each physical register within the 72 //dependency graph. | 84 85 //Create an entry for each physical register within the 86 //dependency graph. |
73 dependGraph = new DependencyEntry[numPhysRegs]; | 87 dependGraph.resize(numPhysRegs); |
74 75 // Resize the register scoreboard. 76 regScoreboard.resize(numPhysRegs); 77 | 88 89 // Resize the register scoreboard. 90 regScoreboard.resize(numPhysRegs); 91 |
78 // Initialize all the head pointers to point to NULL, and all the 79 // entries as unready. 80 // Note that in actuality, the registers corresponding to the logical 81 // registers start off as ready. However this doesn't matter for the 82 // IQ as the instruction should have been correctly told if those 83 // registers are ready in rename. Thus it can all be initialized as 84 // unready. 85 for (int i = 0; i < numPhysRegs; ++i) 86 { 87 dependGraph[i].next = NULL; 88 dependGraph[i].inst = NULL; 89 regScoreboard[i] = false; | 92 //Initialize Mem Dependence Units 93 for (int i = 0; i < numThreads; i++) { 94 memDepUnit[i].init(params,i); 95 memDepUnit[i].setIQ(this); |
90 } 91 | 96 } 97 |
98 resetState(); 99 100 string policy = params->smtIQPolicy; 101 102 //Convert string to lowercase 103 std::transform(policy.begin(), policy.end(), policy.begin(), 104 (int(*)(int)) tolower); 105 106 //Figure out resource sharing policy 107 if (policy == "dynamic") { 108 iqPolicy = Dynamic; 109 110 //Set Max Entries to Total ROB Capacity 111 for (int i = 0; i < numThreads; i++) { 112 maxEntries[i] = numEntries; 113 } 114 115 } else if (policy == "partitioned") { 116 iqPolicy = Partitioned; 117 118 //@todo:make work if part_amt doesnt divide evenly. 119 int part_amt = numEntries / numThreads; 120 121 //Divide ROB up evenly 122 for (int i = 0; i < numThreads; i++) { 123 maxEntries[i] = part_amt; 124 } 125 126 DPRINTF(Fetch, "IQ sharing policy set to Partitioned:" 127 "%i entries per thread.\n",part_amt); 128 129 } else if (policy == "threshold") { 130 iqPolicy = Threshold; 131 132 double threshold = (double)params->smtIQThreshold / 100; 133 134 int thresholdIQ = (int)((double)threshold * numEntries); 135 136 //Divide up by threshold amount 137 for (int i = 0; i < numThreads; i++) { 138 maxEntries[i] = thresholdIQ; 139 } 140 141 DPRINTF(Fetch, "IQ sharing policy set to Threshold:" 142 "%i entries per thread.\n",thresholdIQ); 143 } else { 144 assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 145 "Partitioned, Threshold}"); 146 } |
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92} 93 94template <class Impl> | 147} 148 149template <class Impl> |
150InstructionQueue<Impl>::~InstructionQueue() 151{ 152 dependGraph.reset(); 153 cprintf("Nodes traversed: %i, removed: %i\n", 154 dependGraph.nodesTraversed, dependGraph.nodesRemoved); 155} 156 157template <class Impl> 158std::string 159InstructionQueue<Impl>::name() const 160{ 161 return cpu->name() + ".iq"; 162} 163 164template <class Impl> |
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95void 96InstructionQueue<Impl>::regStats() 97{ | 165void 166InstructionQueue<Impl>::regStats() 167{ |
168 using namespace Stats; |
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98 iqInstsAdded 99 .name(name() + ".iqInstsAdded") 100 .desc("Number of instructions added to the IQ (excludes non-spec)") 101 .prereq(iqInstsAdded); 102 103 iqNonSpecInstsAdded 104 .name(name() + ".iqNonSpecInstsAdded") 105 .desc("Number of non-speculative instructions added to the IQ") 106 .prereq(iqNonSpecInstsAdded); 107 | 169 iqInstsAdded 170 .name(name() + ".iqInstsAdded") 171 .desc("Number of instructions added to the IQ (excludes non-spec)") 172 .prereq(iqInstsAdded); 173 174 iqNonSpecInstsAdded 175 .name(name() + ".iqNonSpecInstsAdded") 176 .desc("Number of non-speculative instructions added to the IQ") 177 .prereq(iqNonSpecInstsAdded); 178 |
108// iqIntInstsAdded; | 179 iqInstsIssued 180 .name(name() + ".iqInstsIssued") 181 .desc("Number of instructions issued") 182 .prereq(iqInstsIssued); |
109 110 iqIntInstsIssued 111 .name(name() + ".iqIntInstsIssued") 112 .desc("Number of integer instructions issued") 113 .prereq(iqIntInstsIssued); 114 | 183 184 iqIntInstsIssued 185 .name(name() + ".iqIntInstsIssued") 186 .desc("Number of integer instructions issued") 187 .prereq(iqIntInstsIssued); 188 |
115// iqFloatInstsAdded; 116 | |
117 iqFloatInstsIssued 118 .name(name() + ".iqFloatInstsIssued") 119 .desc("Number of float instructions issued") 120 .prereq(iqFloatInstsIssued); 121 | 189 iqFloatInstsIssued 190 .name(name() + ".iqFloatInstsIssued") 191 .desc("Number of float instructions issued") 192 .prereq(iqFloatInstsIssued); 193 |
122// iqBranchInstsAdded; 123 | |
124 iqBranchInstsIssued 125 .name(name() + ".iqBranchInstsIssued") 126 .desc("Number of branch instructions issued") 127 .prereq(iqBranchInstsIssued); 128 | 194 iqBranchInstsIssued 195 .name(name() + ".iqBranchInstsIssued") 196 .desc("Number of branch instructions issued") 197 .prereq(iqBranchInstsIssued); 198 |
129// iqMemInstsAdded; 130 | |
131 iqMemInstsIssued 132 .name(name() + ".iqMemInstsIssued") 133 .desc("Number of memory instructions issued") 134 .prereq(iqMemInstsIssued); 135 | 199 iqMemInstsIssued 200 .name(name() + ".iqMemInstsIssued") 201 .desc("Number of memory instructions issued") 202 .prereq(iqMemInstsIssued); 203 |
136// iqMiscInstsAdded; 137 | |
138 iqMiscInstsIssued 139 .name(name() + ".iqMiscInstsIssued") 140 .desc("Number of miscellaneous instructions issued") 141 .prereq(iqMiscInstsIssued); 142 143 iqSquashedInstsIssued 144 .name(name() + ".iqSquashedInstsIssued") 145 .desc("Number of squashed instructions issued") 146 .prereq(iqSquashedInstsIssued); 147 | 204 iqMiscInstsIssued 205 .name(name() + ".iqMiscInstsIssued") 206 .desc("Number of miscellaneous instructions issued") 207 .prereq(iqMiscInstsIssued); 208 209 iqSquashedInstsIssued 210 .name(name() + ".iqSquashedInstsIssued") 211 .desc("Number of squashed instructions issued") 212 .prereq(iqSquashedInstsIssued); 213 |
148 iqLoopSquashStalls 149 .name(name() + ".iqLoopSquashStalls") 150 .desc("Number of times issue loop had to restart due to squashed " 151 "inst; mainly for profiling") 152 .prereq(iqLoopSquashStalls); 153 | |
154 iqSquashedInstsExamined 155 .name(name() + ".iqSquashedInstsExamined") 156 .desc("Number of squashed instructions iterated over during squash;" 157 " mainly for profiling") 158 .prereq(iqSquashedInstsExamined); 159 160 iqSquashedOperandsExamined 161 .name(name() + ".iqSquashedOperandsExamined") 162 .desc("Number of squashed operands that are examined and possibly " 163 "removed from graph") 164 .prereq(iqSquashedOperandsExamined); 165 166 iqSquashedNonSpecRemoved 167 .name(name() + ".iqSquashedNonSpecRemoved") 168 .desc("Number of squashed non-spec instructions that were removed") 169 .prereq(iqSquashedNonSpecRemoved); 170 | 214 iqSquashedInstsExamined 215 .name(name() + ".iqSquashedInstsExamined") 216 .desc("Number of squashed instructions iterated over during squash;" 217 " mainly for profiling") 218 .prereq(iqSquashedInstsExamined); 219 220 iqSquashedOperandsExamined 221 .name(name() + ".iqSquashedOperandsExamined") 222 .desc("Number of squashed operands that are examined and possibly " 223 "removed from graph") 224 .prereq(iqSquashedOperandsExamined); 225 226 iqSquashedNonSpecRemoved 227 .name(name() + ".iqSquashedNonSpecRemoved") 228 .desc("Number of squashed non-spec instructions that were removed") 229 .prereq(iqSquashedNonSpecRemoved); 230 |
171 // Tell mem dependence unit to reg stats as well. 172 memDepUnit.regStats(); | 231 queueResDist 232 .init(Num_OpClasses, 0, 99, 2) 233 .name(name() + ".IQ:residence:") 234 .desc("cycles from dispatch to issue") 235 .flags(total | pdf | cdf ) 236 ; 237 for (int i = 0; i < Num_OpClasses; ++i) { 238 queueResDist.subname(i, opClassStrings[i]); 239 } 240 numIssuedDist 241 .init(0,totalWidth,1) 242 .name(name() + ".ISSUE:issued_per_cycle") 243 .desc("Number of insts issued each cycle") 244 .flags(pdf) 245 ; 246/* 247 dist_unissued 248 .init(Num_OpClasses+2) 249 .name(name() + ".ISSUE:unissued_cause") 250 .desc("Reason ready instruction not issued") 251 .flags(pdf | dist) 252 ; 253 for (int i=0; i < (Num_OpClasses + 2); ++i) { 254 dist_unissued.subname(i, unissued_names[i]); 255 } 256*/ 257 statIssuedInstType 258 .init(numThreads,Num_OpClasses) 259 .name(name() + ".ISSUE:FU_type") 260 .desc("Type of FU issued") 261 .flags(total | pdf | dist) 262 ; 263 statIssuedInstType.ysubnames(opClassStrings); 264 265 // 266 // How long did instructions for a particular FU type wait prior to issue 267 // 268 269 issueDelayDist 270 .init(Num_OpClasses,0,99,2) 271 .name(name() + ".ISSUE:") 272 .desc("cycles from operands ready to issue") 273 .flags(pdf | cdf) 274 ; 275 276 for (int i=0; i<Num_OpClasses; ++i) { 277 stringstream subname; 278 subname << opClassStrings[i] << "_delay"; 279 issueDelayDist.subname(i, subname.str()); 280 } 281 282 issueRate 283 .name(name() + ".ISSUE:rate") 284 .desc("Inst issue rate") 285 .flags(total) 286 ; 287 issueRate = iqInstsIssued / cpu->numCycles; 288/* 289 issue_stores 290 .name(name() + ".ISSUE:stores") 291 .desc("Number of stores issued") 292 .flags(total) 293 ; 294 issue_stores = exe_refs - exe_loads; 295*/ 296/* 297 issue_op_rate 298 .name(name() + ".ISSUE:op_rate") 299 .desc("Operation issue rate") 300 .flags(total) 301 ; 302 issue_op_rate = issued_ops / numCycles; 303*/ 304 statFuBusy 305 .init(Num_OpClasses) 306 .name(name() + ".ISSUE:fu_full") 307 .desc("attempts to use FU when none available") 308 .flags(pdf | dist) 309 ; 310 for (int i=0; i < Num_OpClasses; ++i) { 311 statFuBusy.subname(i, opClassStrings[i]); 312 } 313 314 fuBusy 315 .init(numThreads) 316 .name(name() + ".ISSUE:fu_busy_cnt") 317 .desc("FU busy when requested") 318 .flags(total) 319 ; 320 321 fuBusyRate 322 .name(name() + ".ISSUE:fu_busy_rate") 323 .desc("FU busy rate (busy events/executed inst)") 324 .flags(total) 325 ; 326 fuBusyRate = fuBusy / iqInstsIssued; 327 328 for ( int i=0; i < numThreads; i++) { 329 // Tell mem dependence unit to reg stats as well. 330 memDepUnit[i].regStats(); 331 } |
173} 174 175template <class Impl> 176void | 332} 333 334template <class Impl> 335void |
177InstructionQueue<Impl>::setCPU(FullCPU *cpu_ptr) | 336InstructionQueue<Impl>::resetState() |
178{ | 337{ |
179 cpu = cpu_ptr; | 338 //Initialize thread IQ counts 339 for (int i = 0; i <numThreads; i++) { 340 count[i] = 0; 341 instList[i].clear(); 342 } |
180 | 343 |
181 tail = cpu->instList.begin(); | 344 // Initialize the number of free IQ entries. 345 freeEntries = numEntries; 346 347 // Note that in actuality, the registers corresponding to the logical 348 // registers start off as ready. However this doesn't matter for the 349 // IQ as the instruction should have been correctly told if those 350 // registers are ready in rename. Thus it can all be initialized as 351 // unready. 352 for (int i = 0; i < numPhysRegs; ++i) { 353 regScoreboard[i] = false; 354 } 355 356 for (int i = 0; i < numThreads; ++i) { 357 squashedSeqNum[i] = 0; 358 } 359 360 for (int i = 0; i < Num_OpClasses; ++i) { 361 while (!readyInsts[i].empty()) 362 readyInsts[i].pop(); 363 queueOnList[i] = false; 364 readyIt[i] = listOrder.end(); 365 } 366 nonSpecInsts.clear(); 367 listOrder.clear(); |
182} 183 184template <class Impl> 185void | 368} 369 370template <class Impl> 371void |
186InstructionQueue<Impl>::setIssueToExecuteQueue( 187 TimeBuffer<IssueStruct> *i2e_ptr) | 372InstructionQueue<Impl>::setActiveThreads(list<unsigned> *at_ptr) |
188{ | 373{ |
189 DPRINTF(IQ, "IQ: Set the issue to execute queue.\n"); | 374 DPRINTF(IQ, "Setting active threads list pointer.\n"); 375 activeThreads = at_ptr; 376} 377 378template <class Impl> 379void 380InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 381{ 382 DPRINTF(IQ, "Set the issue to execute queue.\n"); |
190 issueToExecuteQueue = i2e_ptr; 191} 192 193template <class Impl> 194void 195InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 196{ | 383 issueToExecuteQueue = i2e_ptr; 384} 385 386template <class Impl> 387void 388InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 389{ |
197 DPRINTF(IQ, "IQ: Set the time buffer.\n"); | 390 DPRINTF(IQ, "Set the time buffer.\n"); |
198 timeBuffer = tb_ptr; 199 200 fromCommit = timeBuffer->getWire(-commitToIEWDelay); 201} 202 203template <class Impl> | 391 timeBuffer = tb_ptr; 392 393 fromCommit = timeBuffer->getWire(-commitToIEWDelay); 394} 395 396template <class Impl> |
397void 398InstructionQueue<Impl>::switchOut() 399{ 400 resetState(); 401 dependGraph.reset(); 402 switchedOut = true; 403 for (int i = 0; i < numThreads; ++i) { 404 memDepUnit[i].switchOut(); 405 } 406} 407 408template <class Impl> 409void 410InstructionQueue<Impl>::takeOverFrom() 411{ 412 switchedOut = false; 413} 414 415template <class Impl> 416int 417InstructionQueue<Impl>::entryAmount(int num_threads) 418{ 419 if (iqPolicy == Partitioned) { 420 return numEntries / num_threads; 421 } else { 422 return 0; 423 } 424} 425 426 427template <class Impl> 428void 429InstructionQueue<Impl>::resetEntries() 430{ 431 if (iqPolicy != Dynamic || numThreads > 1) { 432 int active_threads = (*activeThreads).size(); 433 434 list<unsigned>::iterator threads = (*activeThreads).begin(); 435 list<unsigned>::iterator list_end = (*activeThreads).end(); 436 437 while (threads != list_end) { 438 if (iqPolicy == Partitioned) { 439 maxEntries[*threads++] = numEntries / active_threads; 440 } else if(iqPolicy == Threshold && active_threads == 1) { 441 maxEntries[*threads++] = numEntries; 442 } 443 } 444 } 445} 446 447template <class Impl> |
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204unsigned 205InstructionQueue<Impl>::numFreeEntries() 206{ 207 return freeEntries; 208} 209 | 448unsigned 449InstructionQueue<Impl>::numFreeEntries() 450{ 451 return freeEntries; 452} 453 |
454template <class Impl> 455unsigned 456InstructionQueue<Impl>::numFreeEntries(unsigned tid) 457{ 458 return maxEntries[tid] - count[tid]; 459} 460 |
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210// Might want to do something more complex if it knows how many instructions 211// will be issued this cycle. 212template <class Impl> 213bool 214InstructionQueue<Impl>::isFull() 215{ 216 if (freeEntries == 0) { 217 return(true); 218 } else { 219 return(false); 220 } 221} 222 223template <class Impl> | 461// Might want to do something more complex if it knows how many instructions 462// will be issued this cycle. 463template <class Impl> 464bool 465InstructionQueue<Impl>::isFull() 466{ 467 if (freeEntries == 0) { 468 return(true); 469 } else { 470 return(false); 471 } 472} 473 474template <class Impl> |
475bool 476InstructionQueue<Impl>::isFull(unsigned tid) 477{ 478 if (numFreeEntries(tid) == 0) { 479 return(true); 480 } else { 481 return(false); 482 } 483} 484 485template <class Impl> 486bool 487InstructionQueue<Impl>::hasReadyInsts() 488{ 489 if (!listOrder.empty()) { 490 return true; 491 } 492 493 for (int i = 0; i < Num_OpClasses; ++i) { 494 if (!readyInsts[i].empty()) { 495 return true; 496 } 497 } 498 499 return false; 500} 501 502template <class Impl> |
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224void 225InstructionQueue<Impl>::insert(DynInstPtr &new_inst) 226{ 227 // Make sure the instruction is valid 228 assert(new_inst); 229 | 503void 504InstructionQueue<Impl>::insert(DynInstPtr &new_inst) 505{ 506 // Make sure the instruction is valid 507 assert(new_inst); 508 |
230 DPRINTF(IQ, "IQ: Adding instruction PC %#x to the IQ.\n", 231 new_inst->readPC()); | 509 DPRINTF(IQ, "Adding instruction [sn:%lli] PC %#x to the IQ.\n", 510 new_inst->seqNum, new_inst->readPC()); |
232 | 511 |
233 // Check if there are any free entries. Panic if there are none. 234 // Might want to have this return a fault in the future instead of 235 // panicing. | |
236 assert(freeEntries != 0); 237 | 512 assert(freeEntries != 0); 513 |
238 // If the IQ currently has nothing in it, then there's a possibility 239 // that the tail iterator is invalid (might have been pointing at an 240 // instruction that was retired). Reset the tail iterator. 241 if (freeEntries == numEntries) { 242 tail = cpu->instList.begin(); 243 } | 514 instList[new_inst->threadNumber].push_back(new_inst); |
244 | 515 |
245 // Move the tail iterator. Instructions may not have been issued 246 // to the IQ, so we may have to increment the iterator more than once. 247 while ((*tail) != new_inst) { 248 tail++; 249 250 // Make sure the tail iterator points at something legal. 251 assert(tail != cpu->instList.end()); 252 } 253 254 255 // Decrease the number of free entries. | |
256 --freeEntries; 257 | 516 --freeEntries; 517 |
518 new_inst->setInIQ(); 519 |
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258 // Look through its source registers (physical regs), and mark any 259 // dependencies. 260 addToDependents(new_inst); 261 262 // Have this instruction set itself as the producer of its destination 263 // register(s). | 520 // Look through its source registers (physical regs), and mark any 521 // dependencies. 522 addToDependents(new_inst); 523 524 // Have this instruction set itself as the producer of its destination 525 // register(s). |
264 createDependency(new_inst); | 526 addToProducers(new_inst); |
265 | 527 |
266 // If it's a memory instruction, add it to the memory dependency 267 // unit. | |
268 if (new_inst->isMemRef()) { | 528 if (new_inst->isMemRef()) { |
269 memDepUnit.insert(new_inst); 270 // Uh..forgot to look it up and put it on the proper dependency list 271 // if the instruction should not go yet. | 529 memDepUnit[new_inst->threadNumber].insert(new_inst); |
272 } else { | 530 } else { |
273 // If the instruction is ready then add it to the ready list. | |
274 addIfReady(new_inst); 275 } 276 277 ++iqInstsAdded; 278 | 531 addIfReady(new_inst); 532 } 533 534 ++iqInstsAdded; 535 |
536 count[new_inst->threadNumber]++; 537 |
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279 assert(freeEntries == (numEntries - countInsts())); 280} 281 282template <class Impl> 283void | 538 assert(freeEntries == (numEntries - countInsts())); 539} 540 541template <class Impl> 542void |
284InstructionQueue | 543InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst) |
285{ | 544{ |
286 nonSpecInsts[inst->seqNum] = inst; 287 | |
288 // @todo: Clean up this code; can do it by setting inst as unable 289 // to issue, then calling normal insert on the inst. 290 | 545 // @todo: Clean up this code; can do it by setting inst as unable 546 // to issue, then calling normal insert on the inst. 547 |
291 // Make sure the instruction is valid 292 assert(inst); | 548 assert(new_inst); |
293 | 549 |
294 DPRINTF(IQ, "IQ: Adding instruction PC %#x to the IQ.\n", 295 inst->readPC()); | 550 nonSpecInsts[new_inst->seqNum] = new_inst; |
296 | 551 |
297 // Check if there are any free entries. Panic if there are none. 298 // Might want to have this return a fault in the future instead of 299 // panicing. | 552 DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %#x " 553 "to the IQ.\n", 554 new_inst->seqNum, new_inst->readPC()); 555 |
300 assert(freeEntries != 0); 301 | 556 assert(freeEntries != 0); 557 |
302 // If the IQ currently has nothing in it, then there's a possibility 303 // that the tail iterator is invalid (might have been pointing at an 304 // instruction that was retired). Reset the tail iterator. 305 if (freeEntries == numEntries) { 306 tail = cpu->instList.begin(); 307 } | 558 instList[new_inst->threadNumber].push_back(new_inst); |
308 | 559 |
309 // Move the tail iterator. Instructions may not have been issued 310 // to the IQ, so we may have to increment the iterator more than once. 311 while ((*tail) != inst) { 312 tail++; 313 314 // Make sure the tail iterator points at something legal. 315 assert(tail != cpu->instList.end()); 316 } 317 318 // Decrease the number of free entries. | |
319 --freeEntries; 320 | 560 --freeEntries; 561 |
562 new_inst->setInIQ(); 563 |
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321 // Have this instruction set itself as the producer of its destination 322 // register(s). | 564 // Have this instruction set itself as the producer of its destination 565 // register(s). |
323 createDependency(inst); | 566 addToProducers(new_inst); |
324 325 // If it's a memory instruction, add it to the memory dependency 326 // unit. | 567 568 // If it's a memory instruction, add it to the memory dependency 569 // unit. |
327 if (inst->isMemRef()) { 328 memDepUnit.insertNonSpec(inst); | 570 if (new_inst->isMemRef()) { 571 memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); |
329 } 330 331 ++iqNonSpecInstsAdded; | 572 } 573 574 ++iqNonSpecInstsAdded; |
575 576 count[new_inst->threadNumber]++; 577 578 assert(freeEntries == (numEntries - countInsts())); |
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332} 333 | 579} 580 |
334// Slightly hack function to advance the tail iterator in the case that 335// the IEW stage issues an instruction that is not added to the IQ. This 336// is needed in case a long chain of such instructions occurs. 337// I don't think this is used anymore. | |
338template <class Impl> 339void | 581template <class Impl> 582void |
340InstructionQueue<Impl>::advanceTail(DynInstPtr &inst) | 583InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst) |
341{ | 584{ |
342 // Make sure the instruction is valid 343 assert(inst); | 585 memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); |
344 | 586 |
345 DPRINTF(IQ, "IQ: Adding instruction PC %#x to the IQ.\n", 346 inst->readPC()); | 587 insertNonSpec(barr_inst); 588} |
347 | 589 |
348 // Check if there are any free entries. Panic if there are none. 349 // Might want to have this return a fault in the future instead of 350 // panicing. 351 assert(freeEntries != 0); 352 353 // If the IQ currently has nothing in it, then there's a possibility 354 // that the tail iterator is invalid (might have been pointing at an 355 // instruction that was retired). Reset the tail iterator. 356 if (freeEntries == numEntries) { 357 tail = cpu->instList.begin(); 358 } 359 360 // Move the tail iterator. Instructions may not have been issued 361 // to the IQ, so we may have to increment the iterator more than once. 362 while ((*tail) != inst) { 363 tail++; 364 365 // Make sure the tail iterator points at something legal. 366 assert(tail != cpu->instList.end()); 367 } 368 369 assert(freeEntries <= numEntries); 370 371 // Have this instruction set itself as the producer of its destination 372 // register(s). 373 createDependency(inst); | 590template <class Impl> 591typename Impl::DynInstPtr 592InstructionQueue<Impl>::getInstToExecute() 593{ 594 assert(!instsToExecute.empty()); 595 DynInstPtr inst = instsToExecute.front(); 596 instsToExecute.pop_front(); 597 return inst; |
374} 375 | 598} 599 |
376// Need to make sure the number of float and integer instructions 377// issued does not exceed the total issue bandwidth. 378// @todo: Figure out a better way to remove the squashed items from the 379// lists. Checking the top item of each list to see if it's squashed 380// wastes time and forces jumps. | |
381template <class Impl> 382void | 600template <class Impl> 601void |
383InstructionQueue<Impl>::scheduleReadyInsts() | 602InstructionQueue<Impl>::addToOrderList(OpClass op_class) |
384{ | 603{ |
385 DPRINTF(IQ, "IQ: Attempting to schedule ready instructions from " 386 "the IQ.\n"); | 604 assert(!readyInsts[op_class].empty()); |
387 | 605 |
388 int int_issued = 0; 389 int float_issued = 0; 390 int branch_issued = 0; 391 int memory_issued = 0; 392 int squashed_issued = 0; 393 int total_issued = 0; | 606 ListOrderEntry queue_entry; |
394 | 607 |
395 IssueStruct *i2e_info = issueToExecuteQueue->access(0); | 608 queue_entry.queueType = op_class; |
396 | 609 |
397 bool insts_available = !readyBranchInsts.empty() || 398 !readyIntInsts.empty() || 399 !readyFloatInsts.empty() || 400 !memDepUnit.empty() || 401 !readyMiscInsts.empty() || 402 !squashedInsts.empty(); | 610 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; |
403 | 611 |
404 // Note: Requires a globally defined constant. 405 InstSeqNum oldest_inst = MaxInstSeqNum; 406 InstList list_with_oldest = None; | 612 ListOrderIt list_it = listOrder.begin(); 613 ListOrderIt list_end_it = listOrder.end(); |
407 | 614 |
408 // Temporary values. 409 DynInstPtr int_head_inst; 410 DynInstPtr float_head_inst; 411 DynInstPtr branch_head_inst; 412 DynInstPtr mem_head_inst; 413 DynInstPtr misc_head_inst; 414 DynInstPtr squashed_head_inst; | 615 while (list_it != list_end_it) { 616 if ((*list_it).oldestInst > queue_entry.oldestInst) { 617 break; 618 } |
415 | 619 |
416 // Somewhat nasty code to look at all of the lists where issuable 417 // instructions are located, and choose the oldest instruction among 418 // those lists. Consider a rewrite in the future. 419 while (insts_available && total_issued < totalWidth) 420 { 421 // Set this to false. Each if-block is required to set it to true 422 // if there were instructions available this check. This will cause 423 // this loop to run once more than necessary, but avoids extra calls. 424 insts_available = false; | 620 list_it++; 621 } |
425 | 622 |
426 oldest_inst = MaxInstSeqNum; | 623 readyIt[op_class] = listOrder.insert(list_it, queue_entry); 624 queueOnList[op_class] = true; 625} |
427 | 626 |
428 list_with_oldest = None; | 627template <class Impl> 628void 629InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 630{ 631 // Get iterator of next item on the list 632 // Delete the original iterator 633 // Determine if the next item is either the end of the list or younger 634 // than the new instruction. If so, then add in a new iterator right here. 635 // If not, then move along. 636 ListOrderEntry queue_entry; 637 OpClass op_class = (*list_order_it).queueType; 638 ListOrderIt next_it = list_order_it; |
429 | 639 |
430 if (!readyIntInsts.empty() && 431 int_issued < intWidth) { | 640 ++next_it; |
432 | 641 |
433 insts_available = true; | 642 queue_entry.queueType = op_class; 643 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; |
434 | 644 |
435 int_head_inst = readyIntInsts.top(); | 645 while (next_it != listOrder.end() && 646 (*next_it).oldestInst < queue_entry.oldestInst) { 647 ++next_it; 648 } |
436 | 649 |
437 if (int_head_inst->isSquashed()) { 438 readyIntInsts.pop(); | 650 readyIt[op_class] = listOrder.insert(next_it, queue_entry); 651} |
439 | 652 |
440 ++iqLoopSquashStalls; | 653template <class Impl> 654void 655InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 656{ 657 // The CPU could have been sleeping until this op completed (*extremely* 658 // long latency op). Wake it if it was. This may be overkill. 659 if (isSwitchedOut()) { 660 return; 661 } |
441 | 662 |
442 continue; 443 } | 663 iewStage->wakeCPU(); |
444 | 664 |
445 oldest_inst = int_head_inst->seqNum; | 665 if (fu_idx > -1) 666 fuPool->freeUnitNextCycle(fu_idx); |
446 | 667 |
447 list_with_oldest = Int; 448 } | 668 // @todo: Ensure that these FU Completions happen at the beginning 669 // of a cycle, otherwise they could add too many instructions to 670 // the queue. 671 // @todo: This could break if there's multiple multi-cycle ops 672 // finishing on this cycle. Maybe implement something like 673 // instToCommit in iew_impl.hh. 674 issueToExecuteQueue->access(0)->size++; 675 instsToExecute.push_back(inst); 676// int &size = issueToExecuteQueue->access(0)->size; |
449 | 677 |
450 if (!readyFloatInsts.empty() && 451 float_issued < floatWidth) { | 678// issueToExecuteQueue->access(0)->insts[size++] = inst; 679} |
452 | 680 |
453 insts_available = true; | 681// @todo: Figure out a better way to remove the squashed items from the 682// lists. Checking the top item of each list to see if it's squashed 683// wastes time and forces jumps. 684template <class Impl> 685void 686InstructionQueue<Impl>::scheduleReadyInsts() 687{ 688 DPRINTF(IQ, "Attempting to schedule ready instructions from " 689 "the IQ.\n"); |
454 | 690 |
455 float_head_inst = readyFloatInsts.top(); | 691 IssueStruct *i2e_info = issueToExecuteQueue->access(0); |
456 | 692 |
457 if (float_head_inst->isSquashed()) { 458 readyFloatInsts.pop(); | 693 // Have iterator to head of the list 694 // While I haven't exceeded bandwidth or reached the end of the list, 695 // Try to get a FU that can do what this op needs. 696 // If successful, change the oldestInst to the new top of the list, put 697 // the queue in the proper place in the list. 698 // Increment the iterator. 699 // This will avoid trying to schedule a certain op class if there are no 700 // FUs that handle it. 701 ListOrderIt order_it = listOrder.begin(); 702 ListOrderIt order_end_it = listOrder.end(); 703 int total_issued = 0; |
459 | 704 |
460 ++iqLoopSquashStalls; | 705 while (total_issued < totalWidth && 706 order_it != order_end_it) { 707 OpClass op_class = (*order_it).queueType; |
461 | 708 |
462 continue; 463 } else if (float_head_inst->seqNum < oldest_inst) { 464 oldest_inst = float_head_inst->seqNum; | 709 assert(!readyInsts[op_class].empty()); |
465 | 710 |
466 list_with_oldest = Float; 467 } 468 } | 711 DynInstPtr issuing_inst = readyInsts[op_class].top(); |
469 | 712 |
470 if (!readyBranchInsts.empty() && 471 branch_issued < branchWidth) { | 713 assert(issuing_inst->seqNum == (*order_it).oldestInst); |
472 | 714 |
473 insts_available = true; | 715 if (issuing_inst->isSquashed()) { 716 readyInsts[op_class].pop(); |
474 | 717 |
475 branch_head_inst = readyBranchInsts.top(); | 718 if (!readyInsts[op_class].empty()) { 719 moveToYoungerInst(order_it); 720 } else { 721 readyIt[op_class] = listOrder.end(); 722 queueOnList[op_class] = false; 723 } |
476 | 724 |
477 if (branch_head_inst->isSquashed()) { 478 readyBranchInsts.pop(); | 725 listOrder.erase(order_it++); |
479 | 726 |
480 ++iqLoopSquashStalls; | 727 ++iqSquashedInstsIssued; |
481 | 728 |
482 continue; 483 } else if (branch_head_inst->seqNum < oldest_inst) { 484 oldest_inst = branch_head_inst->seqNum; 485 486 list_with_oldest = Branch; 487 } 488 | 729 continue; |
489 } 490 | 730 } 731 |
491 if (!memDepUnit.empty() && 492 memory_issued < memoryWidth) { | 732 int idx = -2; 733 int op_latency = 1; 734 int tid = issuing_inst->threadNumber; |
493 | 735 |
494 insts_available = true; | 736 if (op_class != No_OpClass) { 737 idx = fuPool->getUnit(op_class); |
495 | 738 |
496 mem_head_inst = memDepUnit.top(); 497 498 if (mem_head_inst->isSquashed()) { 499 memDepUnit.pop(); 500 501 ++iqLoopSquashStalls; 502 503 continue; 504 } else if (mem_head_inst->seqNum < oldest_inst) { 505 oldest_inst = mem_head_inst->seqNum; 506 507 list_with_oldest = Memory; | 739 if (idx > -1) { 740 op_latency = fuPool->getOpLatency(op_class); |
508 } 509 } 510 | 741 } 742 } 743 |
511 if (!readyMiscInsts.empty()) { | 744 if (idx == -2 || idx != -1) { 745 if (op_latency == 1) { 746// i2e_info->insts[exec_queue_slot++] = issuing_inst; 747 i2e_info->size++; 748 instsToExecute.push_back(issuing_inst); |
512 | 749 |
513 insts_available = true; | 750 // Add the FU onto the list of FU's to be freed next 751 // cycle if we used one. 752 if (idx >= 0) 753 fuPool->freeUnitNextCycle(idx); 754 } else { 755 int issue_latency = fuPool->getIssueLatency(op_class); 756 // Generate completion event for the FU 757 FUCompletion *execution = new FUCompletion(issuing_inst, 758 idx, this); |
514 | 759 |
515 misc_head_inst = readyMiscInsts.top(); | 760 execution->schedule(curTick + cpu->cycles(issue_latency - 1)); |
516 | 761 |
517 if (misc_head_inst->isSquashed()) { 518 readyMiscInsts.pop(); | 762 // @todo: Enforce that issue_latency == 1 or op_latency 763 if (issue_latency > 1) { 764 execution->setFreeFU(); 765 } else { 766 // @todo: Not sure I'm accounting for the 767 // multi-cycle op in a pipelined FU properly, or 768 // the number of instructions issued in one cycle. 769// i2e_info->insts[exec_queue_slot++] = issuing_inst; 770// i2e_info->size++; |
519 | 771 |
520 ++iqLoopSquashStalls; 521 522 continue; 523 } else if (misc_head_inst->seqNum < oldest_inst) { 524 oldest_inst = misc_head_inst->seqNum; 525 526 list_with_oldest = Misc; | 772 // Add the FU onto the list of FU's to be freed next cycle. 773 fuPool->freeUnitNextCycle(idx); 774 } |
527 } | 775 } |
528 } | |
529 | 776 |
530 if (!squashedInsts.empty()) { | 777 DPRINTF(IQ, "Thread %i: Issuing instruction PC %#x " 778 "[sn:%lli]\n", 779 tid, issuing_inst->readPC(), 780 issuing_inst->seqNum); |
531 | 781 |
532 insts_available = true; | 782 readyInsts[op_class].pop(); |
533 | 783 |
534 squashed_head_inst = squashedInsts.top(); 535 536 if (squashed_head_inst->seqNum < oldest_inst) { 537 list_with_oldest = Squashed; | 784 if (!readyInsts[op_class].empty()) { 785 moveToYoungerInst(order_it); 786 } else { 787 readyIt[op_class] = listOrder.end(); 788 queueOnList[op_class] = false; |
538 } 539 | 789 } 790 |
540 } | 791 issuing_inst->setIssued(); 792 ++total_issued; |
541 | 793 |
542 DynInstPtr issuing_inst = NULL; | 794 if (!issuing_inst->isMemRef()) { 795 // Memory instructions can not be freed from the IQ until they 796 // complete. 797 ++freeEntries; 798 count[tid]--; 799 issuing_inst->removeInIQ(); 800 } else { 801 memDepUnit[tid].issue(issuing_inst); 802 } |
543 | 803 |
544 switch (list_with_oldest) { 545 case None: 546 DPRINTF(IQ, "IQ: Not able to schedule any instructions. Issuing " 547 "inst is %#x.\n", issuing_inst); 548 break; 549 550 case Int: 551 issuing_inst = int_head_inst; 552 readyIntInsts.pop(); 553 ++int_issued; 554 DPRINTF(IQ, "IQ: Issuing integer instruction PC %#x.\n", 555 issuing_inst->readPC()); 556 break; 557 558 case Float: 559 issuing_inst = float_head_inst; 560 readyFloatInsts.pop(); 561 ++float_issued; 562 DPRINTF(IQ, "IQ: Issuing float instruction PC %#x.\n", 563 issuing_inst->readPC()); 564 break; 565 566 case Branch: 567 issuing_inst = branch_head_inst; 568 readyBranchInsts.pop(); 569 ++branch_issued; 570 DPRINTF(IQ, "IQ: Issuing branch instruction PC %#x.\n", 571 issuing_inst->readPC()); 572 break; 573 574 case Memory: 575 issuing_inst = mem_head_inst; 576 577 memDepUnit.pop(); 578 ++memory_issued; 579 DPRINTF(IQ, "IQ: Issuing memory instruction PC %#x.\n", 580 issuing_inst->readPC()); 581 break; 582 583 case Misc: 584 issuing_inst = misc_head_inst; 585 readyMiscInsts.pop(); 586 587 ++iqMiscInstsIssued; 588 589 DPRINTF(IQ, "IQ: Issuing a miscellaneous instruction PC %#x.\n", 590 issuing_inst->readPC()); 591 break; 592 593 case Squashed: 594 assert(0 && "Squashed insts should not issue any more!"); 595 squashedInsts.pop(); 596 // Set the squashed instruction as able to commit so that commit 597 // can just drop it from the ROB. This is a bit faked. 598 ++squashed_issued; 599 ++freeEntries; 600 601 DPRINTF(IQ, "IQ: Issuing squashed instruction PC %#x.\n", 602 squashed_head_inst->readPC()); 603 break; | 804 listOrder.erase(order_it++); 805 statIssuedInstType[tid][op_class]++; 806 } else { 807 statFuBusy[op_class]++; 808 fuBusy[tid]++; 809 ++order_it; |
604 } | 810 } |
811 } |
|
605 | 812 |
606 if (list_with_oldest != None && list_with_oldest != Squashed) { 607 i2e_info->insts[total_issued] = issuing_inst; 608 i2e_info->size++; | 813 numIssuedDist.sample(total_issued); 814 iqInstsIssued+= total_issued; |
609 | 815 |
610 issuing_inst->setIssued(); 611 612 ++freeEntries; 613 ++total_issued; 614 } 615 616 assert(freeEntries == (numEntries - countInsts())); | 816 if (total_issued) { 817 cpu->activityThisCycle(); 818 } else { 819 DPRINTF(IQ, "Not able to schedule any instructions.\n"); |
617 } | 820 } |
618 619 iqIntInstsIssued += int_issued; 620 iqFloatInstsIssued += float_issued; 621 iqBranchInstsIssued += branch_issued; 622 iqMemInstsIssued += memory_issued; 623 iqSquashedInstsIssued += squashed_issued; | |
624} 625 626template <class Impl> 627void 628InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 629{ | 821} 822 823template <class Impl> 824void 825InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 826{ |
630 DPRINTF(IQ, "IQ: Marking nonspeculative instruction with sequence " 631 "number %i as ready to execute.\n", inst); | 827 DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 828 "to execute.\n", inst); |
632 | 829 |
633 non_spec_it_t inst_it = nonSpecInsts.find(inst); | 830 NonSpecMapIt inst_it = nonSpecInsts.find(inst); |
634 635 assert(inst_it != nonSpecInsts.end()); 636 | 831 832 assert(inst_it != nonSpecInsts.end()); 833 |
637 // Mark this instruction as ready to issue. | 834 unsigned tid = (*inst_it).second->threadNumber; 835 |
638 (*inst_it).second->setCanIssue(); 639 | 836 (*inst_it).second->setCanIssue(); 837 |
640 // Now schedule the instruction. | |
641 if (!(*inst_it).second->isMemRef()) { 642 addIfReady((*inst_it).second); 643 } else { | 838 if (!(*inst_it).second->isMemRef()) { 839 addIfReady((*inst_it).second); 840 } else { |
644 memDepUnit.nonSpecInstReady((*inst_it).second); | 841 memDepUnit[tid].nonSpecInstReady((*inst_it).second); |
645 } 646 | 842 } 843 |
844 (*inst_it).second = NULL; 845 |
|
647 nonSpecInsts.erase(inst_it); 648} 649 650template <class Impl> 651void | 846 nonSpecInsts.erase(inst_it); 847} 848 849template <class Impl> 850void |
851InstructionQueue<Impl>::commit(const InstSeqNum &inst, unsigned tid) 852{ 853 DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 854 tid,inst); 855 856 ListIt iq_it = instList[tid].begin(); 857 858 while (iq_it != instList[tid].end() && 859 (*iq_it)->seqNum <= inst) { 860 ++iq_it; 861 instList[tid].pop_front(); 862 } 863 864 assert(freeEntries == (numEntries - countInsts())); 865} 866 867template <class Impl> 868int |
|
652InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 653{ | 869InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 870{ |
654 DPRINTF(IQ, "IQ: Waking dependents of completed instruction.\n"); 655 //Look at the physical destination register of the DynInst 656 //and look it up on the dependency graph. Then mark as ready 657 //any instructions within the instruction queue. 658 DependencyEntry *curr; | 871 int dependents = 0; |
659 | 872 |
660 // Tell the memory dependence unit to wake any dependents on this 661 // instruction if it is a memory instruction. | 873 DPRINTF(IQ, "Waking dependents of completed instruction.\n"); |
662 | 874 |
875 assert(!completed_inst->isSquashed()); 876 877 // Tell the memory dependence unit to wake any dependents on this 878 // instruction if it is a memory instruction. Also complete the memory 879 // instruction at this point since we know it executed without issues. 880 // @todo: Might want to rename "completeMemInst" to something that 881 // indicates that it won't need to be replayed, and call this 882 // earlier. Might not be a big deal. |
|
663 if (completed_inst->isMemRef()) { | 883 if (completed_inst->isMemRef()) { |
664 memDepUnit.wakeDependents(completed_inst); | 884 memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 885 completeMemInst(completed_inst); 886 } else if (completed_inst->isMemBarrier() || 887 completed_inst->isWriteBarrier()) { 888 memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); |
665 } 666 667 for (int dest_reg_idx = 0; 668 dest_reg_idx < completed_inst->numDestRegs(); 669 dest_reg_idx++) 670 { 671 PhysRegIndex dest_reg = 672 completed_inst->renamedDestRegIdx(dest_reg_idx); 673 674 // Special case of uniq or control registers. They are not 675 // handled by the IQ and thus have no dependency graph entry. 676 // @todo Figure out a cleaner way to handle this. 677 if (dest_reg >= numPhysRegs) { 678 continue; 679 } 680 | 889 } 890 891 for (int dest_reg_idx = 0; 892 dest_reg_idx < completed_inst->numDestRegs(); 893 dest_reg_idx++) 894 { 895 PhysRegIndex dest_reg = 896 completed_inst->renamedDestRegIdx(dest_reg_idx); 897 898 // Special case of uniq or control registers. They are not 899 // handled by the IQ and thus have no dependency graph entry. 900 // @todo Figure out a cleaner way to handle this. 901 if (dest_reg >= numPhysRegs) { 902 continue; 903 } 904 |
681 DPRINTF(IQ, "IQ: Waking any dependents on register %i.\n", | 905 DPRINTF(IQ, "Waking any dependents on register %i.\n", |
682 (int) dest_reg); 683 | 906 (int) dest_reg); 907 |
684 //Maybe abstract this part into a function. 685 //Go through the dependency chain, marking the registers as ready 686 //within the waiting instructions. 687 while (dependGraph[dest_reg].next) { | 908 //Go through the dependency chain, marking the registers as 909 //ready within the waiting instructions. 910 DynInstPtr dep_inst = dependGraph.pop(dest_reg); |
688 | 911 |
689 curr = dependGraph[dest_reg].next; | 912 while (dep_inst) { 913 DPRINTF(IQ, "Waking up a dependent instruction, PC%#x.\n", 914 dep_inst->readPC()); |
690 | 915 |
691 DPRINTF(IQ, "IQ: Waking up a dependent instruction, PC%#x.\n", 692 curr->inst->readPC()); 693 | |
694 // Might want to give more information to the instruction | 916 // Might want to give more information to the instruction |
695 // so that it knows which of its source registers is ready. 696 // However that would mean that the dependency graph entries 697 // would need to hold the src_reg_idx. 698 curr->inst->markSrcRegReady(); | 917 // so that it knows which of its source registers is 918 // ready. However that would mean that the dependency 919 // graph entries would need to hold the src_reg_idx. 920 dep_inst->markSrcRegReady(); |
699 | 921 |
700 addIfReady(curr->inst); | 922 addIfReady(dep_inst); |
701 | 923 |
702 dependGraph[dest_reg].next = curr->next; | 924 dep_inst = dependGraph.pop(dest_reg); |
703 | 925 |
704 DependencyEntry::mem_alloc_counter--; 705 706 curr->inst = NULL; 707 708 delete curr; | 926 ++dependents; |
709 } 710 | 927 } 928 |
711 // Reset the head node now that all of its dependents have been woken 712 // up. 713 dependGraph[dest_reg].next = NULL; 714 dependGraph[dest_reg].inst = NULL; | 929 // Reset the head node now that all of its dependents have 930 // been woken up. 931 assert(dependGraph.empty(dest_reg)); 932 dependGraph.clearInst(dest_reg); |
715 716 // Mark the scoreboard as having that register ready. 717 regScoreboard[dest_reg] = true; 718 } | 933 934 // Mark the scoreboard as having that register ready. 935 regScoreboard[dest_reg] = true; 936 } |
937 return dependents; |
|
719} 720 721template <class Impl> 722void | 938} 939 940template <class Impl> 941void |
942InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 943{ 944 OpClass op_class = ready_inst->opClass(); 945 946 readyInsts[op_class].push(ready_inst); 947 948 // Will need to reorder the list if either a queue is not on the list, 949 // or it has an older instruction than last time. 950 if (!queueOnList[op_class]) { 951 addToOrderList(op_class); 952 } else if (readyInsts[op_class].top()->seqNum < 953 (*readyIt[op_class]).oldestInst) { 954 listOrder.erase(readyIt[op_class]); 955 addToOrderList(op_class); 956 } 957 958 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 959 "the ready list, PC %#x opclass:%i [sn:%lli].\n", 960 ready_inst->readPC(), op_class, ready_inst->seqNum); 961} 962 963template <class Impl> 964void 965InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 966{ 967 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 968} 969 970template <class Impl> 971void 972InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 973{ 974 memDepUnit[replay_inst->threadNumber].replay(replay_inst); 975} 976 977template <class Impl> 978void 979InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 980{ 981 int tid = completed_inst->threadNumber; 982 983 DPRINTF(IQ, "Completing mem instruction PC:%#x [sn:%lli]\n", 984 completed_inst->readPC(), completed_inst->seqNum); 985 986 ++freeEntries; 987 988 completed_inst->memOpDone = true; 989 990 memDepUnit[tid].completed(completed_inst); 991 992 count[tid]--; 993} 994 995template <class Impl> 996void |
|
723InstructionQueue<Impl>::violation(DynInstPtr &store, 724 DynInstPtr &faulting_load) 725{ | 997InstructionQueue<Impl>::violation(DynInstPtr &store, 998 DynInstPtr &faulting_load) 999{ |
726 memDepUnit.violation(store, faulting_load); | 1000 memDepUnit[store->threadNumber].violation(store, faulting_load); |
727} 728 729template <class Impl> 730void | 1001} 1002 1003template <class Impl> 1004void |
731InstructionQueue | 1005InstructionQueue<Impl>::squash(unsigned tid) |
732{ | 1006{ |
733 DPRINTF(IQ, "IQ: Starting to squash instructions in the IQ.\n"); | 1007 DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 1008 "the IQ.\n", tid); |
734 735 // Read instruction sequence number of last instruction out of the 736 // time buffer. | 1009 1010 // Read instruction sequence number of last instruction out of the 1011 // time buffer. |
737 squashedSeqNum = fromCommit->commitInfo.doneSeqNum; | 1012 squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; |
738 | 1013 |
739 // Setup the squash iterator to point to the tail. 740 squashIt = tail; 741 | |
742 // Call doSquash if there are insts in the IQ | 1014 // Call doSquash if there are insts in the IQ |
743 if (freeEntries != numEntries) { 744 doSquash(); | 1015 if (count[tid] > 0) { 1016 doSquash(tid); |
745 } 746 747 // Also tell the memory dependence unit to squash. | 1017 } 1018 1019 // Also tell the memory dependence unit to squash. |
748 memDepUnit.squash(squashedSeqNum); | 1020 memDepUnit[tid].squash(squashedSeqNum[tid], tid); |
749} 750 751template <class Impl> 752void | 1021} 1022 1023template <class Impl> 1024void |
753InstructionQueue | 1025InstructionQueue<Impl>::doSquash(unsigned tid) |
754{ | 1026{ |
755 // Make sure the squash iterator isn't pointing to nothing. 756 assert(squashIt != cpu->instList.end()); 757 // Make sure the squashed sequence number is valid. 758 assert(squashedSeqNum != 0); | 1027 // Start at the tail. 1028 ListIt squash_it = instList[tid].end(); 1029 --squash_it; |
759 | 1030 |
760 DPRINTF(IQ, "IQ: Squashing instructions in the IQ.\n"); | 1031 DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 1032 tid, squashedSeqNum[tid]); |
761 762 // Squash any instructions younger than the squashed sequence number 763 // given. | 1033 1034 // Squash any instructions younger than the squashed sequence number 1035 // given. |
764 while ((*squashIt)->seqNum > squashedSeqNum) { 765 DynInstPtr squashed_inst = (*squashIt); | 1036 while (squash_it != instList[tid].end() && 1037 (*squash_it)->seqNum > squashedSeqNum[tid]) { |
766 | 1038 |
1039 DynInstPtr squashed_inst = (*squash_it); 1040 |
|
767 // Only handle the instruction if it actually is in the IQ and 768 // hasn't already been squashed in the IQ. | 1041 // Only handle the instruction if it actually is in the IQ and 1042 // hasn't already been squashed in the IQ. |
769 if (!squashed_inst->isIssued() && 770 !squashed_inst->isSquashedInIQ()) { | 1043 if (squashed_inst->threadNumber != tid || 1044 squashed_inst->isSquashedInIQ()) { 1045 --squash_it; 1046 continue; 1047 } |
771 | 1048 |
1049 if (!squashed_inst->isIssued() || 1050 (squashed_inst->isMemRef() && 1051 !squashed_inst->memOpDone)) { 1052 |
|
772 // Remove the instruction from the dependency list. | 1053 // Remove the instruction from the dependency list. |
773 // Hack for now: These below don't add themselves to the 774 // dependency list, so don't try to remove them. 775 if (!squashed_inst->isNonSpeculative()/* && 776 !squashed_inst->isStore()*/ 777 ) { | 1054 if (!squashed_inst->isNonSpeculative() && 1055 !squashed_inst->isStoreConditional() && 1056 !squashed_inst->isMemBarrier() && 1057 !squashed_inst->isWriteBarrier()) { |
778 779 for (int src_reg_idx = 0; 780 src_reg_idx < squashed_inst->numSrcRegs(); 781 src_reg_idx++) 782 { 783 PhysRegIndex src_reg = 784 squashed_inst->renamedSrcRegIdx(src_reg_idx); 785 | 1058 1059 for (int src_reg_idx = 0; 1060 src_reg_idx < squashed_inst->numSrcRegs(); 1061 src_reg_idx++) 1062 { 1063 PhysRegIndex src_reg = 1064 squashed_inst->renamedSrcRegIdx(src_reg_idx); 1065 |
786 // Only remove it from the dependency graph if it was 787 // placed there in the first place. 788 // HACK: This assumes that instructions woken up from the 789 // dependency chain aren't informed that a specific src 790 // register has become ready. This may not always be true 791 // in the future. | 1066 // Only remove it from the dependency graph if it 1067 // was placed there in the first place. 1068 1069 // Instead of doing a linked list traversal, we 1070 // can just remove these squashed instructions 1071 // either at issue time, or when the register is 1072 // overwritten. The only downside to this is it 1073 // leaves more room for error. 1074 |
792 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 793 src_reg < numPhysRegs) { | 1075 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 1076 src_reg < numPhysRegs) { |
794 dependGraph[src_reg].remove(squashed_inst); | 1077 dependGraph.remove(src_reg, squashed_inst); |
795 } 796 | 1078 } 1079 |
1080 |
|
797 ++iqSquashedOperandsExamined; 798 } | 1081 ++iqSquashedOperandsExamined; 1082 } |
799 800 // Might want to remove producers as well. | |
801 } else { | 1083 } else { |
802 nonSpecInsts[squashed_inst->seqNum] = NULL; | 1084 NonSpecMapIt ns_inst_it = 1085 nonSpecInsts.find(squashed_inst->seqNum); 1086 assert(ns_inst_it != nonSpecInsts.end()); |
803 | 1087 |
804 nonSpecInsts.erase(squashed_inst->seqNum); | 1088 (*ns_inst_it).second = NULL; |
805 | 1089 |
1090 nonSpecInsts.erase(ns_inst_it); 1091 |
|
806 ++iqSquashedNonSpecRemoved; 807 } 808 809 // Might want to also clear out the head of the dependency graph. 810 811 // Mark it as squashed within the IQ. 812 squashed_inst->setSquashedInIQ(); 813 | 1092 ++iqSquashedNonSpecRemoved; 1093 } 1094 1095 // Might want to also clear out the head of the dependency graph. 1096 1097 // Mark it as squashed within the IQ. 1098 squashed_inst->setSquashedInIQ(); 1099 |
814// squashedInsts.push(squashed_inst); | 1100 // @todo: Remove this hack where several statuses are set so the 1101 // inst will flow through the rest of the pipeline. |
815 squashed_inst->setIssued(); 816 squashed_inst->setCanCommit(); | 1102 squashed_inst->setIssued(); 1103 squashed_inst->setCanCommit(); |
1104 squashed_inst->removeInIQ(); |
|
817 | 1105 |
1106 //Update Thread IQ Count 1107 count[squashed_inst->threadNumber]--; 1108 |
|
818 ++freeEntries; 819 | 1109 ++freeEntries; 1110 |
820 DPRINTF(IQ, "IQ: Instruction PC %#x squashed.\n", 821 squashed_inst->readPC()); | 1111 DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x " 1112 "squashed.\n", 1113 tid, squashed_inst->seqNum, squashed_inst->readPC()); |
822 } 823 | 1114 } 1115 |
824 --squashIt; | 1116 instList[tid].erase(squash_it--); |
825 ++iqSquashedInstsExamined; 826 } | 1117 ++iqSquashedInstsExamined; 1118 } |
827 828 assert(freeEntries <= numEntries); 829 830 if (freeEntries == numEntries) { 831 tail = cpu->instList.end(); 832 } 833 | |
834} 835 836template <class Impl> | 1119} 1120 1121template <class Impl> |
837void 838InstructionQueue<Impl>::stopSquash() 839{ 840 // Clear up the squash variables to ensure that squashing doesn't 841 // get called improperly. 842 squashedSeqNum = 0; 843 844 squashIt = cpu->instList.end(); 845} 846 847template <class Impl> 848void 849InstructionQueue<Impl>::DependencyEntry::insert(DynInstPtr &new_inst) 850{ 851 //Add this new, dependent instruction at the head of the dependency 852 //chain. 853 854 // First create the entry that will be added to the head of the 855 // dependency chain. 856 DependencyEntry *new_entry = new DependencyEntry; 857 new_entry->next = this->next; 858 new_entry->inst = new_inst; 859 860 // Then actually add it to the chain. 861 this->next = new_entry; 862 863 ++mem_alloc_counter; 864} 865 866template <class Impl> 867void 868InstructionQueue<Impl>::DependencyEntry::remove(DynInstPtr &inst_to_remove) 869{ 870 DependencyEntry *prev = this; 871 DependencyEntry *curr = this->next; 872 873 // Make sure curr isn't NULL. Because this instruction is being 874 // removed from a dependency list, it must have been placed there at 875 // an earlier time. The dependency chain should not be empty, 876 // unless the instruction dependent upon it is already ready. 877 if (curr == NULL) { 878 return; 879 } 880 881 // Find the instruction to remove within the dependency linked list. 882 while(curr->inst != inst_to_remove) 883 { 884 prev = curr; 885 curr = curr->next; 886 887 assert(curr != NULL); 888 } 889 890 // Now remove this instruction from the list. 891 prev->next = curr->next; 892 893 --mem_alloc_counter; 894 895 // Could push this off to the destructor of DependencyEntry 896 curr->inst = NULL; 897 898 delete curr; 899} 900 901template <class Impl> | |
902bool 903InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 904{ 905 // Loop through the instruction's source registers, adding 906 // them to the dependency list if they are not ready. 907 int8_t total_src_regs = new_inst->numSrcRegs(); 908 bool return_val = false; 909 --- 7 unchanged lines hidden (view full) --- 917 918 // Check the IQ's scoreboard to make sure the register 919 // hasn't become ready while the instruction was in flight 920 // between stages. Only if it really isn't ready should 921 // it be added to the dependency graph. 922 if (src_reg >= numPhysRegs) { 923 continue; 924 } else if (regScoreboard[src_reg] == false) { | 1122bool 1123InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 1124{ 1125 // Loop through the instruction's source registers, adding 1126 // them to the dependency list if they are not ready. 1127 int8_t total_src_regs = new_inst->numSrcRegs(); 1128 bool return_val = false; 1129 --- 7 unchanged lines hidden (view full) --- 1137 1138 // Check the IQ's scoreboard to make sure the register 1139 // hasn't become ready while the instruction was in flight 1140 // between stages. Only if it really isn't ready should 1141 // it be added to the dependency graph. 1142 if (src_reg >= numPhysRegs) { 1143 continue; 1144 } else if (regScoreboard[src_reg] == false) { |
925 DPRINTF(IQ, "IQ: Instruction PC %#x has src reg %i that " | 1145 DPRINTF(IQ, "Instruction PC %#x has src reg %i that " |
926 "is being added to the dependency chain.\n", 927 new_inst->readPC(), src_reg); 928 | 1146 "is being added to the dependency chain.\n", 1147 new_inst->readPC(), src_reg); 1148 |
929 dependGraph[src_reg].insert(new_inst); | 1149 dependGraph.insert(src_reg, new_inst); |
930 931 // Change the return value to indicate that something 932 // was added to the dependency graph. 933 return_val = true; 934 } else { | 1150 1151 // Change the return value to indicate that something 1152 // was added to the dependency graph. 1153 return_val = true; 1154 } else { |
935 DPRINTF(IQ, "IQ: Instruction PC %#x has src reg %i that " | 1155 DPRINTF(IQ, "Instruction PC %#x has src reg %i that " |
936 "became ready before it reached the IQ.\n", 937 new_inst->readPC(), src_reg); 938 // Mark a register ready within the instruction. | 1156 "became ready before it reached the IQ.\n", 1157 new_inst->readPC(), src_reg); 1158 // Mark a register ready within the instruction. |
939 new_inst->markSrcRegReady(); | 1159 new_inst->markSrcRegReady(src_reg_idx); |
940 } 941 } 942 } 943 944 return return_val; 945} 946 947template <class Impl> 948void | 1160 } 1161 } 1162 } 1163 1164 return return_val; 1165} 1166 1167template <class Impl> 1168void |
949InstructionQueue<Impl>::createDependency(DynInstPtr &new_inst) | 1169InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst) |
950{ | 1170{ |
951 //Actually nothing really needs to be marked when an 952 //instruction becomes the producer of a register's value, 953 //but for convenience a ptr to the producing instruction will 954 //be placed in the head node of the dependency links. | 1171 // Nothing really needs to be marked when an instruction becomes 1172 // the producer of a register's value, but for convenience a ptr 1173 // to the producing instruction will be placed in the head node of 1174 // the dependency links. |
955 int8_t total_dest_regs = new_inst->numDestRegs(); 956 957 for (int dest_reg_idx = 0; 958 dest_reg_idx < total_dest_regs; 959 dest_reg_idx++) 960 { 961 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 962 963 // Instructions that use the misc regs will have a reg number 964 // higher than the normal physical registers. In this case these 965 // registers are not renamed, and there is no need to track 966 // dependencies as these instructions must be executed at commit. 967 if (dest_reg >= numPhysRegs) { 968 continue; 969 } 970 | 1175 int8_t total_dest_regs = new_inst->numDestRegs(); 1176 1177 for (int dest_reg_idx = 0; 1178 dest_reg_idx < total_dest_regs; 1179 dest_reg_idx++) 1180 { 1181 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 1182 1183 // Instructions that use the misc regs will have a reg number 1184 // higher than the normal physical registers. In this case these 1185 // registers are not renamed, and there is no need to track 1186 // dependencies as these instructions must be executed at commit. 1187 if (dest_reg >= numPhysRegs) { 1188 continue; 1189 } 1190 |
971 dependGraph[dest_reg].inst = new_inst; 972 973 if (dependGraph[dest_reg].next) { 974 dumpDependGraph(); 975 panic("IQ: Dependency graph not empty!"); | 1191 if (!dependGraph.empty(dest_reg)) { 1192 dependGraph.dump(); 1193 panic("Dependency graph %i not empty!", dest_reg); |
976 } 977 | 1194 } 1195 |
1196 dependGraph.setInst(dest_reg, new_inst); 1197 |
|
978 // Mark the scoreboard to say it's not yet ready. 979 regScoreboard[dest_reg] = false; 980 } 981} 982 983template <class Impl> 984void 985InstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 986{ | 1198 // Mark the scoreboard to say it's not yet ready. 1199 regScoreboard[dest_reg] = false; 1200 } 1201} 1202 1203template <class Impl> 1204void 1205InstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 1206{ |
987 //If the instruction now has all of its source registers | 1207 // If the instruction now has all of its source registers |
988 // available, then add it to the list of ready instructions. 989 if (inst->readyToIssue()) { 990 991 //Add the instruction to the proper ready list. | 1208 // available, then add it to the list of ready instructions. 1209 if (inst->readyToIssue()) { 1210 1211 //Add the instruction to the proper ready list. |
992 if (inst->isControl()) { | 1212 if (inst->isMemRef()) { |
993 | 1213 |
994 DPRINTF(IQ, "IQ: Branch instruction is ready to issue, " 995 "putting it onto the ready list, PC %#x.\n", 996 inst->readPC()); 997 readyBranchInsts.push(inst); | 1214 DPRINTF(IQ, "Checking if memory instruction can issue.\n"); |
998 | 1215 |
999 } else if (inst->isMemRef()) { 1000 1001 DPRINTF(IQ, "IQ: Checking if memory instruction can issue.\n"); 1002 | |
1003 // Message to the mem dependence unit that this instruction has 1004 // its registers ready. | 1216 // Message to the mem dependence unit that this instruction has 1217 // its registers ready. |
1218 memDepUnit[inst->threadNumber].regsReady(inst); |
|
1005 | 1219 |
1006 memDepUnit.regsReady(inst); | 1220 return; 1221 } |
1007 | 1222 |
1008#if 0 1009 if (memDepUnit.readyToIssue(inst)) { 1010 DPRINTF(IQ, "IQ: Memory instruction is ready to issue, " 1011 "putting it onto the ready list, PC %#x.\n", 1012 inst->readPC()); 1013 readyMemInsts.push(inst); 1014 } else { 1015 // Make dependent on the store. 1016 // Will need some way to get the store instruction it should 1017 // be dependent upon; then when the store issues it can 1018 // put the instruction on the ready list. 1019 // Yet another tree? 1020 assert(0 && "Instruction has no way to actually issue"); 1021 } 1022#endif | 1223 OpClass op_class = inst->opClass(); |
1023 | 1224 |
1024 } else if (inst->isInteger()) { | 1225 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 1226 "the ready list, PC %#x opclass:%i [sn:%lli].\n", 1227 inst->readPC(), op_class, inst->seqNum); |
1025 | 1228 |
1026 DPRINTF(IQ, "IQ: Integer instruction is ready to issue, " 1027 "putting it onto the ready list, PC %#x.\n", 1028 inst->readPC()); 1029 readyIntInsts.push(inst); | 1229 readyInsts[op_class].push(inst); |
1030 | 1230 |
1031 } else if (inst->isFloating()) { 1032 1033 DPRINTF(IQ, "IQ: Floating instruction is ready to issue, " 1034 "putting it onto the ready list, PC %#x.\n", 1035 inst->readPC()); 1036 readyFloatInsts.push(inst); 1037 1038 } else { 1039 DPRINTF(IQ, "IQ: Miscellaneous instruction is ready to issue, " 1040 "putting it onto the ready list, PC %#x..\n", 1041 inst->readPC()); 1042 1043 readyMiscInsts.push(inst); | 1231 // Will need to reorder the list if either a queue is not on the list, 1232 // or it has an older instruction than last time. 1233 if (!queueOnList[op_class]) { 1234 addToOrderList(op_class); 1235 } else if (readyInsts[op_class].top()->seqNum < 1236 (*readyIt[op_class]).oldestInst) { 1237 listOrder.erase(readyIt[op_class]); 1238 addToOrderList(op_class); |
1044 } 1045 } 1046} 1047 | 1239 } 1240 } 1241} 1242 |
1048/* 1049 * Caution, this function must not be called prior to tail being updated at 1050 * least once, otherwise it will fail the assertion. This is because 1051 * instList.begin() actually changes upon the insertion of an element into the 1052 * list when the list is empty. 1053 */ | |
1054template <class Impl> 1055int 1056InstructionQueue<Impl>::countInsts() 1057{ | 1243template <class Impl> 1244int 1245InstructionQueue<Impl>::countInsts() 1246{ |
1058 ListIt count_it = cpu->instList.begin(); | 1247 //ksewell:This works but definitely could use a cleaner write 1248 //with a more intuitive way of counting. Right now it's 1249 //just brute force .... 1250 1251#if 0 |
1059 int total_insts = 0; 1060 | 1252 int total_insts = 0; 1253 |
1061 if (tail == cpu->instList.end()) 1062 return 0; | 1254 for (int i = 0; i < numThreads; ++i) { 1255 ListIt count_it = instList[i].begin(); |
1063 | 1256 |
1064 while (count_it != tail) { 1065 if (!(*count_it)->isIssued()) { 1066 ++total_insts; 1067 } | 1257 while (count_it != instList[i].end()) { 1258 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 1259 if (!(*count_it)->isIssued()) { 1260 ++total_insts; 1261 } else if ((*count_it)->isMemRef() && 1262 !(*count_it)->memOpDone) { 1263 // Loads that have not been marked as executed still count 1264 // towards the total instructions. 1265 ++total_insts; 1266 } 1267 } |
1068 | 1268 |
1069 ++count_it; 1070 1071 assert(count_it != cpu->instList.end()); | 1269 ++count_it; 1270 } |
1072 } 1073 | 1271 } 1272 |
1074 // Need to count the tail iterator as well. 1075 if (count_it != cpu->instList.end() && 1076 (*count_it) && 1077 !(*count_it)->isIssued()) { 1078 ++total_insts; 1079 } 1080 | |
1081 return total_insts; | 1273 return total_insts; |
1274#else 1275 return numEntries - freeEntries; 1276#endif |
|
1082} 1083 1084template <class Impl> 1085void | 1277} 1278 1279template <class Impl> 1280void |
1086InstructionQueue<Impl>::dumpDependGraph() | 1281InstructionQueue<Impl>::dumpLists() |
1087{ | 1282{ |
1088 DependencyEntry *curr; | 1283 for (int i = 0; i < Num_OpClasses; ++i) { 1284 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); |
1089 | 1285 |
1090 for (int i = 0; i < numPhysRegs; ++i) 1091 { 1092 curr = &dependGraph[i]; | 1286 cprintf("\n"); 1287 } |
1093 | 1288 |
1094 if (curr->inst) { 1095 cprintf("dependGraph[%i]: producer: %#x consumer: ", i, 1096 curr->inst->readPC()); 1097 } else { 1098 cprintf("dependGraph[%i]: No producer. consumer: ", i); 1099 } | 1289 cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); |
1100 | 1290 |
1101 while (curr->next != NULL) { 1102 curr = curr->next; | 1291 NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 1292 NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); |
1103 | 1293 |
1104 cprintf("%#x ", curr->inst->readPC()); 1105 } | 1294 cprintf("Non speculative list: "); |
1106 | 1295 |
1107 cprintf("\n"); | 1296 while (non_spec_it != non_spec_end_it) { 1297 cprintf("%#x [sn:%lli]", (*non_spec_it).second->readPC(), 1298 (*non_spec_it).second->seqNum); 1299 ++non_spec_it; |
1108 } | 1300 } |
1109} | |
1110 | 1301 |
1111template <class Impl> 1112void 1113InstructionQueue<Impl>::dumpLists() 1114{ 1115 cprintf("Ready integer list size: %i\n", readyIntInsts.size()); | 1302 cprintf("\n"); |
1116 | 1303 |
1117 cprintf("Ready float list size: %i\n", readyFloatInsts.size()); | 1304 ListOrderIt list_order_it = listOrder.begin(); 1305 ListOrderIt list_order_end_it = listOrder.end(); 1306 int i = 1; |
1118 | 1307 |
1119 cprintf("Ready branch list size: %i\n", readyBranchInsts.size()); | 1308 cprintf("List order: "); |
1120 | 1309 |
1121 cprintf("Ready misc list size: %i\n", readyMiscInsts.size()); | 1310 while (list_order_it != list_order_end_it) { 1311 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 1312 (*list_order_it).oldestInst); |
1122 | 1313 |
1123 cprintf("Squashed list size: %i\n", squashedInsts.size()); | 1314 ++list_order_it; 1315 ++i; 1316 } |
1124 | 1317 |
1125 cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); | 1318 cprintf("\n"); 1319} |
1126 | 1320 |
1127 non_spec_it_t non_spec_it = nonSpecInsts.begin(); | |
1128 | 1321 |
1129 cprintf("Non speculative list: "); | 1322template <class Impl> 1323void 1324InstructionQueue<Impl>::dumpInsts() 1325{ 1326 for (int i = 0; i < numThreads; ++i) { 1327 int num = 0; 1328 int valid_num = 0; 1329 ListIt inst_list_it = instList[i].begin(); |
1130 | 1330 |
1131 while (non_spec_it != nonSpecInsts.end()) { 1132 cprintf("%#x ", (*non_spec_it).second->readPC()); 1133 ++non_spec_it; 1134 } | 1331 while (inst_list_it != instList[i].end()) 1332 { 1333 cprintf("Instruction:%i\n", 1334 num); 1335 if (!(*inst_list_it)->isSquashed()) { 1336 if (!(*inst_list_it)->isIssued()) { 1337 ++valid_num; 1338 cprintf("Count:%i\n", valid_num); 1339 } else if ((*inst_list_it)->isMemRef() && 1340 !(*inst_list_it)->memOpDone) { 1341 // Loads that have not been marked as executed 1342 // still count towards the total instructions. 1343 ++valid_num; 1344 cprintf("Count:%i\n", valid_num); 1345 } 1346 } |
1135 | 1347 |
1136 cprintf("\n"); | 1348 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n" 1349 "Issued:%i\nSquashed:%i\n", 1350 (*inst_list_it)->readPC(), 1351 (*inst_list_it)->seqNum, 1352 (*inst_list_it)->threadNumber, 1353 (*inst_list_it)->isIssued(), 1354 (*inst_list_it)->isSquashed()); |
1137 | 1355 |
1356 if ((*inst_list_it)->isMemRef()) { 1357 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 1358 } 1359 1360 cprintf("\n"); 1361 1362 inst_list_it++; 1363 ++num; 1364 } 1365 } |
|
1138} | 1366} |