inst_queue_impl.hh (12105:742d80361989) inst_queue_impl.hh (12106:7784fac1b159)
1/*
2 * Copyright (c) 2011-2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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981 {
982 PhysRegIdPtr dest_reg =
983 completed_inst->renamedDestRegIdx(dest_reg_idx);
984
985 // Special case of uniq or control registers. They are not
986 // handled by the IQ and thus have no dependency graph entry.
987 if (dest_reg->isFixedMapping()) {
988 DPRINTF(IQ, "Reg %d [%s] is part of a fix mapping, skipping\n",
1/*
2 * Copyright (c) 2011-2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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981 {
982 PhysRegIdPtr dest_reg =
983 completed_inst->renamedDestRegIdx(dest_reg_idx);
984
985 // Special case of uniq or control registers. They are not
986 // handled by the IQ and thus have no dependency graph entry.
987 if (dest_reg->isFixedMapping()) {
988 DPRINTF(IQ, "Reg %d [%s] is part of a fix mapping, skipping\n",
989 dest_reg->regIdx, RegClassStrings[dest_reg->regClass]);
989 dest_reg->index(), dest_reg->className());
990 continue;
991 }
992
993 DPRINTF(IQ, "Waking any dependents on register %i (%s).\n",
990 continue;
991 }
992
993 DPRINTF(IQ, "Waking any dependents on register %i (%s).\n",
994 dest_reg->regIdx,
995 RegClassStrings[dest_reg->regClass]);
994 dest_reg->index(),
995 dest_reg->className());
996
997 //Go through the dependency chain, marking the registers as
998 //ready within the waiting instructions.
996
997 //Go through the dependency chain, marking the registers as
998 //ready within the waiting instructions.
999 DynInstPtr dep_inst = dependGraph.pop(dest_reg->flatIdx);
999 DynInstPtr dep_inst = dependGraph.pop(dest_reg->flatIndex());
1000
1001 while (dep_inst) {
1002 DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] "
1003 "PC %s.\n", dep_inst->seqNum, dep_inst->pcState());
1004
1005 // Might want to give more information to the instruction
1006 // so that it knows which of its source registers is
1007 // ready. However that would mean that the dependency
1008 // graph entries would need to hold the src_reg_idx.
1009 dep_inst->markSrcRegReady();
1010
1011 addIfReady(dep_inst);
1012
1000
1001 while (dep_inst) {
1002 DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] "
1003 "PC %s.\n", dep_inst->seqNum, dep_inst->pcState());
1004
1005 // Might want to give more information to the instruction
1006 // so that it knows which of its source registers is
1007 // ready. However that would mean that the dependency
1008 // graph entries would need to hold the src_reg_idx.
1009 dep_inst->markSrcRegReady();
1010
1011 addIfReady(dep_inst);
1012
1013 dep_inst = dependGraph.pop(dest_reg->flatIdx);
1013 dep_inst = dependGraph.pop(dest_reg->flatIndex());
1014
1015 ++dependents;
1016 }
1017
1018 // Reset the head node now that all of its dependents have
1019 // been woken up.
1014
1015 ++dependents;
1016 }
1017
1018 // Reset the head node now that all of its dependents have
1019 // been woken up.
1020 assert(dependGraph.empty(dest_reg->flatIdx));
1021 dependGraph.clearInst(dest_reg->flatIdx);
1020 assert(dependGraph.empty(dest_reg->flatIndex()));
1021 dependGraph.clearInst(dest_reg->flatIndex());
1022
1023 // Mark the scoreboard as having that register ready.
1022
1023 // Mark the scoreboard as having that register ready.
1024 regScoreboard[dest_reg->flatIdx] = true;
1024 regScoreboard[dest_reg->flatIndex()] = true;
1025 }
1026 return dependents;
1027}
1028
1029template <class Impl>
1030void
1031InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst)
1032{

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1228 // Instead of doing a linked list traversal, we
1229 // can just remove these squashed instructions
1230 // either at issue time, or when the register is
1231 // overwritten. The only downside to this is it
1232 // leaves more room for error.
1233
1234 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) &&
1235 !src_reg->isFixedMapping()) {
1025 }
1026 return dependents;
1027}
1028
1029template <class Impl>
1030void
1031InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst)
1032{

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1228 // Instead of doing a linked list traversal, we
1229 // can just remove these squashed instructions
1230 // either at issue time, or when the register is
1231 // overwritten. The only downside to this is it
1232 // leaves more room for error.
1233
1234 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) &&
1235 !src_reg->isFixedMapping()) {
1236 dependGraph.remove(src_reg->flatIdx, squashed_inst);
1236 dependGraph.remove(src_reg->flatIndex(),
1237 squashed_inst);
1237 }
1238
1239
1240 ++iqSquashedOperandsExamined;
1241 }
1242 } else if (!squashed_inst->isStoreConditional() ||
1243 !squashed_inst->isCompleted()) {
1244 NonSpecMapIt ns_inst_it =

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1303 PhysRegIdPtr src_reg = new_inst->renamedSrcRegIdx(src_reg_idx);
1304
1305 // Check the IQ's scoreboard to make sure the register
1306 // hasn't become ready while the instruction was in flight
1307 // between stages. Only if it really isn't ready should
1308 // it be added to the dependency graph.
1309 if (src_reg->isFixedMapping()) {
1310 continue;
1238 }
1239
1240
1241 ++iqSquashedOperandsExamined;
1242 }
1243 } else if (!squashed_inst->isStoreConditional() ||
1244 !squashed_inst->isCompleted()) {
1245 NonSpecMapIt ns_inst_it =

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1304 PhysRegIdPtr src_reg = new_inst->renamedSrcRegIdx(src_reg_idx);
1305
1306 // Check the IQ's scoreboard to make sure the register
1307 // hasn't become ready while the instruction was in flight
1308 // between stages. Only if it really isn't ready should
1309 // it be added to the dependency graph.
1310 if (src_reg->isFixedMapping()) {
1311 continue;
1311 } else if (!regScoreboard[src_reg->flatIdx]) {
1312 } else if (!regScoreboard[src_reg->flatIndex()]) {
1312 DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that "
1313 "is being added to the dependency chain.\n",
1313 DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that "
1314 "is being added to the dependency chain.\n",
1314 new_inst->pcState(), src_reg->regIdx,
1315 RegClassStrings[src_reg->regClass]);
1315 new_inst->pcState(), src_reg->index(),
1316 src_reg->className());
1316
1317
1317 dependGraph.insert(src_reg->flatIdx, new_inst);
1318 dependGraph.insert(src_reg->flatIndex(), new_inst);
1318
1319 // Change the return value to indicate that something
1320 // was added to the dependency graph.
1321 return_val = true;
1322 } else {
1323 DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that "
1324 "became ready before it reached the IQ.\n",
1319
1320 // Change the return value to indicate that something
1321 // was added to the dependency graph.
1322 return_val = true;
1323 } else {
1324 DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that "
1325 "became ready before it reached the IQ.\n",
1325 new_inst->pcState(), src_reg->regIdx,
1326 RegClassStrings[src_reg->regClass]);
1326 new_inst->pcState(), src_reg->index(),
1327 src_reg->className());
1327 // Mark a register ready within the instruction.
1328 new_inst->markSrcRegReady(src_reg_idx);
1329 }
1330 }
1331 }
1332
1333 return return_val;
1334}

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1350 PhysRegIdPtr dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx);
1351
1352 // Some registers have fixed mapping, and there is no need to track
1353 // dependencies as these instructions must be executed at commit.
1354 if (dest_reg->isFixedMapping()) {
1355 continue;
1356 }
1357
1328 // Mark a register ready within the instruction.
1329 new_inst->markSrcRegReady(src_reg_idx);
1330 }
1331 }
1332 }
1333
1334 return return_val;
1335}

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1351 PhysRegIdPtr dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx);
1352
1353 // Some registers have fixed mapping, and there is no need to track
1354 // dependencies as these instructions must be executed at commit.
1355 if (dest_reg->isFixedMapping()) {
1356 continue;
1357 }
1358
1358 if (!dependGraph.empty(dest_reg->flatIdx)) {
1359 if (!dependGraph.empty(dest_reg->flatIndex())) {
1359 dependGraph.dump();
1360 panic("Dependency graph %i (%s) (flat: %i) not empty!",
1360 dependGraph.dump();
1361 panic("Dependency graph %i (%s) (flat: %i) not empty!",
1361 dest_reg->regIdx, RegClassStrings[dest_reg->regClass],
1362 dest_reg->flatIdx);
1362 dest_reg->index(), dest_reg->className(),
1363 dest_reg->flatIndex());
1363 }
1364
1364 }
1365
1365 dependGraph.setInst(dest_reg->flatIdx, new_inst);
1366 dependGraph.setInst(dest_reg->flatIndex(), new_inst);
1366
1367 // Mark the scoreboard to say it's not yet ready.
1367
1368 // Mark the scoreboard to say it's not yet ready.
1368 regScoreboard[dest_reg->flatIdx] = false;
1369 regScoreboard[dest_reg->flatIndex()] = false;
1369 }
1370}
1371
1372template <class Impl>
1373void
1374InstructionQueue<Impl>::addIfReady(DynInstPtr &inst)
1375{
1376 // If the instruction now has all of its source registers

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1371}
1372
1373template <class Impl>
1374void
1375InstructionQueue<Impl>::addIfReady(DynInstPtr &inst)
1376{
1377 // If the instruction now has all of its source registers

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