1/* 2 * Copyright (c) 2011-2013 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 * Korey Sewell 43 */ 44 45#ifndef __CPU_O3_INST_QUEUE_IMPL_HH__ 46#define __CPU_O3_INST_QUEUE_IMPL_HH__ 47 48#include <limits> 49#include <vector> 50 51#include "cpu/o3/fu_pool.hh" 52#include "cpu/o3/inst_queue.hh" 53#include "debug/IQ.hh" 54#include "enums/OpClass.hh" 55#include "params/DerivO3CPU.hh" 56#include "sim/core.hh" 57 58// clang complains about std::set being overloaded with Packet::set if 59// we open up the entire namespace std 60using std::list; 61 62template <class Impl> 63InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 64 int fu_idx, InstructionQueue<Impl> *iq_ptr) 65 : Event(Stat_Event_Pri, AutoDelete), 66 inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 67{ 68} 69 70template <class Impl> 71void 72InstructionQueue<Impl>::FUCompletion::process() 73{ 74 iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 75 inst = NULL; 76} 77 78 79template <class Impl> 80const char * 81InstructionQueue<Impl>::FUCompletion::description() const 82{ 83 return "Functional unit completion"; 84} 85 86template <class Impl> 87InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 88 DerivO3CPUParams *params) 89 : cpu(cpu_ptr), 90 iewStage(iew_ptr), 91 fuPool(params->fuPool), 92 numEntries(params->numIQEntries), 93 totalWidth(params->issueWidth), 94 commitToIEWDelay(params->commitToIEWDelay) 95{ 96 assert(fuPool); 97 98 numThreads = params->numThreads; 99 100 // Set the number of total physical registers 101 numPhysRegs = params->numPhysIntRegs + params->numPhysFloatRegs + 102 params->numPhysCCRegs; 103 104 //Create an entry for each physical register within the 105 //dependency graph. 106 dependGraph.resize(numPhysRegs); 107 108 // Resize the register scoreboard. 109 regScoreboard.resize(numPhysRegs); 110 111 //Initialize Mem Dependence Units 112 for (ThreadID tid = 0; tid < numThreads; tid++) { 113 memDepUnit[tid].init(params, tid); 114 memDepUnit[tid].setIQ(this); 115 } 116 117 resetState(); 118 119 std::string policy = params->smtIQPolicy; 120 121 //Convert string to lowercase 122 std::transform(policy.begin(), policy.end(), policy.begin(), 123 (int(*)(int)) tolower); 124 125 //Figure out resource sharing policy 126 if (policy == "dynamic") { 127 iqPolicy = Dynamic; 128 129 //Set Max Entries to Total ROB Capacity 130 for (ThreadID tid = 0; tid < numThreads; tid++) { 131 maxEntries[tid] = numEntries; 132 } 133 134 } else if (policy == "partitioned") { 135 iqPolicy = Partitioned; 136 137 //@todo:make work if part_amt doesnt divide evenly. 138 int part_amt = numEntries / numThreads; 139 140 //Divide ROB up evenly 141 for (ThreadID tid = 0; tid < numThreads; tid++) { 142 maxEntries[tid] = part_amt; 143 } 144 145 DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 146 "%i entries per thread.\n",part_amt); 147 } else if (policy == "threshold") { 148 iqPolicy = Threshold; 149 150 double threshold = (double)params->smtIQThreshold / 100; 151 152 int thresholdIQ = (int)((double)threshold * numEntries); 153 154 //Divide up by threshold amount 155 for (ThreadID tid = 0; tid < numThreads; tid++) { 156 maxEntries[tid] = thresholdIQ; 157 } 158 159 DPRINTF(IQ, "IQ sharing policy set to Threshold:" 160 "%i entries per thread.\n",thresholdIQ); 161 } else { 162 assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 163 "Partitioned, Threshold}"); 164 } 165} 166 167template <class Impl> 168InstructionQueue<Impl>::~InstructionQueue() 169{ 170 dependGraph.reset(); 171#ifdef DEBUG 172 cprintf("Nodes traversed: %i, removed: %i\n", 173 dependGraph.nodesTraversed, dependGraph.nodesRemoved); 174#endif 175} 176 177template <class Impl> 178std::string 179InstructionQueue<Impl>::name() const 180{ 181 return cpu->name() + ".iq"; 182} 183 184template <class Impl> 185void 186InstructionQueue<Impl>::regStats() 187{ 188 using namespace Stats; 189 iqInstsAdded 190 .name(name() + ".iqInstsAdded") 191 .desc("Number of instructions added to the IQ (excludes non-spec)") 192 .prereq(iqInstsAdded); 193 194 iqNonSpecInstsAdded 195 .name(name() + ".iqNonSpecInstsAdded") 196 .desc("Number of non-speculative instructions added to the IQ") 197 .prereq(iqNonSpecInstsAdded); 198 199 iqInstsIssued 200 .name(name() + ".iqInstsIssued") 201 .desc("Number of instructions issued") 202 .prereq(iqInstsIssued); 203 204 iqIntInstsIssued 205 .name(name() + ".iqIntInstsIssued") 206 .desc("Number of integer instructions issued") 207 .prereq(iqIntInstsIssued); 208 209 iqFloatInstsIssued 210 .name(name() + ".iqFloatInstsIssued") 211 .desc("Number of float instructions issued") 212 .prereq(iqFloatInstsIssued); 213 214 iqBranchInstsIssued 215 .name(name() + ".iqBranchInstsIssued") 216 .desc("Number of branch instructions issued") 217 .prereq(iqBranchInstsIssued); 218 219 iqMemInstsIssued 220 .name(name() + ".iqMemInstsIssued") 221 .desc("Number of memory instructions issued") 222 .prereq(iqMemInstsIssued); 223 224 iqMiscInstsIssued 225 .name(name() + ".iqMiscInstsIssued") 226 .desc("Number of miscellaneous instructions issued") 227 .prereq(iqMiscInstsIssued); 228 229 iqSquashedInstsIssued 230 .name(name() + ".iqSquashedInstsIssued") 231 .desc("Number of squashed instructions issued") 232 .prereq(iqSquashedInstsIssued); 233 234 iqSquashedInstsExamined 235 .name(name() + ".iqSquashedInstsExamined") 236 .desc("Number of squashed instructions iterated over during squash;" 237 " mainly for profiling") 238 .prereq(iqSquashedInstsExamined); 239 240 iqSquashedOperandsExamined 241 .name(name() + ".iqSquashedOperandsExamined") 242 .desc("Number of squashed operands that are examined and possibly " 243 "removed from graph") 244 .prereq(iqSquashedOperandsExamined); 245 246 iqSquashedNonSpecRemoved 247 .name(name() + ".iqSquashedNonSpecRemoved") 248 .desc("Number of squashed non-spec instructions that were removed") 249 .prereq(iqSquashedNonSpecRemoved); 250/* 251 queueResDist 252 .init(Num_OpClasses, 0, 99, 2) 253 .name(name() + ".IQ:residence:") 254 .desc("cycles from dispatch to issue") 255 .flags(total | pdf | cdf ) 256 ; 257 for (int i = 0; i < Num_OpClasses; ++i) { 258 queueResDist.subname(i, opClassStrings[i]); 259 } 260*/ 261 numIssuedDist 262 .init(0,totalWidth,1) 263 .name(name() + ".issued_per_cycle") 264 .desc("Number of insts issued each cycle") 265 .flags(pdf) 266 ; 267/* 268 dist_unissued 269 .init(Num_OpClasses+2) 270 .name(name() + ".unissued_cause") 271 .desc("Reason ready instruction not issued") 272 .flags(pdf | dist) 273 ; 274 for (int i=0; i < (Num_OpClasses + 2); ++i) { 275 dist_unissued.subname(i, unissued_names[i]); 276 } 277*/ 278 statIssuedInstType 279 .init(numThreads,Enums::Num_OpClass) 280 .name(name() + ".FU_type") 281 .desc("Type of FU issued") 282 .flags(total | pdf | dist) 283 ; 284 statIssuedInstType.ysubnames(Enums::OpClassStrings); 285 286 // 287 // How long did instructions for a particular FU type wait prior to issue 288 // 289/* 290 issueDelayDist 291 .init(Num_OpClasses,0,99,2) 292 .name(name() + ".") 293 .desc("cycles from operands ready to issue") 294 .flags(pdf | cdf) 295 ; 296 297 for (int i=0; i<Num_OpClasses; ++i) { 298 std::stringstream subname; 299 subname << opClassStrings[i] << "_delay"; 300 issueDelayDist.subname(i, subname.str()); 301 } 302*/ 303 issueRate 304 .name(name() + ".rate") 305 .desc("Inst issue rate") 306 .flags(total) 307 ; 308 issueRate = iqInstsIssued / cpu->numCycles; 309 310 statFuBusy 311 .init(Num_OpClasses) 312 .name(name() + ".fu_full") 313 .desc("attempts to use FU when none available") 314 .flags(pdf | dist) 315 ; 316 for (int i=0; i < Num_OpClasses; ++i) { 317 statFuBusy.subname(i, Enums::OpClassStrings[i]); 318 } 319 320 fuBusy 321 .init(numThreads) 322 .name(name() + ".fu_busy_cnt") 323 .desc("FU busy when requested") 324 .flags(total) 325 ; 326 327 fuBusyRate 328 .name(name() + ".fu_busy_rate") 329 .desc("FU busy rate (busy events/executed inst)") 330 .flags(total) 331 ; 332 fuBusyRate = fuBusy / iqInstsIssued; 333 334 for (ThreadID tid = 0; tid < numThreads; tid++) { 335 // Tell mem dependence unit to reg stats as well. 336 memDepUnit[tid].regStats(); 337 } 338 339 intInstQueueReads 340 .name(name() + ".int_inst_queue_reads") 341 .desc("Number of integer instruction queue reads") 342 .flags(total); 343 344 intInstQueueWrites 345 .name(name() + ".int_inst_queue_writes") 346 .desc("Number of integer instruction queue writes") 347 .flags(total); 348 349 intInstQueueWakeupAccesses 350 .name(name() + ".int_inst_queue_wakeup_accesses") 351 .desc("Number of integer instruction queue wakeup accesses") 352 .flags(total); 353 354 fpInstQueueReads 355 .name(name() + ".fp_inst_queue_reads") 356 .desc("Number of floating instruction queue reads") 357 .flags(total); 358 359 fpInstQueueWrites 360 .name(name() + ".fp_inst_queue_writes") 361 .desc("Number of floating instruction queue writes") 362 .flags(total); 363 364 fpInstQueueWakeupQccesses 365 .name(name() + ".fp_inst_queue_wakeup_accesses") 366 .desc("Number of floating instruction queue wakeup accesses") 367 .flags(total); 368 369 intAluAccesses 370 .name(name() + ".int_alu_accesses") 371 .desc("Number of integer alu accesses") 372 .flags(total); 373 374 fpAluAccesses 375 .name(name() + ".fp_alu_accesses") 376 .desc("Number of floating point alu accesses") 377 .flags(total); 378 379} 380 381template <class Impl> 382void 383InstructionQueue<Impl>::resetState() 384{ 385 //Initialize thread IQ counts 386 for (ThreadID tid = 0; tid <numThreads; tid++) { 387 count[tid] = 0; 388 instList[tid].clear(); 389 } 390 391 // Initialize the number of free IQ entries. 392 freeEntries = numEntries; 393 394 // Note that in actuality, the registers corresponding to the logical 395 // registers start off as ready. However this doesn't matter for the 396 // IQ as the instruction should have been correctly told if those 397 // registers are ready in rename. Thus it can all be initialized as 398 // unready. 399 for (int i = 0; i < numPhysRegs; ++i) { 400 regScoreboard[i] = false; 401 } 402 403 for (ThreadID tid = 0; tid < numThreads; ++tid) { 404 squashedSeqNum[tid] = 0; 405 } 406 407 for (int i = 0; i < Num_OpClasses; ++i) { 408 while (!readyInsts[i].empty()) 409 readyInsts[i].pop(); 410 queueOnList[i] = false; 411 readyIt[i] = listOrder.end(); 412 } 413 nonSpecInsts.clear(); 414 listOrder.clear(); 415 deferredMemInsts.clear(); 416} 417 418template <class Impl> 419void 420InstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 421{ 422 activeThreads = at_ptr; 423} 424 425template <class Impl> 426void 427InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 428{ 429 issueToExecuteQueue = i2e_ptr; 430} 431 432template <class Impl> 433void 434InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 435{ 436 timeBuffer = tb_ptr; 437 438 fromCommit = timeBuffer->getWire(-commitToIEWDelay); 439} 440 441template <class Impl> 442void 443InstructionQueue<Impl>::drainSanityCheck() const 444{ 445 assert(dependGraph.empty()); 446 assert(instsToExecute.empty()); 447 for (ThreadID tid = 0; tid < numThreads; ++tid) 448 memDepUnit[tid].drainSanityCheck(); 449} 450 451template <class Impl> 452void 453InstructionQueue<Impl>::takeOverFrom() 454{ 455 resetState(); 456} 457 458template <class Impl> 459int 460InstructionQueue<Impl>::entryAmount(ThreadID num_threads) 461{ 462 if (iqPolicy == Partitioned) { 463 return numEntries / num_threads; 464 } else { 465 return 0; 466 } 467} 468 469 470template <class Impl> 471void 472InstructionQueue<Impl>::resetEntries() 473{ 474 if (iqPolicy != Dynamic || numThreads > 1) { 475 int active_threads = activeThreads->size(); 476 477 list<ThreadID>::iterator threads = activeThreads->begin(); 478 list<ThreadID>::iterator end = activeThreads->end(); 479 480 while (threads != end) { 481 ThreadID tid = *threads++; 482 483 if (iqPolicy == Partitioned) { 484 maxEntries[tid] = numEntries / active_threads; 485 } else if(iqPolicy == Threshold && active_threads == 1) { 486 maxEntries[tid] = numEntries; 487 } 488 } 489 } 490} 491 492template <class Impl> 493unsigned 494InstructionQueue<Impl>::numFreeEntries() 495{ 496 return freeEntries; 497} 498 499template <class Impl> 500unsigned 501InstructionQueue<Impl>::numFreeEntries(ThreadID tid) 502{ 503 return maxEntries[tid] - count[tid]; 504} 505 506// Might want to do something more complex if it knows how many instructions 507// will be issued this cycle. 508template <class Impl> 509bool 510InstructionQueue<Impl>::isFull() 511{ 512 if (freeEntries == 0) { 513 return(true); 514 } else { 515 return(false); 516 } 517} 518 519template <class Impl> 520bool 521InstructionQueue<Impl>::isFull(ThreadID tid) 522{ 523 if (numFreeEntries(tid) == 0) { 524 return(true); 525 } else { 526 return(false); 527 } 528} 529 530template <class Impl> 531bool 532InstructionQueue<Impl>::hasReadyInsts() 533{ 534 if (!listOrder.empty()) { 535 return true; 536 } 537 538 for (int i = 0; i < Num_OpClasses; ++i) { 539 if (!readyInsts[i].empty()) { 540 return true; 541 } 542 } 543 544 return false; 545} 546 547template <class Impl> 548void 549InstructionQueue<Impl>::insert(DynInstPtr &new_inst) 550{ 551 new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 552 // Make sure the instruction is valid 553 assert(new_inst); 554 555 DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n", 556 new_inst->seqNum, new_inst->pcState()); 557 558 assert(freeEntries != 0); 559 560 instList[new_inst->threadNumber].push_back(new_inst); 561 562 --freeEntries; 563 564 new_inst->setInIQ(); 565 566 // Look through its source registers (physical regs), and mark any 567 // dependencies. 568 addToDependents(new_inst); 569 570 // Have this instruction set itself as the producer of its destination 571 // register(s). 572 addToProducers(new_inst); 573 574 if (new_inst->isMemRef()) { 575 memDepUnit[new_inst->threadNumber].insert(new_inst); 576 } else { 577 addIfReady(new_inst); 578 } 579 580 ++iqInstsAdded; 581 582 count[new_inst->threadNumber]++; 583 584 assert(freeEntries == (numEntries - countInsts())); 585} 586 587template <class Impl> 588void 589InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst) 590{ 591 // @todo: Clean up this code; can do it by setting inst as unable 592 // to issue, then calling normal insert on the inst. 593 new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 594 595 assert(new_inst); 596 597 nonSpecInsts[new_inst->seqNum] = new_inst; 598 599 DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s " 600 "to the IQ.\n", 601 new_inst->seqNum, new_inst->pcState()); 602 603 assert(freeEntries != 0); 604 605 instList[new_inst->threadNumber].push_back(new_inst); 606 607 --freeEntries; 608 609 new_inst->setInIQ(); 610 611 // Have this instruction set itself as the producer of its destination 612 // register(s). 613 addToProducers(new_inst); 614 615 // If it's a memory instruction, add it to the memory dependency 616 // unit. 617 if (new_inst->isMemRef()) { 618 memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 619 } 620 621 ++iqNonSpecInstsAdded; 622 623 count[new_inst->threadNumber]++; 624 625 assert(freeEntries == (numEntries - countInsts())); 626} 627 628template <class Impl> 629void 630InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst) 631{ 632 memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 633 634 insertNonSpec(barr_inst); 635} 636 637template <class Impl> 638typename Impl::DynInstPtr 639InstructionQueue<Impl>::getInstToExecute() 640{ 641 assert(!instsToExecute.empty()); 642 DynInstPtr inst = instsToExecute.front(); 643 instsToExecute.pop_front(); 644 if (inst->isFloating()){ 645 fpInstQueueReads++; 646 } else { 647 intInstQueueReads++; 648 } 649 return inst; 650} 651 652template <class Impl> 653void 654InstructionQueue<Impl>::addToOrderList(OpClass op_class) 655{ 656 assert(!readyInsts[op_class].empty()); 657 658 ListOrderEntry queue_entry; 659 660 queue_entry.queueType = op_class; 661 662 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 663 664 ListOrderIt list_it = listOrder.begin(); 665 ListOrderIt list_end_it = listOrder.end(); 666 667 while (list_it != list_end_it) { 668 if ((*list_it).oldestInst > queue_entry.oldestInst) { 669 break; 670 } 671 672 list_it++; 673 } 674 675 readyIt[op_class] = listOrder.insert(list_it, queue_entry); 676 queueOnList[op_class] = true; 677} 678 679template <class Impl> 680void 681InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 682{ 683 // Get iterator of next item on the list 684 // Delete the original iterator 685 // Determine if the next item is either the end of the list or younger 686 // than the new instruction. If so, then add in a new iterator right here. 687 // If not, then move along. 688 ListOrderEntry queue_entry; 689 OpClass op_class = (*list_order_it).queueType; 690 ListOrderIt next_it = list_order_it; 691 692 ++next_it; 693 694 queue_entry.queueType = op_class; 695 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 696 697 while (next_it != listOrder.end() && 698 (*next_it).oldestInst < queue_entry.oldestInst) { 699 ++next_it; 700 } 701 702 readyIt[op_class] = listOrder.insert(next_it, queue_entry); 703} 704 705template <class Impl> 706void 707InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 708{ 709 DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 710 assert(!cpu->switchedOut()); 711 // The CPU could have been sleeping until this op completed (*extremely* 712 // long latency op). Wake it if it was. This may be overkill. 713 iewStage->wakeCPU(); 714 715 if (fu_idx > -1) 716 fuPool->freeUnitNextCycle(fu_idx); 717 718 // @todo: Ensure that these FU Completions happen at the beginning 719 // of a cycle, otherwise they could add too many instructions to 720 // the queue. 721 issueToExecuteQueue->access(-1)->size++; 722 instsToExecute.push_back(inst); 723} 724 725// @todo: Figure out a better way to remove the squashed items from the 726// lists. Checking the top item of each list to see if it's squashed 727// wastes time and forces jumps. 728template <class Impl> 729void 730InstructionQueue<Impl>::scheduleReadyInsts() 731{ 732 DPRINTF(IQ, "Attempting to schedule ready instructions from " 733 "the IQ.\n"); 734 735 IssueStruct *i2e_info = issueToExecuteQueue->access(0); 736 737 DynInstPtr deferred_mem_inst; 738 int total_deferred_mem_issued = 0; 739 while (total_deferred_mem_issued < totalWidth && 740 (deferred_mem_inst = getDeferredMemInstToExecute()) != 0) { 741 issueToExecuteQueue->access(0)->size++; 742 instsToExecute.push_back(deferred_mem_inst); 743 total_deferred_mem_issued++; 744 } 745 746 // Have iterator to head of the list 747 // While I haven't exceeded bandwidth or reached the end of the list, 748 // Try to get a FU that can do what this op needs. 749 // If successful, change the oldestInst to the new top of the list, put 750 // the queue in the proper place in the list. 751 // Increment the iterator. 752 // This will avoid trying to schedule a certain op class if there are no 753 // FUs that handle it. 754 ListOrderIt order_it = listOrder.begin(); 755 ListOrderIt order_end_it = listOrder.end(); 756 int total_issued = 0; 757 758 while (total_issued < (totalWidth - total_deferred_mem_issued) && |
759 order_it != order_end_it) { 760 OpClass op_class = (*order_it).queueType; 761 762 assert(!readyInsts[op_class].empty()); 763 764 DynInstPtr issuing_inst = readyInsts[op_class].top(); 765 766 issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++; 767 768 assert(issuing_inst->seqNum == (*order_it).oldestInst); 769 770 if (issuing_inst->isSquashed()) { 771 readyInsts[op_class].pop(); 772 773 if (!readyInsts[op_class].empty()) { 774 moveToYoungerInst(order_it); 775 } else { 776 readyIt[op_class] = listOrder.end(); 777 queueOnList[op_class] = false; 778 } 779 780 listOrder.erase(order_it++); 781 782 ++iqSquashedInstsIssued; 783 784 continue; 785 } 786 787 int idx = -2; 788 Cycles op_latency = Cycles(1); 789 ThreadID tid = issuing_inst->threadNumber; 790 791 if (op_class != No_OpClass) { 792 idx = fuPool->getUnit(op_class); 793 issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++; 794 if (idx > -1) { 795 op_latency = fuPool->getOpLatency(op_class); 796 } 797 } 798 799 // If we have an instruction that doesn't require a FU, or a 800 // valid FU, then schedule for execution. 801 if (idx == -2 || idx != -1) { 802 if (op_latency == Cycles(1)) { 803 i2e_info->size++; 804 instsToExecute.push_back(issuing_inst); 805 806 // Add the FU onto the list of FU's to be freed next 807 // cycle if we used one. 808 if (idx >= 0) 809 fuPool->freeUnitNextCycle(idx); 810 } else { 811 Cycles issue_latency = fuPool->getIssueLatency(op_class); 812 // Generate completion event for the FU 813 FUCompletion *execution = new FUCompletion(issuing_inst, 814 idx, this); 815 816 cpu->schedule(execution, 817 cpu->clockEdge(Cycles(op_latency - 1))); 818 819 // @todo: Enforce that issue_latency == 1 or op_latency 820 if (issue_latency > Cycles(1)) { 821 // If FU isn't pipelined, then it must be freed 822 // upon the execution completing. 823 execution->setFreeFU(); 824 } else { 825 // Add the FU onto the list of FU's to be freed next cycle. 826 fuPool->freeUnitNextCycle(idx); 827 } 828 } 829 830 DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " 831 "[sn:%lli]\n", 832 tid, issuing_inst->pcState(), 833 issuing_inst->seqNum); 834 835 readyInsts[op_class].pop(); 836 837 if (!readyInsts[op_class].empty()) { 838 moveToYoungerInst(order_it); 839 } else { 840 readyIt[op_class] = listOrder.end(); 841 queueOnList[op_class] = false; 842 } 843 844 issuing_inst->setIssued(); 845 ++total_issued; 846 847#if TRACING_ON 848 issuing_inst->issueTick = curTick() - issuing_inst->fetchTick; 849#endif 850 851 if (!issuing_inst->isMemRef()) { 852 // Memory instructions can not be freed from the IQ until they 853 // complete. 854 ++freeEntries; 855 count[tid]--; 856 issuing_inst->clearInIQ(); 857 } else { 858 memDepUnit[tid].issue(issuing_inst); 859 } 860 861 listOrder.erase(order_it++); 862 statIssuedInstType[tid][op_class]++; |
863 } else { 864 statFuBusy[op_class]++; 865 fuBusy[tid]++; 866 ++order_it; 867 } 868 } 869 870 numIssuedDist.sample(total_issued); 871 iqInstsIssued+= total_issued; 872 873 // If we issued any instructions, tell the CPU we had activity. 874 // @todo If the way deferred memory instructions are handeled due to 875 // translation changes then the deferredMemInsts condition should be removed 876 // from the code below. 877 if (total_issued || total_deferred_mem_issued || deferredMemInsts.size()) { 878 cpu->activityThisCycle(); 879 } else { 880 DPRINTF(IQ, "Not able to schedule any instructions.\n"); 881 } 882} 883 884template <class Impl> 885void 886InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 887{ 888 DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 889 "to execute.\n", inst); 890 891 NonSpecMapIt inst_it = nonSpecInsts.find(inst); 892 893 assert(inst_it != nonSpecInsts.end()); 894 895 ThreadID tid = (*inst_it).second->threadNumber; 896 897 (*inst_it).second->setAtCommit(); 898 899 (*inst_it).second->setCanIssue(); 900 901 if (!(*inst_it).second->isMemRef()) { 902 addIfReady((*inst_it).second); 903 } else { 904 memDepUnit[tid].nonSpecInstReady((*inst_it).second); 905 } 906 907 (*inst_it).second = NULL; 908 909 nonSpecInsts.erase(inst_it); 910} 911 912template <class Impl> 913void 914InstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 915{ 916 DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 917 tid,inst); 918 919 ListIt iq_it = instList[tid].begin(); 920 921 while (iq_it != instList[tid].end() && 922 (*iq_it)->seqNum <= inst) { 923 ++iq_it; 924 instList[tid].pop_front(); 925 } 926 927 assert(freeEntries == (numEntries - countInsts())); 928} 929 930template <class Impl> 931int 932InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 933{ 934 int dependents = 0; 935 936 // The instruction queue here takes care of both floating and int ops 937 if (completed_inst->isFloating()) { 938 fpInstQueueWakeupQccesses++; 939 } else { 940 intInstQueueWakeupAccesses++; 941 } 942 943 DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 944 945 assert(!completed_inst->isSquashed()); 946 947 // Tell the memory dependence unit to wake any dependents on this 948 // instruction if it is a memory instruction. Also complete the memory 949 // instruction at this point since we know it executed without issues. 950 // @todo: Might want to rename "completeMemInst" to something that 951 // indicates that it won't need to be replayed, and call this 952 // earlier. Might not be a big deal. 953 if (completed_inst->isMemRef()) { 954 memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 955 completeMemInst(completed_inst); 956 } else if (completed_inst->isMemBarrier() || 957 completed_inst->isWriteBarrier()) { 958 memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 959 } 960 961 for (int dest_reg_idx = 0; 962 dest_reg_idx < completed_inst->numDestRegs(); 963 dest_reg_idx++) 964 { 965 PhysRegIndex dest_reg = 966 completed_inst->renamedDestRegIdx(dest_reg_idx); 967 968 // Special case of uniq or control registers. They are not 969 // handled by the IQ and thus have no dependency graph entry. 970 // @todo Figure out a cleaner way to handle this. 971 if (dest_reg >= numPhysRegs) { 972 DPRINTF(IQ, "dest_reg :%d, numPhysRegs: %d\n", dest_reg, 973 numPhysRegs); 974 continue; 975 } 976 977 DPRINTF(IQ, "Waking any dependents on register %i.\n", 978 (int) dest_reg); 979 980 //Go through the dependency chain, marking the registers as 981 //ready within the waiting instructions. 982 DynInstPtr dep_inst = dependGraph.pop(dest_reg); 983 984 while (dep_inst) { 985 DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] " 986 "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); 987 988 // Might want to give more information to the instruction 989 // so that it knows which of its source registers is 990 // ready. However that would mean that the dependency 991 // graph entries would need to hold the src_reg_idx. 992 dep_inst->markSrcRegReady(); 993 994 addIfReady(dep_inst); 995 996 dep_inst = dependGraph.pop(dest_reg); 997 998 ++dependents; 999 } 1000 1001 // Reset the head node now that all of its dependents have 1002 // been woken up. 1003 assert(dependGraph.empty(dest_reg)); 1004 dependGraph.clearInst(dest_reg); 1005 1006 // Mark the scoreboard as having that register ready. 1007 regScoreboard[dest_reg] = true; 1008 } 1009 return dependents; 1010} 1011 1012template <class Impl> 1013void 1014InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 1015{ 1016 OpClass op_class = ready_inst->opClass(); 1017 1018 readyInsts[op_class].push(ready_inst); 1019 1020 // Will need to reorder the list if either a queue is not on the list, 1021 // or it has an older instruction than last time. 1022 if (!queueOnList[op_class]) { 1023 addToOrderList(op_class); 1024 } else if (readyInsts[op_class].top()->seqNum < 1025 (*readyIt[op_class]).oldestInst) { 1026 listOrder.erase(readyIt[op_class]); 1027 addToOrderList(op_class); 1028 } 1029 1030 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 1031 "the ready list, PC %s opclass:%i [sn:%lli].\n", 1032 ready_inst->pcState(), op_class, ready_inst->seqNum); 1033} 1034 1035template <class Impl> 1036void 1037InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 1038{ 1039 DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 1040 1041 // Reset DTB translation state 1042 resched_inst->translationStarted(false); 1043 resched_inst->translationCompleted(false); 1044 1045 resched_inst->clearCanIssue(); 1046 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 1047} 1048 1049template <class Impl> 1050void 1051InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 1052{ 1053 memDepUnit[replay_inst->threadNumber].replay(replay_inst); 1054} 1055 1056template <class Impl> 1057void 1058InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 1059{ 1060 ThreadID tid = completed_inst->threadNumber; 1061 1062 DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n", 1063 completed_inst->pcState(), completed_inst->seqNum); 1064 1065 ++freeEntries; 1066 1067 completed_inst->memOpDone(true); 1068 1069 memDepUnit[tid].completed(completed_inst); 1070 count[tid]--; 1071} 1072 1073template <class Impl> 1074void 1075InstructionQueue<Impl>::deferMemInst(DynInstPtr &deferred_inst) 1076{ 1077 deferredMemInsts.push_back(deferred_inst); 1078} 1079 1080template <class Impl> 1081typename Impl::DynInstPtr 1082InstructionQueue<Impl>::getDeferredMemInstToExecute() 1083{ 1084 for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end(); 1085 ++it) { 1086 if ((*it)->translationCompleted() || (*it)->isSquashed()) { 1087 DynInstPtr ret = *it; 1088 deferredMemInsts.erase(it); 1089 return ret; 1090 } 1091 } 1092 return NULL; 1093} 1094 1095template <class Impl> 1096void 1097InstructionQueue<Impl>::violation(DynInstPtr &store, 1098 DynInstPtr &faulting_load) 1099{ 1100 intInstQueueWrites++; 1101 memDepUnit[store->threadNumber].violation(store, faulting_load); 1102} 1103 1104template <class Impl> 1105void 1106InstructionQueue<Impl>::squash(ThreadID tid) 1107{ 1108 DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 1109 "the IQ.\n", tid); 1110 1111 // Read instruction sequence number of last instruction out of the 1112 // time buffer. 1113 squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 1114 1115 // Call doSquash if there are insts in the IQ 1116 if (count[tid] > 0) { 1117 doSquash(tid); 1118 } 1119 1120 // Also tell the memory dependence unit to squash. 1121 memDepUnit[tid].squash(squashedSeqNum[tid], tid); 1122} 1123 1124template <class Impl> 1125void 1126InstructionQueue<Impl>::doSquash(ThreadID tid) 1127{ 1128 // Start at the tail. 1129 ListIt squash_it = instList[tid].end(); 1130 --squash_it; 1131 1132 DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 1133 tid, squashedSeqNum[tid]); 1134 1135 // Squash any instructions younger than the squashed sequence number 1136 // given. 1137 while (squash_it != instList[tid].end() && 1138 (*squash_it)->seqNum > squashedSeqNum[tid]) { 1139 1140 DynInstPtr squashed_inst = (*squash_it); 1141 squashed_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 1142 1143 // Only handle the instruction if it actually is in the IQ and 1144 // hasn't already been squashed in the IQ. 1145 if (squashed_inst->threadNumber != tid || 1146 squashed_inst->isSquashedInIQ()) { 1147 --squash_it; 1148 continue; 1149 } 1150 1151 if (!squashed_inst->isIssued() || 1152 (squashed_inst->isMemRef() && 1153 !squashed_inst->memOpDone())) { 1154 1155 DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n", 1156 tid, squashed_inst->seqNum, squashed_inst->pcState()); 1157 1158 bool is_acq_rel = squashed_inst->isMemBarrier() && 1159 (squashed_inst->isLoad() || 1160 (squashed_inst->isStore() && 1161 !squashed_inst->isStoreConditional())); 1162 1163 // Remove the instruction from the dependency list. 1164 if (is_acq_rel || 1165 (!squashed_inst->isNonSpeculative() && 1166 !squashed_inst->isStoreConditional() && 1167 !squashed_inst->isMemBarrier() && 1168 !squashed_inst->isWriteBarrier())) { 1169 1170 for (int src_reg_idx = 0; 1171 src_reg_idx < squashed_inst->numSrcRegs(); 1172 src_reg_idx++) 1173 { 1174 PhysRegIndex src_reg = 1175 squashed_inst->renamedSrcRegIdx(src_reg_idx); 1176 1177 // Only remove it from the dependency graph if it 1178 // was placed there in the first place. 1179 1180 // Instead of doing a linked list traversal, we 1181 // can just remove these squashed instructions 1182 // either at issue time, or when the register is 1183 // overwritten. The only downside to this is it 1184 // leaves more room for error. 1185 1186 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 1187 src_reg < numPhysRegs) { 1188 dependGraph.remove(src_reg, squashed_inst); 1189 } 1190 1191 1192 ++iqSquashedOperandsExamined; 1193 } 1194 } else if (!squashed_inst->isStoreConditional() || 1195 !squashed_inst->isCompleted()) { 1196 NonSpecMapIt ns_inst_it = 1197 nonSpecInsts.find(squashed_inst->seqNum); 1198 1199 // we remove non-speculative instructions from 1200 // nonSpecInsts already when they are ready, and so we 1201 // cannot always expect to find them 1202 if (ns_inst_it == nonSpecInsts.end()) { 1203 // loads that became ready but stalled on a 1204 // blocked cache are alreayd removed from 1205 // nonSpecInsts, and have not faulted 1206 assert(squashed_inst->getFault() != NoFault || 1207 squashed_inst->isMemRef()); 1208 } else { 1209 1210 (*ns_inst_it).second = NULL; 1211 1212 nonSpecInsts.erase(ns_inst_it); 1213 1214 ++iqSquashedNonSpecRemoved; 1215 } 1216 } 1217 1218 // Might want to also clear out the head of the dependency graph. 1219 1220 // Mark it as squashed within the IQ. 1221 squashed_inst->setSquashedInIQ(); 1222 1223 // @todo: Remove this hack where several statuses are set so the 1224 // inst will flow through the rest of the pipeline. 1225 squashed_inst->setIssued(); 1226 squashed_inst->setCanCommit(); 1227 squashed_inst->clearInIQ(); 1228 1229 //Update Thread IQ Count 1230 count[squashed_inst->threadNumber]--; 1231 1232 ++freeEntries; 1233 } 1234 1235 instList[tid].erase(squash_it--); 1236 ++iqSquashedInstsExamined; 1237 } 1238} 1239 1240template <class Impl> 1241bool 1242InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 1243{ 1244 // Loop through the instruction's source registers, adding 1245 // them to the dependency list if they are not ready. 1246 int8_t total_src_regs = new_inst->numSrcRegs(); 1247 bool return_val = false; 1248 1249 for (int src_reg_idx = 0; 1250 src_reg_idx < total_src_regs; 1251 src_reg_idx++) 1252 { 1253 // Only add it to the dependency graph if it's not ready. 1254 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 1255 PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 1256 1257 // Check the IQ's scoreboard to make sure the register 1258 // hasn't become ready while the instruction was in flight 1259 // between stages. Only if it really isn't ready should 1260 // it be added to the dependency graph. 1261 if (src_reg >= numPhysRegs) { 1262 continue; 1263 } else if (!regScoreboard[src_reg]) { 1264 DPRINTF(IQ, "Instruction PC %s has src reg %i that " 1265 "is being added to the dependency chain.\n", 1266 new_inst->pcState(), src_reg); 1267 1268 dependGraph.insert(src_reg, new_inst); 1269 1270 // Change the return value to indicate that something 1271 // was added to the dependency graph. 1272 return_val = true; 1273 } else { 1274 DPRINTF(IQ, "Instruction PC %s has src reg %i that " 1275 "became ready before it reached the IQ.\n", 1276 new_inst->pcState(), src_reg); 1277 // Mark a register ready within the instruction. 1278 new_inst->markSrcRegReady(src_reg_idx); 1279 } 1280 } 1281 } 1282 1283 return return_val; 1284} 1285 1286template <class Impl> 1287void 1288InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst) 1289{ 1290 // Nothing really needs to be marked when an instruction becomes 1291 // the producer of a register's value, but for convenience a ptr 1292 // to the producing instruction will be placed in the head node of 1293 // the dependency links. 1294 int8_t total_dest_regs = new_inst->numDestRegs(); 1295 1296 for (int dest_reg_idx = 0; 1297 dest_reg_idx < total_dest_regs; 1298 dest_reg_idx++) 1299 { 1300 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 1301 1302 // Instructions that use the misc regs will have a reg number 1303 // higher than the normal physical registers. In this case these 1304 // registers are not renamed, and there is no need to track 1305 // dependencies as these instructions must be executed at commit. 1306 if (dest_reg >= numPhysRegs) { 1307 continue; 1308 } 1309 1310 if (!dependGraph.empty(dest_reg)) { 1311 dependGraph.dump(); 1312 panic("Dependency graph %i not empty!", dest_reg); 1313 } 1314 1315 dependGraph.setInst(dest_reg, new_inst); 1316 1317 // Mark the scoreboard to say it's not yet ready. 1318 regScoreboard[dest_reg] = false; 1319 } 1320} 1321 1322template <class Impl> 1323void 1324InstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 1325{ 1326 // If the instruction now has all of its source registers 1327 // available, then add it to the list of ready instructions. 1328 if (inst->readyToIssue()) { 1329 1330 //Add the instruction to the proper ready list. 1331 if (inst->isMemRef()) { 1332 1333 DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 1334 1335 // Message to the mem dependence unit that this instruction has 1336 // its registers ready. 1337 memDepUnit[inst->threadNumber].regsReady(inst); 1338 1339 return; 1340 } 1341 1342 OpClass op_class = inst->opClass(); 1343 1344 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 1345 "the ready list, PC %s opclass:%i [sn:%lli].\n", 1346 inst->pcState(), op_class, inst->seqNum); 1347 1348 readyInsts[op_class].push(inst); 1349 1350 // Will need to reorder the list if either a queue is not on the list, 1351 // or it has an older instruction than last time. 1352 if (!queueOnList[op_class]) { 1353 addToOrderList(op_class); 1354 } else if (readyInsts[op_class].top()->seqNum < 1355 (*readyIt[op_class]).oldestInst) { 1356 listOrder.erase(readyIt[op_class]); 1357 addToOrderList(op_class); 1358 } 1359 } 1360} 1361 1362template <class Impl> 1363int 1364InstructionQueue<Impl>::countInsts() 1365{ 1366#if 0 1367 //ksewell:This works but definitely could use a cleaner write 1368 //with a more intuitive way of counting. Right now it's 1369 //just brute force .... 1370 // Change the #if if you want to use this method. 1371 int total_insts = 0; 1372 1373 for (ThreadID tid = 0; tid < numThreads; ++tid) { 1374 ListIt count_it = instList[tid].begin(); 1375 1376 while (count_it != instList[tid].end()) { 1377 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 1378 if (!(*count_it)->isIssued()) { 1379 ++total_insts; 1380 } else if ((*count_it)->isMemRef() && 1381 !(*count_it)->memOpDone) { 1382 // Loads that have not been marked as executed still count 1383 // towards the total instructions. 1384 ++total_insts; 1385 } 1386 } 1387 1388 ++count_it; 1389 } 1390 } 1391 1392 return total_insts; 1393#else 1394 return numEntries - freeEntries; 1395#endif 1396} 1397 1398template <class Impl> 1399void 1400InstructionQueue<Impl>::dumpLists() 1401{ 1402 for (int i = 0; i < Num_OpClasses; ++i) { 1403 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 1404 1405 cprintf("\n"); 1406 } 1407 1408 cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 1409 1410 NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 1411 NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 1412 1413 cprintf("Non speculative list: "); 1414 1415 while (non_spec_it != non_spec_end_it) { 1416 cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(), 1417 (*non_spec_it).second->seqNum); 1418 ++non_spec_it; 1419 } 1420 1421 cprintf("\n"); 1422 1423 ListOrderIt list_order_it = listOrder.begin(); 1424 ListOrderIt list_order_end_it = listOrder.end(); 1425 int i = 1; 1426 1427 cprintf("List order: "); 1428 1429 while (list_order_it != list_order_end_it) { 1430 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 1431 (*list_order_it).oldestInst); 1432 1433 ++list_order_it; 1434 ++i; 1435 } 1436 1437 cprintf("\n"); 1438} 1439 1440 1441template <class Impl> 1442void 1443InstructionQueue<Impl>::dumpInsts() 1444{ 1445 for (ThreadID tid = 0; tid < numThreads; ++tid) { 1446 int num = 0; 1447 int valid_num = 0; 1448 ListIt inst_list_it = instList[tid].begin(); 1449 1450 while (inst_list_it != instList[tid].end()) { 1451 cprintf("Instruction:%i\n", num); 1452 if (!(*inst_list_it)->isSquashed()) { 1453 if (!(*inst_list_it)->isIssued()) { 1454 ++valid_num; 1455 cprintf("Count:%i\n", valid_num); 1456 } else if ((*inst_list_it)->isMemRef() && 1457 !(*inst_list_it)->memOpDone()) { 1458 // Loads that have not been marked as executed 1459 // still count towards the total instructions. 1460 ++valid_num; 1461 cprintf("Count:%i\n", valid_num); 1462 } 1463 } 1464 1465 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 1466 "Issued:%i\nSquashed:%i\n", 1467 (*inst_list_it)->pcState(), 1468 (*inst_list_it)->seqNum, 1469 (*inst_list_it)->threadNumber, 1470 (*inst_list_it)->isIssued(), 1471 (*inst_list_it)->isSquashed()); 1472 1473 if ((*inst_list_it)->isMemRef()) { 1474 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 1475 } 1476 1477 cprintf("\n"); 1478 1479 inst_list_it++; 1480 ++num; 1481 } 1482 } 1483 1484 cprintf("Insts to Execute list:\n"); 1485 1486 int num = 0; 1487 int valid_num = 0; 1488 ListIt inst_list_it = instsToExecute.begin(); 1489 1490 while (inst_list_it != instsToExecute.end()) 1491 { 1492 cprintf("Instruction:%i\n", 1493 num); 1494 if (!(*inst_list_it)->isSquashed()) { 1495 if (!(*inst_list_it)->isIssued()) { 1496 ++valid_num; 1497 cprintf("Count:%i\n", valid_num); 1498 } else if ((*inst_list_it)->isMemRef() && 1499 !(*inst_list_it)->memOpDone()) { 1500 // Loads that have not been marked as executed 1501 // still count towards the total instructions. 1502 ++valid_num; 1503 cprintf("Count:%i\n", valid_num); 1504 } 1505 } 1506 1507 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 1508 "Issued:%i\nSquashed:%i\n", 1509 (*inst_list_it)->pcState(), 1510 (*inst_list_it)->seqNum, 1511 (*inst_list_it)->threadNumber, 1512 (*inst_list_it)->isIssued(), 1513 (*inst_list_it)->isSquashed()); 1514 1515 if ((*inst_list_it)->isMemRef()) { 1516 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 1517 } 1518 1519 cprintf("\n"); 1520 1521 inst_list_it++; 1522 ++num; 1523 } 1524} 1525 1526#endif//__CPU_O3_INST_QUEUE_IMPL_HH__ |