1/* |
2 * Copyright (c) 2011-2012 ARM Limited |
3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 77 unchanged lines hidden (view full) --- 88 numEntries(params->numIQEntries), 89 totalWidth(params->issueWidth), 90 numPhysIntRegs(params->numPhysIntRegs), 91 numPhysFloatRegs(params->numPhysFloatRegs), 92 commitToIEWDelay(params->commitToIEWDelay) 93{ 94 assert(fuPool); 95 |
96 numThreads = params->numThreads; 97 98 // Set the number of physical registers as the number of int + float 99 numPhysRegs = numPhysIntRegs + numPhysFloatRegs; 100 101 //Create an entry for each physical register within the 102 //dependency graph. 103 dependGraph.resize(numPhysRegs); --- 328 unchanged lines hidden (view full) --- 432{ 433 timeBuffer = tb_ptr; 434 435 fromCommit = timeBuffer->getWire(-commitToIEWDelay); 436} 437 438template <class Impl> 439void |
440InstructionQueue<Impl>::drainSanityCheck() const |
441{ |
442 assert(dependGraph.empty()); 443 assert(instsToExecute.empty()); 444 for (ThreadID tid = 0; tid < numThreads; ++tid) 445 memDepUnit[tid].drainSanityCheck(); |
446} 447 448template <class Impl> 449void 450InstructionQueue<Impl>::takeOverFrom() 451{ |
452 resetState(); |
453} 454 455template <class Impl> 456int 457InstructionQueue<Impl>::entryAmount(ThreadID num_threads) 458{ 459 if (iqPolicy == Partitioned) { 460 return numEntries / num_threads; --- 238 unchanged lines hidden (view full) --- 699 readyIt[op_class] = listOrder.insert(next_it, queue_entry); 700} 701 702template <class Impl> 703void 704InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 705{ 706 DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); |
707 assert(!cpu->switchedOut()); |
708 // The CPU could have been sleeping until this op completed (*extremely* 709 // long latency op). Wake it if it was. This may be overkill. |
710 iewStage->wakeCPU(); 711 712 if (fu_idx > -1) 713 fuPool->freeUnitNextCycle(fu_idx); 714 715 // @todo: Ensure that these FU Completions happen at the beginning 716 // of a cycle, otherwise they could add too many instructions to 717 // the queue. --- 793 unchanged lines hidden --- |