1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 815 unchanged lines hidden (view full) --- 824 "to execute.\n", inst); 825 826 NonSpecMapIt inst_it = nonSpecInsts.find(inst); 827 828 assert(inst_it != nonSpecInsts.end()); 829 830 unsigned tid = (*inst_it).second->threadNumber; 831 |
832 (*inst_it).second->setAtCommit(); 833 |
834 (*inst_it).second->setCanIssue(); 835 836 if (!(*inst_it).second->isMemRef()) { 837 addIfReady((*inst_it).second); 838 } else { 839 memDepUnit[tid].nonSpecInstReady((*inst_it).second); 840 } 841 --- 115 unchanged lines hidden (view full) --- 957 "the ready list, PC %#x opclass:%i [sn:%lli].\n", 958 ready_inst->readPC(), op_class, ready_inst->seqNum); 959} 960 961template <class Impl> 962void 963InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 964{ |
965 DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 966 resched_inst->clearCanIssue(); |
967 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 968} 969 970template <class Impl> 971void 972InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 973{ 974 memDepUnit[replay_inst->threadNumber].replay(replay_inst); --- 8 unchanged lines hidden (view full) --- 983 DPRINTF(IQ, "Completing mem instruction PC:%#x [sn:%lli]\n", 984 completed_inst->readPC(), completed_inst->seqNum); 985 986 ++freeEntries; 987 988 completed_inst->memOpDone = true; 989 990 memDepUnit[tid].completed(completed_inst); |
991 count[tid]--; 992} 993 994template <class Impl> 995void 996InstructionQueue<Impl>::violation(DynInstPtr &store, 997 DynInstPtr &faulting_load) 998{ --- 83 unchanged lines hidden (view full) --- 1082 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 1083 src_reg < numPhysRegs) { 1084 dependGraph.remove(src_reg, squashed_inst); 1085 } 1086 1087 1088 ++iqSquashedOperandsExamined; 1089 } |
1090 } else if (!squashed_inst->isStoreConditional() || 1091 !squashed_inst->isCompleted()) { |
1092 NonSpecMapIt ns_inst_it = 1093 nonSpecInsts.find(squashed_inst->seqNum); 1094 assert(ns_inst_it != nonSpecInsts.end()); |
1095 if (ns_inst_it == nonSpecInsts.end()) { 1096 assert(squashed_inst->getFault() != NoFault); 1097 } else { |
1098 |
1099 (*ns_inst_it).second = NULL; |
1100 |
1101 nonSpecInsts.erase(ns_inst_it); |
1102 |
1103 ++iqSquashedNonSpecRemoved; 1104 } |
1105 } 1106 1107 // Might want to also clear out the head of the dependency graph. 1108 1109 // Mark it as squashed within the IQ. 1110 squashed_inst->setSquashedInIQ(); 1111 1112 // @todo: Remove this hack where several statuses are set so the --- 303 unchanged lines hidden --- |