35c35
< #include "sim/root.hh"
---
> #include "sim/core.hh"
832,833d831
< (*inst_it).second->setAtCommit();
<
965,966d962
< DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum);
< resched_inst->clearCanIssue();
990a987
>
1090,1091c1087
< } else if (!squashed_inst->isStoreConditional() ||
< !squashed_inst->isCompleted()) {
---
> } else if (!squashed_inst->isStoreConditional() || !squashed_inst->isCompleted()) {
1095,1097d1090
< if (ns_inst_it == nonSpecInsts.end()) {
< assert(squashed_inst->getFault() != NoFault);
< } else {
1099c1092
< (*ns_inst_it).second = NULL;
---
> (*ns_inst_it).second = NULL;
1101c1094
< nonSpecInsts.erase(ns_inst_it);
---
> nonSpecInsts.erase(ns_inst_it);
1103,1104c1096
< ++iqSquashedNonSpecRemoved;
< }
---
> ++iqSquashedNonSpecRemoved;