1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include <limits>
33#include <vector>
34
35#include "sim/core.hh"
36
37#include "cpu/o3/fu_pool.hh"
38#include "cpu/o3/inst_queue.hh"
39
40template <class Impl>
41InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
42 int fu_idx,
43 InstructionQueue<Impl> *iq_ptr)
44 : Event(&mainEventQueue, Stat_Event_Pri),
45 inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false)
46{
47 this->setFlags(Event::AutoDelete);
48}
49
50template <class Impl>
51void
52InstructionQueue<Impl>::FUCompletion::process()
53{
54 iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1);
55 inst = NULL;
56}
57
58
59template <class Impl>
60const char *
61InstructionQueue<Impl>::FUCompletion::description()
62{
63 return "Functional unit completion event";
64}
65
66template <class Impl>
67InstructionQueue<Impl>::InstructionQueue(Params *params)
68 : fuPool(params->fuPool),
69 numEntries(params->numIQEntries),
70 totalWidth(params->issueWidth),
71 numPhysIntRegs(params->numPhysIntRegs),
72 numPhysFloatRegs(params->numPhysFloatRegs),
73 commitToIEWDelay(params->commitToIEWDelay)
74{
75 assert(fuPool);
76
77 switchedOut = false;
78
79 numThreads = params->numberOfThreads;
80
81 // Set the number of physical registers as the number of int + float
82 numPhysRegs = numPhysIntRegs + numPhysFloatRegs;
83
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include <limits>
33#include <vector>
34
35#include "sim/core.hh"
36
37#include "cpu/o3/fu_pool.hh"
38#include "cpu/o3/inst_queue.hh"
39
40template <class Impl>
41InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
42 int fu_idx,
43 InstructionQueue<Impl> *iq_ptr)
44 : Event(&mainEventQueue, Stat_Event_Pri),
45 inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false)
46{
47 this->setFlags(Event::AutoDelete);
48}
49
50template <class Impl>
51void
52InstructionQueue<Impl>::FUCompletion::process()
53{
54 iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1);
55 inst = NULL;
56}
57
58
59template <class Impl>
60const char *
61InstructionQueue<Impl>::FUCompletion::description()
62{
63 return "Functional unit completion event";
64}
65
66template <class Impl>
67InstructionQueue<Impl>::InstructionQueue(Params *params)
68 : fuPool(params->fuPool),
69 numEntries(params->numIQEntries),
70 totalWidth(params->issueWidth),
71 numPhysIntRegs(params->numPhysIntRegs),
72 numPhysFloatRegs(params->numPhysFloatRegs),
73 commitToIEWDelay(params->commitToIEWDelay)
74{
75 assert(fuPool);
76
77 switchedOut = false;
78
79 numThreads = params->numberOfThreads;
80
81 // Set the number of physical registers as the number of int + float
82 numPhysRegs = numPhysIntRegs + numPhysFloatRegs;
83
|
380 timeBuffer = tb_ptr;
381
382 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
383}
384
385template <class Impl>
386void
387InstructionQueue<Impl>::switchOut()
388{
389/*
390 if (!instList[0].empty() || (numEntries != freeEntries) ||
391 !readyInsts[0].empty() || !nonSpecInsts.empty() || !listOrder.empty()) {
392 dumpInsts();
393// assert(0);
394 }
395*/
396 resetState();
397 dependGraph.reset();
398 instsToExecute.clear();
399 switchedOut = true;
400 for (int i = 0; i < numThreads; ++i) {
401 memDepUnit[i].switchOut();
402 }
403}
404
405template <class Impl>
406void
407InstructionQueue<Impl>::takeOverFrom()
408{
409 switchedOut = false;
410}
411
412template <class Impl>
413int
414InstructionQueue<Impl>::entryAmount(int num_threads)
415{
416 if (iqPolicy == Partitioned) {
417 return numEntries / num_threads;
418 } else {
419 return 0;
420 }
421}
422
423
424template <class Impl>
425void
426InstructionQueue<Impl>::resetEntries()
427{
428 if (iqPolicy != Dynamic || numThreads > 1) {
429 int active_threads = activeThreads->size();
430
431 std::list<unsigned>::iterator threads = activeThreads->begin();
432 std::list<unsigned>::iterator end = activeThreads->end();
433
434 while (threads != end) {
435 unsigned tid = *threads++;
436
437 if (iqPolicy == Partitioned) {
438 maxEntries[tid] = numEntries / active_threads;
439 } else if(iqPolicy == Threshold && active_threads == 1) {
440 maxEntries[tid] = numEntries;
441 }
442 }
443 }
444}
445
446template <class Impl>
447unsigned
448InstructionQueue<Impl>::numFreeEntries()
449{
450 return freeEntries;
451}
452
453template <class Impl>
454unsigned
455InstructionQueue<Impl>::numFreeEntries(unsigned tid)
456{
457 return maxEntries[tid] - count[tid];
458}
459
460// Might want to do something more complex if it knows how many instructions
461// will be issued this cycle.
462template <class Impl>
463bool
464InstructionQueue<Impl>::isFull()
465{
466 if (freeEntries == 0) {
467 return(true);
468 } else {
469 return(false);
470 }
471}
472
473template <class Impl>
474bool
475InstructionQueue<Impl>::isFull(unsigned tid)
476{
477 if (numFreeEntries(tid) == 0) {
478 return(true);
479 } else {
480 return(false);
481 }
482}
483
484template <class Impl>
485bool
486InstructionQueue<Impl>::hasReadyInsts()
487{
488 if (!listOrder.empty()) {
489 return true;
490 }
491
492 for (int i = 0; i < Num_OpClasses; ++i) {
493 if (!readyInsts[i].empty()) {
494 return true;
495 }
496 }
497
498 return false;
499}
500
501template <class Impl>
502void
503InstructionQueue<Impl>::insert(DynInstPtr &new_inst)
504{
505 // Make sure the instruction is valid
506 assert(new_inst);
507
508 DPRINTF(IQ, "Adding instruction [sn:%lli] PC %#x to the IQ.\n",
509 new_inst->seqNum, new_inst->readPC());
510
511 assert(freeEntries != 0);
512
513 instList[new_inst->threadNumber].push_back(new_inst);
514
515 --freeEntries;
516
517 new_inst->setInIQ();
518
519 // Look through its source registers (physical regs), and mark any
520 // dependencies.
521 addToDependents(new_inst);
522
523 // Have this instruction set itself as the producer of its destination
524 // register(s).
525 addToProducers(new_inst);
526
527 if (new_inst->isMemRef()) {
528 memDepUnit[new_inst->threadNumber].insert(new_inst);
529 } else {
530 addIfReady(new_inst);
531 }
532
533 ++iqInstsAdded;
534
535 count[new_inst->threadNumber]++;
536
537 assert(freeEntries == (numEntries - countInsts()));
538}
539
540template <class Impl>
541void
542InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst)
543{
544 // @todo: Clean up this code; can do it by setting inst as unable
545 // to issue, then calling normal insert on the inst.
546
547 assert(new_inst);
548
549 nonSpecInsts[new_inst->seqNum] = new_inst;
550
551 DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %#x "
552 "to the IQ.\n",
553 new_inst->seqNum, new_inst->readPC());
554
555 assert(freeEntries != 0);
556
557 instList[new_inst->threadNumber].push_back(new_inst);
558
559 --freeEntries;
560
561 new_inst->setInIQ();
562
563 // Have this instruction set itself as the producer of its destination
564 // register(s).
565 addToProducers(new_inst);
566
567 // If it's a memory instruction, add it to the memory dependency
568 // unit.
569 if (new_inst->isMemRef()) {
570 memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst);
571 }
572
573 ++iqNonSpecInstsAdded;
574
575 count[new_inst->threadNumber]++;
576
577 assert(freeEntries == (numEntries - countInsts()));
578}
579
580template <class Impl>
581void
582InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst)
583{
584 memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst);
585
586 insertNonSpec(barr_inst);
587}
588
589template <class Impl>
590typename Impl::DynInstPtr
591InstructionQueue<Impl>::getInstToExecute()
592{
593 assert(!instsToExecute.empty());
594 DynInstPtr inst = instsToExecute.front();
595 instsToExecute.pop_front();
596 return inst;
597}
598
599template <class Impl>
600void
601InstructionQueue<Impl>::addToOrderList(OpClass op_class)
602{
603 assert(!readyInsts[op_class].empty());
604
605 ListOrderEntry queue_entry;
606
607 queue_entry.queueType = op_class;
608
609 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
610
611 ListOrderIt list_it = listOrder.begin();
612 ListOrderIt list_end_it = listOrder.end();
613
614 while (list_it != list_end_it) {
615 if ((*list_it).oldestInst > queue_entry.oldestInst) {
616 break;
617 }
618
619 list_it++;
620 }
621
622 readyIt[op_class] = listOrder.insert(list_it, queue_entry);
623 queueOnList[op_class] = true;
624}
625
626template <class Impl>
627void
628InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it)
629{
630 // Get iterator of next item on the list
631 // Delete the original iterator
632 // Determine if the next item is either the end of the list or younger
633 // than the new instruction. If so, then add in a new iterator right here.
634 // If not, then move along.
635 ListOrderEntry queue_entry;
636 OpClass op_class = (*list_order_it).queueType;
637 ListOrderIt next_it = list_order_it;
638
639 ++next_it;
640
641 queue_entry.queueType = op_class;
642 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
643
644 while (next_it != listOrder.end() &&
645 (*next_it).oldestInst < queue_entry.oldestInst) {
646 ++next_it;
647 }
648
649 readyIt[op_class] = listOrder.insert(next_it, queue_entry);
650}
651
652template <class Impl>
653void
654InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx)
655{
656 DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum);
657 // The CPU could have been sleeping until this op completed (*extremely*
658 // long latency op). Wake it if it was. This may be overkill.
659 if (isSwitchedOut()) {
660 DPRINTF(IQ, "FU completion not processed, IQ is switched out [sn:%lli]\n",
661 inst->seqNum);
662 return;
663 }
664
665 iewStage->wakeCPU();
666
667 if (fu_idx > -1)
668 fuPool->freeUnitNextCycle(fu_idx);
669
670 // @todo: Ensure that these FU Completions happen at the beginning
671 // of a cycle, otherwise they could add too many instructions to
672 // the queue.
673 issueToExecuteQueue->access(0)->size++;
674 instsToExecute.push_back(inst);
675}
676
677// @todo: Figure out a better way to remove the squashed items from the
678// lists. Checking the top item of each list to see if it's squashed
679// wastes time and forces jumps.
680template <class Impl>
681void
682InstructionQueue<Impl>::scheduleReadyInsts()
683{
684 DPRINTF(IQ, "Attempting to schedule ready instructions from "
685 "the IQ.\n");
686
687 IssueStruct *i2e_info = issueToExecuteQueue->access(0);
688
689 // Have iterator to head of the list
690 // While I haven't exceeded bandwidth or reached the end of the list,
691 // Try to get a FU that can do what this op needs.
692 // If successful, change the oldestInst to the new top of the list, put
693 // the queue in the proper place in the list.
694 // Increment the iterator.
695 // This will avoid trying to schedule a certain op class if there are no
696 // FUs that handle it.
697 ListOrderIt order_it = listOrder.begin();
698 ListOrderIt order_end_it = listOrder.end();
699 int total_issued = 0;
700
701 while (total_issued < totalWidth &&
702 iewStage->canIssue() &&
703 order_it != order_end_it) {
704 OpClass op_class = (*order_it).queueType;
705
706 assert(!readyInsts[op_class].empty());
707
708 DynInstPtr issuing_inst = readyInsts[op_class].top();
709
710 assert(issuing_inst->seqNum == (*order_it).oldestInst);
711
712 if (issuing_inst->isSquashed()) {
713 readyInsts[op_class].pop();
714
715 if (!readyInsts[op_class].empty()) {
716 moveToYoungerInst(order_it);
717 } else {
718 readyIt[op_class] = listOrder.end();
719 queueOnList[op_class] = false;
720 }
721
722 listOrder.erase(order_it++);
723
724 ++iqSquashedInstsIssued;
725
726 continue;
727 }
728
729 int idx = -2;
730 int op_latency = 1;
731 int tid = issuing_inst->threadNumber;
732
733 if (op_class != No_OpClass) {
734 idx = fuPool->getUnit(op_class);
735
736 if (idx > -1) {
737 op_latency = fuPool->getOpLatency(op_class);
738 }
739 }
740
741 // If we have an instruction that doesn't require a FU, or a
742 // valid FU, then schedule for execution.
743 if (idx == -2 || idx != -1) {
744 if (op_latency == 1) {
745 i2e_info->size++;
746 instsToExecute.push_back(issuing_inst);
747
748 // Add the FU onto the list of FU's to be freed next
749 // cycle if we used one.
750 if (idx >= 0)
751 fuPool->freeUnitNextCycle(idx);
752 } else {
753 int issue_latency = fuPool->getIssueLatency(op_class);
754 // Generate completion event for the FU
755 FUCompletion *execution = new FUCompletion(issuing_inst,
756 idx, this);
757
758 execution->schedule(curTick + cpu->cycles(issue_latency - 1));
759
760 // @todo: Enforce that issue_latency == 1 or op_latency
761 if (issue_latency > 1) {
762 // If FU isn't pipelined, then it must be freed
763 // upon the execution completing.
764 execution->setFreeFU();
765 } else {
766 // Add the FU onto the list of FU's to be freed next cycle.
767 fuPool->freeUnitNextCycle(idx);
768 }
769 }
770
771 DPRINTF(IQ, "Thread %i: Issuing instruction PC %#x "
772 "[sn:%lli]\n",
773 tid, issuing_inst->readPC(),
774 issuing_inst->seqNum);
775
776 readyInsts[op_class].pop();
777
778 if (!readyInsts[op_class].empty()) {
779 moveToYoungerInst(order_it);
780 } else {
781 readyIt[op_class] = listOrder.end();
782 queueOnList[op_class] = false;
783 }
784
785 issuing_inst->setIssued();
786 ++total_issued;
787
788 if (!issuing_inst->isMemRef()) {
789 // Memory instructions can not be freed from the IQ until they
790 // complete.
791 ++freeEntries;
792 count[tid]--;
793 issuing_inst->clearInIQ();
794 } else {
795 memDepUnit[tid].issue(issuing_inst);
796 }
797
798 listOrder.erase(order_it++);
799 statIssuedInstType[tid][op_class]++;
800 iewStage->incrWb(issuing_inst->seqNum);
801 } else {
802 statFuBusy[op_class]++;
803 fuBusy[tid]++;
804 ++order_it;
805 }
806 }
807
808 numIssuedDist.sample(total_issued);
809 iqInstsIssued+= total_issued;
810
811 // If we issued any instructions, tell the CPU we had activity.
812 if (total_issued) {
813 cpu->activityThisCycle();
814 } else {
815 DPRINTF(IQ, "Not able to schedule any instructions.\n");
816 }
817}
818
819template <class Impl>
820void
821InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
822{
823 DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready "
824 "to execute.\n", inst);
825
826 NonSpecMapIt inst_it = nonSpecInsts.find(inst);
827
828 assert(inst_it != nonSpecInsts.end());
829
830 unsigned tid = (*inst_it).second->threadNumber;
831
832 (*inst_it).second->setAtCommit();
833
834 (*inst_it).second->setCanIssue();
835
836 if (!(*inst_it).second->isMemRef()) {
837 addIfReady((*inst_it).second);
838 } else {
839 memDepUnit[tid].nonSpecInstReady((*inst_it).second);
840 }
841
842 (*inst_it).second = NULL;
843
844 nonSpecInsts.erase(inst_it);
845}
846
847template <class Impl>
848void
849InstructionQueue<Impl>::commit(const InstSeqNum &inst, unsigned tid)
850{
851 DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n",
852 tid,inst);
853
854 ListIt iq_it = instList[tid].begin();
855
856 while (iq_it != instList[tid].end() &&
857 (*iq_it)->seqNum <= inst) {
858 ++iq_it;
859 instList[tid].pop_front();
860 }
861
862 assert(freeEntries == (numEntries - countInsts()));
863}
864
865template <class Impl>
866int
867InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
868{
869 int dependents = 0;
870
871 DPRINTF(IQ, "Waking dependents of completed instruction.\n");
872
873 assert(!completed_inst->isSquashed());
874
875 // Tell the memory dependence unit to wake any dependents on this
876 // instruction if it is a memory instruction. Also complete the memory
877 // instruction at this point since we know it executed without issues.
878 // @todo: Might want to rename "completeMemInst" to something that
879 // indicates that it won't need to be replayed, and call this
880 // earlier. Might not be a big deal.
881 if (completed_inst->isMemRef()) {
882 memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst);
883 completeMemInst(completed_inst);
884 } else if (completed_inst->isMemBarrier() ||
885 completed_inst->isWriteBarrier()) {
886 memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst);
887 }
888
889 for (int dest_reg_idx = 0;
890 dest_reg_idx < completed_inst->numDestRegs();
891 dest_reg_idx++)
892 {
893 PhysRegIndex dest_reg =
894 completed_inst->renamedDestRegIdx(dest_reg_idx);
895
896 // Special case of uniq or control registers. They are not
897 // handled by the IQ and thus have no dependency graph entry.
898 // @todo Figure out a cleaner way to handle this.
899 if (dest_reg >= numPhysRegs) {
900 continue;
901 }
902
903 DPRINTF(IQ, "Waking any dependents on register %i.\n",
904 (int) dest_reg);
905
906 //Go through the dependency chain, marking the registers as
907 //ready within the waiting instructions.
908 DynInstPtr dep_inst = dependGraph.pop(dest_reg);
909
910 while (dep_inst) {
911 DPRINTF(IQ, "Waking up a dependent instruction, PC%#x.\n",
912 dep_inst->readPC());
913
914 // Might want to give more information to the instruction
915 // so that it knows which of its source registers is
916 // ready. However that would mean that the dependency
917 // graph entries would need to hold the src_reg_idx.
918 dep_inst->markSrcRegReady();
919
920 addIfReady(dep_inst);
921
922 dep_inst = dependGraph.pop(dest_reg);
923
924 ++dependents;
925 }
926
927 // Reset the head node now that all of its dependents have
928 // been woken up.
929 assert(dependGraph.empty(dest_reg));
930 dependGraph.clearInst(dest_reg);
931
932 // Mark the scoreboard as having that register ready.
933 regScoreboard[dest_reg] = true;
934 }
935 return dependents;
936}
937
938template <class Impl>
939void
940InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst)
941{
942 OpClass op_class = ready_inst->opClass();
943
944 readyInsts[op_class].push(ready_inst);
945
946 // Will need to reorder the list if either a queue is not on the list,
947 // or it has an older instruction than last time.
948 if (!queueOnList[op_class]) {
949 addToOrderList(op_class);
950 } else if (readyInsts[op_class].top()->seqNum <
951 (*readyIt[op_class]).oldestInst) {
952 listOrder.erase(readyIt[op_class]);
953 addToOrderList(op_class);
954 }
955
956 DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
957 "the ready list, PC %#x opclass:%i [sn:%lli].\n",
958 ready_inst->readPC(), op_class, ready_inst->seqNum);
959}
960
961template <class Impl>
962void
963InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst)
964{
965 DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum);
966 resched_inst->clearCanIssue();
967 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
968}
969
970template <class Impl>
971void
972InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst)
973{
974 memDepUnit[replay_inst->threadNumber].replay(replay_inst);
975}
976
977template <class Impl>
978void
979InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst)
980{
981 int tid = completed_inst->threadNumber;
982
983 DPRINTF(IQ, "Completing mem instruction PC:%#x [sn:%lli]\n",
984 completed_inst->readPC(), completed_inst->seqNum);
985
986 ++freeEntries;
987
988 completed_inst->memOpDone = true;
989
990 memDepUnit[tid].completed(completed_inst);
991 count[tid]--;
992}
993
994template <class Impl>
995void
996InstructionQueue<Impl>::violation(DynInstPtr &store,
997 DynInstPtr &faulting_load)
998{
999 memDepUnit[store->threadNumber].violation(store, faulting_load);
1000}
1001
1002template <class Impl>
1003void
1004InstructionQueue<Impl>::squash(unsigned tid)
1005{
1006 DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in "
1007 "the IQ.\n", tid);
1008
1009 // Read instruction sequence number of last instruction out of the
1010 // time buffer.
1011#if ISA_HAS_DELAY_SLOT
1012 squashedSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
1013#else
1014 squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
1015#endif
1016
1017 // Call doSquash if there are insts in the IQ
1018 if (count[tid] > 0) {
1019 doSquash(tid);
1020 }
1021
1022 // Also tell the memory dependence unit to squash.
1023 memDepUnit[tid].squash(squashedSeqNum[tid], tid);
1024}
1025
1026template <class Impl>
1027void
1028InstructionQueue<Impl>::doSquash(unsigned tid)
1029{
1030 // Start at the tail.
1031 ListIt squash_it = instList[tid].end();
1032 --squash_it;
1033
1034 DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n",
1035 tid, squashedSeqNum[tid]);
1036
1037 // Squash any instructions younger than the squashed sequence number
1038 // given.
1039 while (squash_it != instList[tid].end() &&
1040 (*squash_it)->seqNum > squashedSeqNum[tid]) {
1041
1042 DynInstPtr squashed_inst = (*squash_it);
1043
1044 // Only handle the instruction if it actually is in the IQ and
1045 // hasn't already been squashed in the IQ.
1046 if (squashed_inst->threadNumber != tid ||
1047 squashed_inst->isSquashedInIQ()) {
1048 --squash_it;
1049 continue;
1050 }
1051
1052 if (!squashed_inst->isIssued() ||
1053 (squashed_inst->isMemRef() &&
1054 !squashed_inst->memOpDone)) {
1055
1056 DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x "
1057 "squashed.\n",
1058 tid, squashed_inst->seqNum, squashed_inst->readPC());
1059
1060 // Remove the instruction from the dependency list.
1061 if (!squashed_inst->isNonSpeculative() &&
1062 !squashed_inst->isStoreConditional() &&
1063 !squashed_inst->isMemBarrier() &&
1064 !squashed_inst->isWriteBarrier()) {
1065
1066 for (int src_reg_idx = 0;
1067 src_reg_idx < squashed_inst->numSrcRegs();
1068 src_reg_idx++)
1069 {
1070 PhysRegIndex src_reg =
1071 squashed_inst->renamedSrcRegIdx(src_reg_idx);
1072
1073 // Only remove it from the dependency graph if it
1074 // was placed there in the first place.
1075
1076 // Instead of doing a linked list traversal, we
1077 // can just remove these squashed instructions
1078 // either at issue time, or when the register is
1079 // overwritten. The only downside to this is it
1080 // leaves more room for error.
1081
1082 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) &&
1083 src_reg < numPhysRegs) {
1084 dependGraph.remove(src_reg, squashed_inst);
1085 }
1086
1087
1088 ++iqSquashedOperandsExamined;
1089 }
1090 } else if (!squashed_inst->isStoreConditional() ||
1091 !squashed_inst->isCompleted()) {
1092 NonSpecMapIt ns_inst_it =
1093 nonSpecInsts.find(squashed_inst->seqNum);
1094 assert(ns_inst_it != nonSpecInsts.end());
1095 if (ns_inst_it == nonSpecInsts.end()) {
1096 assert(squashed_inst->getFault() != NoFault);
1097 } else {
1098
1099 (*ns_inst_it).second = NULL;
1100
1101 nonSpecInsts.erase(ns_inst_it);
1102
1103 ++iqSquashedNonSpecRemoved;
1104 }
1105 }
1106
1107 // Might want to also clear out the head of the dependency graph.
1108
1109 // Mark it as squashed within the IQ.
1110 squashed_inst->setSquashedInIQ();
1111
1112 // @todo: Remove this hack where several statuses are set so the
1113 // inst will flow through the rest of the pipeline.
1114 squashed_inst->setIssued();
1115 squashed_inst->setCanCommit();
1116 squashed_inst->clearInIQ();
1117
1118 //Update Thread IQ Count
1119 count[squashed_inst->threadNumber]--;
1120
1121 ++freeEntries;
1122 }
1123
1124 instList[tid].erase(squash_it--);
1125 ++iqSquashedInstsExamined;
1126 }
1127}
1128
1129template <class Impl>
1130bool
1131InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst)
1132{
1133 // Loop through the instruction's source registers, adding
1134 // them to the dependency list if they are not ready.
1135 int8_t total_src_regs = new_inst->numSrcRegs();
1136 bool return_val = false;
1137
1138 for (int src_reg_idx = 0;
1139 src_reg_idx < total_src_regs;
1140 src_reg_idx++)
1141 {
1142 // Only add it to the dependency graph if it's not ready.
1143 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) {
1144 PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx);
1145
1146 // Check the IQ's scoreboard to make sure the register
1147 // hasn't become ready while the instruction was in flight
1148 // between stages. Only if it really isn't ready should
1149 // it be added to the dependency graph.
1150 if (src_reg >= numPhysRegs) {
1151 continue;
1152 } else if (regScoreboard[src_reg] == false) {
1153 DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
1154 "is being added to the dependency chain.\n",
1155 new_inst->readPC(), src_reg);
1156
1157 dependGraph.insert(src_reg, new_inst);
1158
1159 // Change the return value to indicate that something
1160 // was added to the dependency graph.
1161 return_val = true;
1162 } else {
1163 DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
1164 "became ready before it reached the IQ.\n",
1165 new_inst->readPC(), src_reg);
1166 // Mark a register ready within the instruction.
1167 new_inst->markSrcRegReady(src_reg_idx);
1168 }
1169 }
1170 }
1171
1172 return return_val;
1173}
1174
1175template <class Impl>
1176void
1177InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst)
1178{
1179 // Nothing really needs to be marked when an instruction becomes
1180 // the producer of a register's value, but for convenience a ptr
1181 // to the producing instruction will be placed in the head node of
1182 // the dependency links.
1183 int8_t total_dest_regs = new_inst->numDestRegs();
1184
1185 for (int dest_reg_idx = 0;
1186 dest_reg_idx < total_dest_regs;
1187 dest_reg_idx++)
1188 {
1189 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx);
1190
1191 // Instructions that use the misc regs will have a reg number
1192 // higher than the normal physical registers. In this case these
1193 // registers are not renamed, and there is no need to track
1194 // dependencies as these instructions must be executed at commit.
1195 if (dest_reg >= numPhysRegs) {
1196 continue;
1197 }
1198
1199 if (!dependGraph.empty(dest_reg)) {
1200 dependGraph.dump();
1201 panic("Dependency graph %i not empty!", dest_reg);
1202 }
1203
1204 dependGraph.setInst(dest_reg, new_inst);
1205
1206 // Mark the scoreboard to say it's not yet ready.
1207 regScoreboard[dest_reg] = false;
1208 }
1209}
1210
1211template <class Impl>
1212void
1213InstructionQueue<Impl>::addIfReady(DynInstPtr &inst)
1214{
1215 // If the instruction now has all of its source registers
1216 // available, then add it to the list of ready instructions.
1217 if (inst->readyToIssue()) {
1218
1219 //Add the instruction to the proper ready list.
1220 if (inst->isMemRef()) {
1221
1222 DPRINTF(IQ, "Checking if memory instruction can issue.\n");
1223
1224 // Message to the mem dependence unit that this instruction has
1225 // its registers ready.
1226 memDepUnit[inst->threadNumber].regsReady(inst);
1227
1228 return;
1229 }
1230
1231 OpClass op_class = inst->opClass();
1232
1233 DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1234 "the ready list, PC %#x opclass:%i [sn:%lli].\n",
1235 inst->readPC(), op_class, inst->seqNum);
1236
1237 readyInsts[op_class].push(inst);
1238
1239 // Will need to reorder the list if either a queue is not on the list,
1240 // or it has an older instruction than last time.
1241 if (!queueOnList[op_class]) {
1242 addToOrderList(op_class);
1243 } else if (readyInsts[op_class].top()->seqNum <
1244 (*readyIt[op_class]).oldestInst) {
1245 listOrder.erase(readyIt[op_class]);
1246 addToOrderList(op_class);
1247 }
1248 }
1249}
1250
1251template <class Impl>
1252int
1253InstructionQueue<Impl>::countInsts()
1254{
1255#if 0
1256 //ksewell:This works but definitely could use a cleaner write
1257 //with a more intuitive way of counting. Right now it's
1258 //just brute force ....
1259 // Change the #if if you want to use this method.
1260 int total_insts = 0;
1261
1262 for (int i = 0; i < numThreads; ++i) {
1263 ListIt count_it = instList[i].begin();
1264
1265 while (count_it != instList[i].end()) {
1266 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) {
1267 if (!(*count_it)->isIssued()) {
1268 ++total_insts;
1269 } else if ((*count_it)->isMemRef() &&
1270 !(*count_it)->memOpDone) {
1271 // Loads that have not been marked as executed still count
1272 // towards the total instructions.
1273 ++total_insts;
1274 }
1275 }
1276
1277 ++count_it;
1278 }
1279 }
1280
1281 return total_insts;
1282#else
1283 return numEntries - freeEntries;
1284#endif
1285}
1286
1287template <class Impl>
1288void
1289InstructionQueue<Impl>::dumpLists()
1290{
1291 for (int i = 0; i < Num_OpClasses; ++i) {
1292 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size());
1293
1294 cprintf("\n");
1295 }
1296
1297 cprintf("Non speculative list size: %i\n", nonSpecInsts.size());
1298
1299 NonSpecMapIt non_spec_it = nonSpecInsts.begin();
1300 NonSpecMapIt non_spec_end_it = nonSpecInsts.end();
1301
1302 cprintf("Non speculative list: ");
1303
1304 while (non_spec_it != non_spec_end_it) {
1305 cprintf("%#x [sn:%lli]", (*non_spec_it).second->readPC(),
1306 (*non_spec_it).second->seqNum);
1307 ++non_spec_it;
1308 }
1309
1310 cprintf("\n");
1311
1312 ListOrderIt list_order_it = listOrder.begin();
1313 ListOrderIt list_order_end_it = listOrder.end();
1314 int i = 1;
1315
1316 cprintf("List order: ");
1317
1318 while (list_order_it != list_order_end_it) {
1319 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType,
1320 (*list_order_it).oldestInst);
1321
1322 ++list_order_it;
1323 ++i;
1324 }
1325
1326 cprintf("\n");
1327}
1328
1329
1330template <class Impl>
1331void
1332InstructionQueue<Impl>::dumpInsts()
1333{
1334 for (int i = 0; i < numThreads; ++i) {
1335 int num = 0;
1336 int valid_num = 0;
1337 ListIt inst_list_it = instList[i].begin();
1338
1339 while (inst_list_it != instList[i].end())
1340 {
1341 cprintf("Instruction:%i\n",
1342 num);
1343 if (!(*inst_list_it)->isSquashed()) {
1344 if (!(*inst_list_it)->isIssued()) {
1345 ++valid_num;
1346 cprintf("Count:%i\n", valid_num);
1347 } else if ((*inst_list_it)->isMemRef() &&
1348 !(*inst_list_it)->memOpDone) {
1349 // Loads that have not been marked as executed
1350 // still count towards the total instructions.
1351 ++valid_num;
1352 cprintf("Count:%i\n", valid_num);
1353 }
1354 }
1355
1356 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
1357 "Issued:%i\nSquashed:%i\n",
1358 (*inst_list_it)->readPC(),
1359 (*inst_list_it)->seqNum,
1360 (*inst_list_it)->threadNumber,
1361 (*inst_list_it)->isIssued(),
1362 (*inst_list_it)->isSquashed());
1363
1364 if ((*inst_list_it)->isMemRef()) {
1365 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
1366 }
1367
1368 cprintf("\n");
1369
1370 inst_list_it++;
1371 ++num;
1372 }
1373 }
1374
1375 cprintf("Insts to Execute list:\n");
1376
1377 int num = 0;
1378 int valid_num = 0;
1379 ListIt inst_list_it = instsToExecute.begin();
1380
1381 while (inst_list_it != instsToExecute.end())
1382 {
1383 cprintf("Instruction:%i\n",
1384 num);
1385 if (!(*inst_list_it)->isSquashed()) {
1386 if (!(*inst_list_it)->isIssued()) {
1387 ++valid_num;
1388 cprintf("Count:%i\n", valid_num);
1389 } else if ((*inst_list_it)->isMemRef() &&
1390 !(*inst_list_it)->memOpDone) {
1391 // Loads that have not been marked as executed
1392 // still count towards the total instructions.
1393 ++valid_num;
1394 cprintf("Count:%i\n", valid_num);
1395 }
1396 }
1397
1398 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
1399 "Issued:%i\nSquashed:%i\n",
1400 (*inst_list_it)->readPC(),
1401 (*inst_list_it)->seqNum,
1402 (*inst_list_it)->threadNumber,
1403 (*inst_list_it)->isIssued(),
1404 (*inst_list_it)->isSquashed());
1405
1406 if ((*inst_list_it)->isMemRef()) {
1407 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
1408 }
1409
1410 cprintf("\n");
1411
1412 inst_list_it++;
1413 ++num;
1414 }
1415}
| 379 timeBuffer = tb_ptr;
380
381 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
382}
383
384template <class Impl>
385void
386InstructionQueue<Impl>::switchOut()
387{
388/*
389 if (!instList[0].empty() || (numEntries != freeEntries) ||
390 !readyInsts[0].empty() || !nonSpecInsts.empty() || !listOrder.empty()) {
391 dumpInsts();
392// assert(0);
393 }
394*/
395 resetState();
396 dependGraph.reset();
397 instsToExecute.clear();
398 switchedOut = true;
399 for (int i = 0; i < numThreads; ++i) {
400 memDepUnit[i].switchOut();
401 }
402}
403
404template <class Impl>
405void
406InstructionQueue<Impl>::takeOverFrom()
407{
408 switchedOut = false;
409}
410
411template <class Impl>
412int
413InstructionQueue<Impl>::entryAmount(int num_threads)
414{
415 if (iqPolicy == Partitioned) {
416 return numEntries / num_threads;
417 } else {
418 return 0;
419 }
420}
421
422
423template <class Impl>
424void
425InstructionQueue<Impl>::resetEntries()
426{
427 if (iqPolicy != Dynamic || numThreads > 1) {
428 int active_threads = activeThreads->size();
429
430 std::list<unsigned>::iterator threads = activeThreads->begin();
431 std::list<unsigned>::iterator end = activeThreads->end();
432
433 while (threads != end) {
434 unsigned tid = *threads++;
435
436 if (iqPolicy == Partitioned) {
437 maxEntries[tid] = numEntries / active_threads;
438 } else if(iqPolicy == Threshold && active_threads == 1) {
439 maxEntries[tid] = numEntries;
440 }
441 }
442 }
443}
444
445template <class Impl>
446unsigned
447InstructionQueue<Impl>::numFreeEntries()
448{
449 return freeEntries;
450}
451
452template <class Impl>
453unsigned
454InstructionQueue<Impl>::numFreeEntries(unsigned tid)
455{
456 return maxEntries[tid] - count[tid];
457}
458
459// Might want to do something more complex if it knows how many instructions
460// will be issued this cycle.
461template <class Impl>
462bool
463InstructionQueue<Impl>::isFull()
464{
465 if (freeEntries == 0) {
466 return(true);
467 } else {
468 return(false);
469 }
470}
471
472template <class Impl>
473bool
474InstructionQueue<Impl>::isFull(unsigned tid)
475{
476 if (numFreeEntries(tid) == 0) {
477 return(true);
478 } else {
479 return(false);
480 }
481}
482
483template <class Impl>
484bool
485InstructionQueue<Impl>::hasReadyInsts()
486{
487 if (!listOrder.empty()) {
488 return true;
489 }
490
491 for (int i = 0; i < Num_OpClasses; ++i) {
492 if (!readyInsts[i].empty()) {
493 return true;
494 }
495 }
496
497 return false;
498}
499
500template <class Impl>
501void
502InstructionQueue<Impl>::insert(DynInstPtr &new_inst)
503{
504 // Make sure the instruction is valid
505 assert(new_inst);
506
507 DPRINTF(IQ, "Adding instruction [sn:%lli] PC %#x to the IQ.\n",
508 new_inst->seqNum, new_inst->readPC());
509
510 assert(freeEntries != 0);
511
512 instList[new_inst->threadNumber].push_back(new_inst);
513
514 --freeEntries;
515
516 new_inst->setInIQ();
517
518 // Look through its source registers (physical regs), and mark any
519 // dependencies.
520 addToDependents(new_inst);
521
522 // Have this instruction set itself as the producer of its destination
523 // register(s).
524 addToProducers(new_inst);
525
526 if (new_inst->isMemRef()) {
527 memDepUnit[new_inst->threadNumber].insert(new_inst);
528 } else {
529 addIfReady(new_inst);
530 }
531
532 ++iqInstsAdded;
533
534 count[new_inst->threadNumber]++;
535
536 assert(freeEntries == (numEntries - countInsts()));
537}
538
539template <class Impl>
540void
541InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst)
542{
543 // @todo: Clean up this code; can do it by setting inst as unable
544 // to issue, then calling normal insert on the inst.
545
546 assert(new_inst);
547
548 nonSpecInsts[new_inst->seqNum] = new_inst;
549
550 DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %#x "
551 "to the IQ.\n",
552 new_inst->seqNum, new_inst->readPC());
553
554 assert(freeEntries != 0);
555
556 instList[new_inst->threadNumber].push_back(new_inst);
557
558 --freeEntries;
559
560 new_inst->setInIQ();
561
562 // Have this instruction set itself as the producer of its destination
563 // register(s).
564 addToProducers(new_inst);
565
566 // If it's a memory instruction, add it to the memory dependency
567 // unit.
568 if (new_inst->isMemRef()) {
569 memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst);
570 }
571
572 ++iqNonSpecInstsAdded;
573
574 count[new_inst->threadNumber]++;
575
576 assert(freeEntries == (numEntries - countInsts()));
577}
578
579template <class Impl>
580void
581InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst)
582{
583 memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst);
584
585 insertNonSpec(barr_inst);
586}
587
588template <class Impl>
589typename Impl::DynInstPtr
590InstructionQueue<Impl>::getInstToExecute()
591{
592 assert(!instsToExecute.empty());
593 DynInstPtr inst = instsToExecute.front();
594 instsToExecute.pop_front();
595 return inst;
596}
597
598template <class Impl>
599void
600InstructionQueue<Impl>::addToOrderList(OpClass op_class)
601{
602 assert(!readyInsts[op_class].empty());
603
604 ListOrderEntry queue_entry;
605
606 queue_entry.queueType = op_class;
607
608 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
609
610 ListOrderIt list_it = listOrder.begin();
611 ListOrderIt list_end_it = listOrder.end();
612
613 while (list_it != list_end_it) {
614 if ((*list_it).oldestInst > queue_entry.oldestInst) {
615 break;
616 }
617
618 list_it++;
619 }
620
621 readyIt[op_class] = listOrder.insert(list_it, queue_entry);
622 queueOnList[op_class] = true;
623}
624
625template <class Impl>
626void
627InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it)
628{
629 // Get iterator of next item on the list
630 // Delete the original iterator
631 // Determine if the next item is either the end of the list or younger
632 // than the new instruction. If so, then add in a new iterator right here.
633 // If not, then move along.
634 ListOrderEntry queue_entry;
635 OpClass op_class = (*list_order_it).queueType;
636 ListOrderIt next_it = list_order_it;
637
638 ++next_it;
639
640 queue_entry.queueType = op_class;
641 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
642
643 while (next_it != listOrder.end() &&
644 (*next_it).oldestInst < queue_entry.oldestInst) {
645 ++next_it;
646 }
647
648 readyIt[op_class] = listOrder.insert(next_it, queue_entry);
649}
650
651template <class Impl>
652void
653InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx)
654{
655 DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum);
656 // The CPU could have been sleeping until this op completed (*extremely*
657 // long latency op). Wake it if it was. This may be overkill.
658 if (isSwitchedOut()) {
659 DPRINTF(IQ, "FU completion not processed, IQ is switched out [sn:%lli]\n",
660 inst->seqNum);
661 return;
662 }
663
664 iewStage->wakeCPU();
665
666 if (fu_idx > -1)
667 fuPool->freeUnitNextCycle(fu_idx);
668
669 // @todo: Ensure that these FU Completions happen at the beginning
670 // of a cycle, otherwise they could add too many instructions to
671 // the queue.
672 issueToExecuteQueue->access(0)->size++;
673 instsToExecute.push_back(inst);
674}
675
676// @todo: Figure out a better way to remove the squashed items from the
677// lists. Checking the top item of each list to see if it's squashed
678// wastes time and forces jumps.
679template <class Impl>
680void
681InstructionQueue<Impl>::scheduleReadyInsts()
682{
683 DPRINTF(IQ, "Attempting to schedule ready instructions from "
684 "the IQ.\n");
685
686 IssueStruct *i2e_info = issueToExecuteQueue->access(0);
687
688 // Have iterator to head of the list
689 // While I haven't exceeded bandwidth or reached the end of the list,
690 // Try to get a FU that can do what this op needs.
691 // If successful, change the oldestInst to the new top of the list, put
692 // the queue in the proper place in the list.
693 // Increment the iterator.
694 // This will avoid trying to schedule a certain op class if there are no
695 // FUs that handle it.
696 ListOrderIt order_it = listOrder.begin();
697 ListOrderIt order_end_it = listOrder.end();
698 int total_issued = 0;
699
700 while (total_issued < totalWidth &&
701 iewStage->canIssue() &&
702 order_it != order_end_it) {
703 OpClass op_class = (*order_it).queueType;
704
705 assert(!readyInsts[op_class].empty());
706
707 DynInstPtr issuing_inst = readyInsts[op_class].top();
708
709 assert(issuing_inst->seqNum == (*order_it).oldestInst);
710
711 if (issuing_inst->isSquashed()) {
712 readyInsts[op_class].pop();
713
714 if (!readyInsts[op_class].empty()) {
715 moveToYoungerInst(order_it);
716 } else {
717 readyIt[op_class] = listOrder.end();
718 queueOnList[op_class] = false;
719 }
720
721 listOrder.erase(order_it++);
722
723 ++iqSquashedInstsIssued;
724
725 continue;
726 }
727
728 int idx = -2;
729 int op_latency = 1;
730 int tid = issuing_inst->threadNumber;
731
732 if (op_class != No_OpClass) {
733 idx = fuPool->getUnit(op_class);
734
735 if (idx > -1) {
736 op_latency = fuPool->getOpLatency(op_class);
737 }
738 }
739
740 // If we have an instruction that doesn't require a FU, or a
741 // valid FU, then schedule for execution.
742 if (idx == -2 || idx != -1) {
743 if (op_latency == 1) {
744 i2e_info->size++;
745 instsToExecute.push_back(issuing_inst);
746
747 // Add the FU onto the list of FU's to be freed next
748 // cycle if we used one.
749 if (idx >= 0)
750 fuPool->freeUnitNextCycle(idx);
751 } else {
752 int issue_latency = fuPool->getIssueLatency(op_class);
753 // Generate completion event for the FU
754 FUCompletion *execution = new FUCompletion(issuing_inst,
755 idx, this);
756
757 execution->schedule(curTick + cpu->cycles(issue_latency - 1));
758
759 // @todo: Enforce that issue_latency == 1 or op_latency
760 if (issue_latency > 1) {
761 // If FU isn't pipelined, then it must be freed
762 // upon the execution completing.
763 execution->setFreeFU();
764 } else {
765 // Add the FU onto the list of FU's to be freed next cycle.
766 fuPool->freeUnitNextCycle(idx);
767 }
768 }
769
770 DPRINTF(IQ, "Thread %i: Issuing instruction PC %#x "
771 "[sn:%lli]\n",
772 tid, issuing_inst->readPC(),
773 issuing_inst->seqNum);
774
775 readyInsts[op_class].pop();
776
777 if (!readyInsts[op_class].empty()) {
778 moveToYoungerInst(order_it);
779 } else {
780 readyIt[op_class] = listOrder.end();
781 queueOnList[op_class] = false;
782 }
783
784 issuing_inst->setIssued();
785 ++total_issued;
786
787 if (!issuing_inst->isMemRef()) {
788 // Memory instructions can not be freed from the IQ until they
789 // complete.
790 ++freeEntries;
791 count[tid]--;
792 issuing_inst->clearInIQ();
793 } else {
794 memDepUnit[tid].issue(issuing_inst);
795 }
796
797 listOrder.erase(order_it++);
798 statIssuedInstType[tid][op_class]++;
799 iewStage->incrWb(issuing_inst->seqNum);
800 } else {
801 statFuBusy[op_class]++;
802 fuBusy[tid]++;
803 ++order_it;
804 }
805 }
806
807 numIssuedDist.sample(total_issued);
808 iqInstsIssued+= total_issued;
809
810 // If we issued any instructions, tell the CPU we had activity.
811 if (total_issued) {
812 cpu->activityThisCycle();
813 } else {
814 DPRINTF(IQ, "Not able to schedule any instructions.\n");
815 }
816}
817
818template <class Impl>
819void
820InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
821{
822 DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready "
823 "to execute.\n", inst);
824
825 NonSpecMapIt inst_it = nonSpecInsts.find(inst);
826
827 assert(inst_it != nonSpecInsts.end());
828
829 unsigned tid = (*inst_it).second->threadNumber;
830
831 (*inst_it).second->setAtCommit();
832
833 (*inst_it).second->setCanIssue();
834
835 if (!(*inst_it).second->isMemRef()) {
836 addIfReady((*inst_it).second);
837 } else {
838 memDepUnit[tid].nonSpecInstReady((*inst_it).second);
839 }
840
841 (*inst_it).second = NULL;
842
843 nonSpecInsts.erase(inst_it);
844}
845
846template <class Impl>
847void
848InstructionQueue<Impl>::commit(const InstSeqNum &inst, unsigned tid)
849{
850 DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n",
851 tid,inst);
852
853 ListIt iq_it = instList[tid].begin();
854
855 while (iq_it != instList[tid].end() &&
856 (*iq_it)->seqNum <= inst) {
857 ++iq_it;
858 instList[tid].pop_front();
859 }
860
861 assert(freeEntries == (numEntries - countInsts()));
862}
863
864template <class Impl>
865int
866InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
867{
868 int dependents = 0;
869
870 DPRINTF(IQ, "Waking dependents of completed instruction.\n");
871
872 assert(!completed_inst->isSquashed());
873
874 // Tell the memory dependence unit to wake any dependents on this
875 // instruction if it is a memory instruction. Also complete the memory
876 // instruction at this point since we know it executed without issues.
877 // @todo: Might want to rename "completeMemInst" to something that
878 // indicates that it won't need to be replayed, and call this
879 // earlier. Might not be a big deal.
880 if (completed_inst->isMemRef()) {
881 memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst);
882 completeMemInst(completed_inst);
883 } else if (completed_inst->isMemBarrier() ||
884 completed_inst->isWriteBarrier()) {
885 memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst);
886 }
887
888 for (int dest_reg_idx = 0;
889 dest_reg_idx < completed_inst->numDestRegs();
890 dest_reg_idx++)
891 {
892 PhysRegIndex dest_reg =
893 completed_inst->renamedDestRegIdx(dest_reg_idx);
894
895 // Special case of uniq or control registers. They are not
896 // handled by the IQ and thus have no dependency graph entry.
897 // @todo Figure out a cleaner way to handle this.
898 if (dest_reg >= numPhysRegs) {
899 continue;
900 }
901
902 DPRINTF(IQ, "Waking any dependents on register %i.\n",
903 (int) dest_reg);
904
905 //Go through the dependency chain, marking the registers as
906 //ready within the waiting instructions.
907 DynInstPtr dep_inst = dependGraph.pop(dest_reg);
908
909 while (dep_inst) {
910 DPRINTF(IQ, "Waking up a dependent instruction, PC%#x.\n",
911 dep_inst->readPC());
912
913 // Might want to give more information to the instruction
914 // so that it knows which of its source registers is
915 // ready. However that would mean that the dependency
916 // graph entries would need to hold the src_reg_idx.
917 dep_inst->markSrcRegReady();
918
919 addIfReady(dep_inst);
920
921 dep_inst = dependGraph.pop(dest_reg);
922
923 ++dependents;
924 }
925
926 // Reset the head node now that all of its dependents have
927 // been woken up.
928 assert(dependGraph.empty(dest_reg));
929 dependGraph.clearInst(dest_reg);
930
931 // Mark the scoreboard as having that register ready.
932 regScoreboard[dest_reg] = true;
933 }
934 return dependents;
935}
936
937template <class Impl>
938void
939InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst)
940{
941 OpClass op_class = ready_inst->opClass();
942
943 readyInsts[op_class].push(ready_inst);
944
945 // Will need to reorder the list if either a queue is not on the list,
946 // or it has an older instruction than last time.
947 if (!queueOnList[op_class]) {
948 addToOrderList(op_class);
949 } else if (readyInsts[op_class].top()->seqNum <
950 (*readyIt[op_class]).oldestInst) {
951 listOrder.erase(readyIt[op_class]);
952 addToOrderList(op_class);
953 }
954
955 DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
956 "the ready list, PC %#x opclass:%i [sn:%lli].\n",
957 ready_inst->readPC(), op_class, ready_inst->seqNum);
958}
959
960template <class Impl>
961void
962InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst)
963{
964 DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum);
965 resched_inst->clearCanIssue();
966 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
967}
968
969template <class Impl>
970void
971InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst)
972{
973 memDepUnit[replay_inst->threadNumber].replay(replay_inst);
974}
975
976template <class Impl>
977void
978InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst)
979{
980 int tid = completed_inst->threadNumber;
981
982 DPRINTF(IQ, "Completing mem instruction PC:%#x [sn:%lli]\n",
983 completed_inst->readPC(), completed_inst->seqNum);
984
985 ++freeEntries;
986
987 completed_inst->memOpDone = true;
988
989 memDepUnit[tid].completed(completed_inst);
990 count[tid]--;
991}
992
993template <class Impl>
994void
995InstructionQueue<Impl>::violation(DynInstPtr &store,
996 DynInstPtr &faulting_load)
997{
998 memDepUnit[store->threadNumber].violation(store, faulting_load);
999}
1000
1001template <class Impl>
1002void
1003InstructionQueue<Impl>::squash(unsigned tid)
1004{
1005 DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in "
1006 "the IQ.\n", tid);
1007
1008 // Read instruction sequence number of last instruction out of the
1009 // time buffer.
1010#if ISA_HAS_DELAY_SLOT
1011 squashedSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
1012#else
1013 squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
1014#endif
1015
1016 // Call doSquash if there are insts in the IQ
1017 if (count[tid] > 0) {
1018 doSquash(tid);
1019 }
1020
1021 // Also tell the memory dependence unit to squash.
1022 memDepUnit[tid].squash(squashedSeqNum[tid], tid);
1023}
1024
1025template <class Impl>
1026void
1027InstructionQueue<Impl>::doSquash(unsigned tid)
1028{
1029 // Start at the tail.
1030 ListIt squash_it = instList[tid].end();
1031 --squash_it;
1032
1033 DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n",
1034 tid, squashedSeqNum[tid]);
1035
1036 // Squash any instructions younger than the squashed sequence number
1037 // given.
1038 while (squash_it != instList[tid].end() &&
1039 (*squash_it)->seqNum > squashedSeqNum[tid]) {
1040
1041 DynInstPtr squashed_inst = (*squash_it);
1042
1043 // Only handle the instruction if it actually is in the IQ and
1044 // hasn't already been squashed in the IQ.
1045 if (squashed_inst->threadNumber != tid ||
1046 squashed_inst->isSquashedInIQ()) {
1047 --squash_it;
1048 continue;
1049 }
1050
1051 if (!squashed_inst->isIssued() ||
1052 (squashed_inst->isMemRef() &&
1053 !squashed_inst->memOpDone)) {
1054
1055 DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x "
1056 "squashed.\n",
1057 tid, squashed_inst->seqNum, squashed_inst->readPC());
1058
1059 // Remove the instruction from the dependency list.
1060 if (!squashed_inst->isNonSpeculative() &&
1061 !squashed_inst->isStoreConditional() &&
1062 !squashed_inst->isMemBarrier() &&
1063 !squashed_inst->isWriteBarrier()) {
1064
1065 for (int src_reg_idx = 0;
1066 src_reg_idx < squashed_inst->numSrcRegs();
1067 src_reg_idx++)
1068 {
1069 PhysRegIndex src_reg =
1070 squashed_inst->renamedSrcRegIdx(src_reg_idx);
1071
1072 // Only remove it from the dependency graph if it
1073 // was placed there in the first place.
1074
1075 // Instead of doing a linked list traversal, we
1076 // can just remove these squashed instructions
1077 // either at issue time, or when the register is
1078 // overwritten. The only downside to this is it
1079 // leaves more room for error.
1080
1081 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) &&
1082 src_reg < numPhysRegs) {
1083 dependGraph.remove(src_reg, squashed_inst);
1084 }
1085
1086
1087 ++iqSquashedOperandsExamined;
1088 }
1089 } else if (!squashed_inst->isStoreConditional() ||
1090 !squashed_inst->isCompleted()) {
1091 NonSpecMapIt ns_inst_it =
1092 nonSpecInsts.find(squashed_inst->seqNum);
1093 assert(ns_inst_it != nonSpecInsts.end());
1094 if (ns_inst_it == nonSpecInsts.end()) {
1095 assert(squashed_inst->getFault() != NoFault);
1096 } else {
1097
1098 (*ns_inst_it).second = NULL;
1099
1100 nonSpecInsts.erase(ns_inst_it);
1101
1102 ++iqSquashedNonSpecRemoved;
1103 }
1104 }
1105
1106 // Might want to also clear out the head of the dependency graph.
1107
1108 // Mark it as squashed within the IQ.
1109 squashed_inst->setSquashedInIQ();
1110
1111 // @todo: Remove this hack where several statuses are set so the
1112 // inst will flow through the rest of the pipeline.
1113 squashed_inst->setIssued();
1114 squashed_inst->setCanCommit();
1115 squashed_inst->clearInIQ();
1116
1117 //Update Thread IQ Count
1118 count[squashed_inst->threadNumber]--;
1119
1120 ++freeEntries;
1121 }
1122
1123 instList[tid].erase(squash_it--);
1124 ++iqSquashedInstsExamined;
1125 }
1126}
1127
1128template <class Impl>
1129bool
1130InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst)
1131{
1132 // Loop through the instruction's source registers, adding
1133 // them to the dependency list if they are not ready.
1134 int8_t total_src_regs = new_inst->numSrcRegs();
1135 bool return_val = false;
1136
1137 for (int src_reg_idx = 0;
1138 src_reg_idx < total_src_regs;
1139 src_reg_idx++)
1140 {
1141 // Only add it to the dependency graph if it's not ready.
1142 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) {
1143 PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx);
1144
1145 // Check the IQ's scoreboard to make sure the register
1146 // hasn't become ready while the instruction was in flight
1147 // between stages. Only if it really isn't ready should
1148 // it be added to the dependency graph.
1149 if (src_reg >= numPhysRegs) {
1150 continue;
1151 } else if (regScoreboard[src_reg] == false) {
1152 DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
1153 "is being added to the dependency chain.\n",
1154 new_inst->readPC(), src_reg);
1155
1156 dependGraph.insert(src_reg, new_inst);
1157
1158 // Change the return value to indicate that something
1159 // was added to the dependency graph.
1160 return_val = true;
1161 } else {
1162 DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
1163 "became ready before it reached the IQ.\n",
1164 new_inst->readPC(), src_reg);
1165 // Mark a register ready within the instruction.
1166 new_inst->markSrcRegReady(src_reg_idx);
1167 }
1168 }
1169 }
1170
1171 return return_val;
1172}
1173
1174template <class Impl>
1175void
1176InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst)
1177{
1178 // Nothing really needs to be marked when an instruction becomes
1179 // the producer of a register's value, but for convenience a ptr
1180 // to the producing instruction will be placed in the head node of
1181 // the dependency links.
1182 int8_t total_dest_regs = new_inst->numDestRegs();
1183
1184 for (int dest_reg_idx = 0;
1185 dest_reg_idx < total_dest_regs;
1186 dest_reg_idx++)
1187 {
1188 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx);
1189
1190 // Instructions that use the misc regs will have a reg number
1191 // higher than the normal physical registers. In this case these
1192 // registers are not renamed, and there is no need to track
1193 // dependencies as these instructions must be executed at commit.
1194 if (dest_reg >= numPhysRegs) {
1195 continue;
1196 }
1197
1198 if (!dependGraph.empty(dest_reg)) {
1199 dependGraph.dump();
1200 panic("Dependency graph %i not empty!", dest_reg);
1201 }
1202
1203 dependGraph.setInst(dest_reg, new_inst);
1204
1205 // Mark the scoreboard to say it's not yet ready.
1206 regScoreboard[dest_reg] = false;
1207 }
1208}
1209
1210template <class Impl>
1211void
1212InstructionQueue<Impl>::addIfReady(DynInstPtr &inst)
1213{
1214 // If the instruction now has all of its source registers
1215 // available, then add it to the list of ready instructions.
1216 if (inst->readyToIssue()) {
1217
1218 //Add the instruction to the proper ready list.
1219 if (inst->isMemRef()) {
1220
1221 DPRINTF(IQ, "Checking if memory instruction can issue.\n");
1222
1223 // Message to the mem dependence unit that this instruction has
1224 // its registers ready.
1225 memDepUnit[inst->threadNumber].regsReady(inst);
1226
1227 return;
1228 }
1229
1230 OpClass op_class = inst->opClass();
1231
1232 DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1233 "the ready list, PC %#x opclass:%i [sn:%lli].\n",
1234 inst->readPC(), op_class, inst->seqNum);
1235
1236 readyInsts[op_class].push(inst);
1237
1238 // Will need to reorder the list if either a queue is not on the list,
1239 // or it has an older instruction than last time.
1240 if (!queueOnList[op_class]) {
1241 addToOrderList(op_class);
1242 } else if (readyInsts[op_class].top()->seqNum <
1243 (*readyIt[op_class]).oldestInst) {
1244 listOrder.erase(readyIt[op_class]);
1245 addToOrderList(op_class);
1246 }
1247 }
1248}
1249
1250template <class Impl>
1251int
1252InstructionQueue<Impl>::countInsts()
1253{
1254#if 0
1255 //ksewell:This works but definitely could use a cleaner write
1256 //with a more intuitive way of counting. Right now it's
1257 //just brute force ....
1258 // Change the #if if you want to use this method.
1259 int total_insts = 0;
1260
1261 for (int i = 0; i < numThreads; ++i) {
1262 ListIt count_it = instList[i].begin();
1263
1264 while (count_it != instList[i].end()) {
1265 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) {
1266 if (!(*count_it)->isIssued()) {
1267 ++total_insts;
1268 } else if ((*count_it)->isMemRef() &&
1269 !(*count_it)->memOpDone) {
1270 // Loads that have not been marked as executed still count
1271 // towards the total instructions.
1272 ++total_insts;
1273 }
1274 }
1275
1276 ++count_it;
1277 }
1278 }
1279
1280 return total_insts;
1281#else
1282 return numEntries - freeEntries;
1283#endif
1284}
1285
1286template <class Impl>
1287void
1288InstructionQueue<Impl>::dumpLists()
1289{
1290 for (int i = 0; i < Num_OpClasses; ++i) {
1291 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size());
1292
1293 cprintf("\n");
1294 }
1295
1296 cprintf("Non speculative list size: %i\n", nonSpecInsts.size());
1297
1298 NonSpecMapIt non_spec_it = nonSpecInsts.begin();
1299 NonSpecMapIt non_spec_end_it = nonSpecInsts.end();
1300
1301 cprintf("Non speculative list: ");
1302
1303 while (non_spec_it != non_spec_end_it) {
1304 cprintf("%#x [sn:%lli]", (*non_spec_it).second->readPC(),
1305 (*non_spec_it).second->seqNum);
1306 ++non_spec_it;
1307 }
1308
1309 cprintf("\n");
1310
1311 ListOrderIt list_order_it = listOrder.begin();
1312 ListOrderIt list_order_end_it = listOrder.end();
1313 int i = 1;
1314
1315 cprintf("List order: ");
1316
1317 while (list_order_it != list_order_end_it) {
1318 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType,
1319 (*list_order_it).oldestInst);
1320
1321 ++list_order_it;
1322 ++i;
1323 }
1324
1325 cprintf("\n");
1326}
1327
1328
1329template <class Impl>
1330void
1331InstructionQueue<Impl>::dumpInsts()
1332{
1333 for (int i = 0; i < numThreads; ++i) {
1334 int num = 0;
1335 int valid_num = 0;
1336 ListIt inst_list_it = instList[i].begin();
1337
1338 while (inst_list_it != instList[i].end())
1339 {
1340 cprintf("Instruction:%i\n",
1341 num);
1342 if (!(*inst_list_it)->isSquashed()) {
1343 if (!(*inst_list_it)->isIssued()) {
1344 ++valid_num;
1345 cprintf("Count:%i\n", valid_num);
1346 } else if ((*inst_list_it)->isMemRef() &&
1347 !(*inst_list_it)->memOpDone) {
1348 // Loads that have not been marked as executed
1349 // still count towards the total instructions.
1350 ++valid_num;
1351 cprintf("Count:%i\n", valid_num);
1352 }
1353 }
1354
1355 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
1356 "Issued:%i\nSquashed:%i\n",
1357 (*inst_list_it)->readPC(),
1358 (*inst_list_it)->seqNum,
1359 (*inst_list_it)->threadNumber,
1360 (*inst_list_it)->isIssued(),
1361 (*inst_list_it)->isSquashed());
1362
1363 if ((*inst_list_it)->isMemRef()) {
1364 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
1365 }
1366
1367 cprintf("\n");
1368
1369 inst_list_it++;
1370 ++num;
1371 }
1372 }
1373
1374 cprintf("Insts to Execute list:\n");
1375
1376 int num = 0;
1377 int valid_num = 0;
1378 ListIt inst_list_it = instsToExecute.begin();
1379
1380 while (inst_list_it != instsToExecute.end())
1381 {
1382 cprintf("Instruction:%i\n",
1383 num);
1384 if (!(*inst_list_it)->isSquashed()) {
1385 if (!(*inst_list_it)->isIssued()) {
1386 ++valid_num;
1387 cprintf("Count:%i\n", valid_num);
1388 } else if ((*inst_list_it)->isMemRef() &&
1389 !(*inst_list_it)->memOpDone) {
1390 // Loads that have not been marked as executed
1391 // still count towards the total instructions.
1392 ++valid_num;
1393 cprintf("Count:%i\n", valid_num);
1394 }
1395 }
1396
1397 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
1398 "Issued:%i\nSquashed:%i\n",
1399 (*inst_list_it)->readPC(),
1400 (*inst_list_it)->seqNum,
1401 (*inst_list_it)->threadNumber,
1402 (*inst_list_it)->isIssued(),
1403 (*inst_list_it)->isSquashed());
1404
1405 if ((*inst_list_it)->isMemRef()) {
1406 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
1407 }
1408
1409 cprintf("\n");
1410
1411 inst_list_it++;
1412 ++num;
1413 }
1414}
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