1/*
| 1/*
|
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
| 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
|
3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
| 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
| 27 * 28 * Authors: Kevin Lim
|
27 */ 28
| 29 */ 30
|
| 31// Todo: 32// Current ordering allows for 0 cycle added-to-scheduled. Could maybe fake 33// it; either do in reverse order, or have added instructions put into a 34// different ready queue that, in scheduleRreadyInsts(), gets put onto the 35// normal ready queue. This would however give only a one cycle delay, 36// but probably is more flexible to actually add in a delay parameter than 37// just running it backwards. 38
|
29#include <limits> 30#include <vector> 31 32#include "sim/root.hh" 33
| 39#include <limits> 40#include <vector> 41 42#include "sim/root.hh" 43
|
34#include "cpu/o3/fu_pool.hh"
| |
35#include "cpu/o3/inst_queue.hh" 36
| 44#include "cpu/o3/inst_queue.hh" 45
|
37using namespace std;
| 46// Either compile error or max int due to sign extension. 47// Hack to avoid compile warnings. 48const InstSeqNum MaxInstSeqNum = std::numeric_limits<InstSeqNum>::max();
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38 39template <class Impl>
| 49 50template <class Impl>
|
40InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 41 int fu_idx, 42 InstructionQueue<Impl> *iq_ptr) 43 : Event(&mainEventQueue, Stat_Event_Pri), 44 inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false)
| 51InstructionQueue<Impl>::InstructionQueue(Params ¶ms) 52 : memDepUnit(params), 53 numEntries(params.numIQEntries), 54 intWidth(params.executeIntWidth), 55 floatWidth(params.executeFloatWidth), 56 branchWidth(params.executeBranchWidth), 57 memoryWidth(params.executeMemoryWidth), 58 totalWidth(params.issueWidth), 59 numPhysIntRegs(params.numPhysIntRegs), 60 numPhysFloatRegs(params.numPhysFloatRegs), 61 commitToIEWDelay(params.commitToIEWDelay)
|
45{
| 62{
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46 this->setFlags(Event::AutoDelete); 47}
| 63 // Initialize the number of free IQ entries. 64 freeEntries = numEntries;
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48
| 65
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49template <class Impl> 50void 51InstructionQueue<Impl>::FUCompletion::process() 52{ 53 iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 54 inst = NULL; 55} 56 57 58template <class Impl> 59const char * 60InstructionQueue<Impl>::FUCompletion::description() 61{ 62 return "Functional unit completion event"; 63} 64 65template <class Impl> 66InstructionQueue<Impl>::InstructionQueue(Params *params) 67 : dcacheInterface(params->dcacheInterface), 68 fuPool(params->fuPool), 69 numEntries(params->numIQEntries), 70 totalWidth(params->issueWidth), 71 numPhysIntRegs(params->numPhysIntRegs), 72 numPhysFloatRegs(params->numPhysFloatRegs), 73 commitToIEWDelay(params->commitToIEWDelay) 74{ 75 assert(fuPool); 76 77 switchedOut = false; 78 79 numThreads = params->numberOfThreads; 80
| |
81 // Set the number of physical registers as the number of int + float 82 numPhysRegs = numPhysIntRegs + numPhysFloatRegs; 83
| 66 // Set the number of physical registers as the number of int + float 67 numPhysRegs = numPhysIntRegs + numPhysFloatRegs; 68
|
84 DPRINTF(IQ, "There are %i physical registers.\n", numPhysRegs);
| 69 DPRINTF(IQ, "IQ: There are %i physical registers.\n", numPhysRegs);
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85 86 //Create an entry for each physical register within the 87 //dependency graph.
| 70 71 //Create an entry for each physical register within the 72 //dependency graph.
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88 dependGraph.resize(numPhysRegs);
| 73 dependGraph = new DependencyEntry[numPhysRegs];
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89 90 // Resize the register scoreboard. 91 regScoreboard.resize(numPhysRegs); 92
| 74 75 // Resize the register scoreboard. 76 regScoreboard.resize(numPhysRegs); 77
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93 //Initialize Mem Dependence Units 94 for (int i = 0; i < numThreads; i++) { 95 memDepUnit[i].init(params,i); 96 memDepUnit[i].setIQ(this);
| 78 // Initialize all the head pointers to point to NULL, and all the 79 // entries as unready. 80 // Note that in actuality, the registers corresponding to the logical 81 // registers start off as ready. However this doesn't matter for the 82 // IQ as the instruction should have been correctly told if those 83 // registers are ready in rename. Thus it can all be initialized as 84 // unready. 85 for (int i = 0; i < numPhysRegs; ++i) 86 { 87 dependGraph[i].next = NULL; 88 dependGraph[i].inst = NULL; 89 regScoreboard[i] = false;
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97 } 98
| 90 } 91
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99 resetState(); 100 101 string policy = params->smtIQPolicy; 102 103 //Convert string to lowercase 104 std::transform(policy.begin(), policy.end(), policy.begin(), 105 (int(*)(int)) tolower); 106 107 //Figure out resource sharing policy 108 if (policy == "dynamic") { 109 iqPolicy = Dynamic; 110 111 //Set Max Entries to Total ROB Capacity 112 for (int i = 0; i < numThreads; i++) { 113 maxEntries[i] = numEntries; 114 } 115 116 } else if (policy == "partitioned") { 117 iqPolicy = Partitioned; 118 119 //@todo:make work if part_amt doesnt divide evenly. 120 int part_amt = numEntries / numThreads; 121 122 //Divide ROB up evenly 123 for (int i = 0; i < numThreads; i++) { 124 maxEntries[i] = part_amt; 125 } 126 127 DPRINTF(Fetch, "IQ sharing policy set to Partitioned:" 128 "%i entries per thread.\n",part_amt); 129 130 } else if (policy == "threshold") { 131 iqPolicy = Threshold; 132 133 double threshold = (double)params->smtIQThreshold / 100; 134 135 int thresholdIQ = (int)((double)threshold * numEntries); 136 137 //Divide up by threshold amount 138 for (int i = 0; i < numThreads; i++) { 139 maxEntries[i] = thresholdIQ; 140 } 141 142 DPRINTF(Fetch, "IQ sharing policy set to Threshold:" 143 "%i entries per thread.\n",thresholdIQ); 144 } else { 145 assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 146 "Partitioned, Threshold}"); 147 }
| |
148} 149 150template <class Impl>
| 92} 93 94template <class Impl>
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151InstructionQueue<Impl>::~InstructionQueue() 152{ 153 dependGraph.reset(); 154 cprintf("Nodes traversed: %i, removed: %i\n", 155 dependGraph.nodesTraversed, dependGraph.nodesRemoved); 156} 157 158template <class Impl> 159std::string 160InstructionQueue<Impl>::name() const 161{ 162 return cpu->name() + ".iq"; 163} 164 165template <class Impl>
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166void 167InstructionQueue<Impl>::regStats() 168{
| 95void 96InstructionQueue<Impl>::regStats() 97{
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169 using namespace Stats;
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170 iqInstsAdded 171 .name(name() + ".iqInstsAdded") 172 .desc("Number of instructions added to the IQ (excludes non-spec)") 173 .prereq(iqInstsAdded); 174 175 iqNonSpecInstsAdded 176 .name(name() + ".iqNonSpecInstsAdded") 177 .desc("Number of non-speculative instructions added to the IQ") 178 .prereq(iqNonSpecInstsAdded); 179
| 98 iqInstsAdded 99 .name(name() + ".iqInstsAdded") 100 .desc("Number of instructions added to the IQ (excludes non-spec)") 101 .prereq(iqInstsAdded); 102 103 iqNonSpecInstsAdded 104 .name(name() + ".iqNonSpecInstsAdded") 105 .desc("Number of non-speculative instructions added to the IQ") 106 .prereq(iqNonSpecInstsAdded); 107
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180 iqInstsIssued 181 .name(name() + ".iqInstsIssued") 182 .desc("Number of instructions issued") 183 .prereq(iqInstsIssued);
| 108// iqIntInstsAdded;
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184 185 iqIntInstsIssued 186 .name(name() + ".iqIntInstsIssued") 187 .desc("Number of integer instructions issued") 188 .prereq(iqIntInstsIssued); 189
| 109 110 iqIntInstsIssued 111 .name(name() + ".iqIntInstsIssued") 112 .desc("Number of integer instructions issued") 113 .prereq(iqIntInstsIssued); 114
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| 115// iqFloatInstsAdded; 116
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190 iqFloatInstsIssued 191 .name(name() + ".iqFloatInstsIssued") 192 .desc("Number of float instructions issued") 193 .prereq(iqFloatInstsIssued); 194
| 117 iqFloatInstsIssued 118 .name(name() + ".iqFloatInstsIssued") 119 .desc("Number of float instructions issued") 120 .prereq(iqFloatInstsIssued); 121
|
| 122// iqBranchInstsAdded; 123
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195 iqBranchInstsIssued 196 .name(name() + ".iqBranchInstsIssued") 197 .desc("Number of branch instructions issued") 198 .prereq(iqBranchInstsIssued); 199
| 124 iqBranchInstsIssued 125 .name(name() + ".iqBranchInstsIssued") 126 .desc("Number of branch instructions issued") 127 .prereq(iqBranchInstsIssued); 128
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| 129// iqMemInstsAdded; 130
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200 iqMemInstsIssued 201 .name(name() + ".iqMemInstsIssued") 202 .desc("Number of memory instructions issued") 203 .prereq(iqMemInstsIssued); 204
| 131 iqMemInstsIssued 132 .name(name() + ".iqMemInstsIssued") 133 .desc("Number of memory instructions issued") 134 .prereq(iqMemInstsIssued); 135
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| 136// iqMiscInstsAdded; 137
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205 iqMiscInstsIssued 206 .name(name() + ".iqMiscInstsIssued") 207 .desc("Number of miscellaneous instructions issued") 208 .prereq(iqMiscInstsIssued); 209 210 iqSquashedInstsIssued 211 .name(name() + ".iqSquashedInstsIssued") 212 .desc("Number of squashed instructions issued") 213 .prereq(iqSquashedInstsIssued); 214
| 138 iqMiscInstsIssued 139 .name(name() + ".iqMiscInstsIssued") 140 .desc("Number of miscellaneous instructions issued") 141 .prereq(iqMiscInstsIssued); 142 143 iqSquashedInstsIssued 144 .name(name() + ".iqSquashedInstsIssued") 145 .desc("Number of squashed instructions issued") 146 .prereq(iqSquashedInstsIssued); 147
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| 148 iqLoopSquashStalls 149 .name(name() + ".iqLoopSquashStalls") 150 .desc("Number of times issue loop had to restart due to squashed " 151 "inst; mainly for profiling") 152 .prereq(iqLoopSquashStalls); 153
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215 iqSquashedInstsExamined 216 .name(name() + ".iqSquashedInstsExamined") 217 .desc("Number of squashed instructions iterated over during squash;" 218 " mainly for profiling") 219 .prereq(iqSquashedInstsExamined); 220 221 iqSquashedOperandsExamined 222 .name(name() + ".iqSquashedOperandsExamined") 223 .desc("Number of squashed operands that are examined and possibly " 224 "removed from graph") 225 .prereq(iqSquashedOperandsExamined); 226 227 iqSquashedNonSpecRemoved 228 .name(name() + ".iqSquashedNonSpecRemoved") 229 .desc("Number of squashed non-spec instructions that were removed") 230 .prereq(iqSquashedNonSpecRemoved); 231
| 154 iqSquashedInstsExamined 155 .name(name() + ".iqSquashedInstsExamined") 156 .desc("Number of squashed instructions iterated over during squash;" 157 " mainly for profiling") 158 .prereq(iqSquashedInstsExamined); 159 160 iqSquashedOperandsExamined 161 .name(name() + ".iqSquashedOperandsExamined") 162 .desc("Number of squashed operands that are examined and possibly " 163 "removed from graph") 164 .prereq(iqSquashedOperandsExamined); 165 166 iqSquashedNonSpecRemoved 167 .name(name() + ".iqSquashedNonSpecRemoved") 168 .desc("Number of squashed non-spec instructions that were removed") 169 .prereq(iqSquashedNonSpecRemoved); 170
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232 queueResDist 233 .init(Num_OpClasses, 0, 99, 2) 234 .name(name() + ".IQ:residence:") 235 .desc("cycles from dispatch to issue") 236 .flags(total | pdf | cdf ) 237 ; 238 for (int i = 0; i < Num_OpClasses; ++i) { 239 queueResDist.subname(i, opClassStrings[i]); 240 } 241 numIssuedDist 242 .init(0,totalWidth,1) 243 .name(name() + ".ISSUE:issued_per_cycle") 244 .desc("Number of insts issued each cycle") 245 .flags(pdf) 246 ; 247/* 248 dist_unissued 249 .init(Num_OpClasses+2) 250 .name(name() + ".ISSUE:unissued_cause") 251 .desc("Reason ready instruction not issued") 252 .flags(pdf | dist) 253 ; 254 for (int i=0; i < (Num_OpClasses + 2); ++i) { 255 dist_unissued.subname(i, unissued_names[i]); 256 } 257*/ 258 statIssuedInstType 259 .init(numThreads,Num_OpClasses) 260 .name(name() + ".ISSUE:FU_type") 261 .desc("Type of FU issued") 262 .flags(total | pdf | dist) 263 ; 264 statIssuedInstType.ysubnames(opClassStrings); 265 266 // 267 // How long did instructions for a particular FU type wait prior to issue 268 // 269 270 issueDelayDist 271 .init(Num_OpClasses,0,99,2) 272 .name(name() + ".ISSUE:") 273 .desc("cycles from operands ready to issue") 274 .flags(pdf | cdf) 275 ; 276 277 for (int i=0; i<Num_OpClasses; ++i) { 278 stringstream subname; 279 subname << opClassStrings[i] << "_delay"; 280 issueDelayDist.subname(i, subname.str()); 281 } 282 283 issueRate 284 .name(name() + ".ISSUE:rate") 285 .desc("Inst issue rate") 286 .flags(total) 287 ; 288 issueRate = iqInstsIssued / cpu->numCycles; 289/* 290 issue_stores 291 .name(name() + ".ISSUE:stores") 292 .desc("Number of stores issued") 293 .flags(total) 294 ; 295 issue_stores = exe_refs - exe_loads; 296*/ 297/* 298 issue_op_rate 299 .name(name() + ".ISSUE:op_rate") 300 .desc("Operation issue rate") 301 .flags(total) 302 ; 303 issue_op_rate = issued_ops / numCycles; 304*/ 305 statFuBusy 306 .init(Num_OpClasses) 307 .name(name() + ".ISSUE:fu_full") 308 .desc("attempts to use FU when none available") 309 .flags(pdf | dist) 310 ; 311 for (int i=0; i < Num_OpClasses; ++i) { 312 statFuBusy.subname(i, opClassStrings[i]); 313 } 314 315 fuBusy 316 .init(numThreads) 317 .name(name() + ".ISSUE:fu_busy_cnt") 318 .desc("FU busy when requested") 319 .flags(total) 320 ; 321 322 fuBusyRate 323 .name(name() + ".ISSUE:fu_busy_rate") 324 .desc("FU busy rate (busy events/executed inst)") 325 .flags(total) 326 ; 327 fuBusyRate = fuBusy / iqInstsIssued; 328 329 for ( int i=0; i < numThreads; i++) { 330 // Tell mem dependence unit to reg stats as well. 331 memDepUnit[i].regStats(); 332 }
| 171 // Tell mem dependence unit to reg stats as well. 172 memDepUnit.regStats();
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333} 334 335template <class Impl> 336void
| 173} 174 175template <class Impl> 176void
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337InstructionQueue<Impl>::resetState()
| 177InstructionQueue<Impl>::setCPU(FullCPU *cpu_ptr)
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338{
| 178{
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339 //Initialize thread IQ counts 340 for (int i = 0; i <numThreads; i++) { 341 count[i] = 0; 342 instList[i].clear(); 343 }
| 179 cpu = cpu_ptr;
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344
| 180
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345 // Initialize the number of free IQ entries. 346 freeEntries = numEntries; 347 348 // Note that in actuality, the registers corresponding to the logical 349 // registers start off as ready. However this doesn't matter for the 350 // IQ as the instruction should have been correctly told if those 351 // registers are ready in rename. Thus it can all be initialized as 352 // unready. 353 for (int i = 0; i < numPhysRegs; ++i) { 354 regScoreboard[i] = false; 355 } 356 357 for (int i = 0; i < numThreads; ++i) { 358 squashedSeqNum[i] = 0; 359 } 360 361 for (int i = 0; i < Num_OpClasses; ++i) { 362 while (!readyInsts[i].empty()) 363 readyInsts[i].pop(); 364 queueOnList[i] = false; 365 readyIt[i] = listOrder.end(); 366 } 367 nonSpecInsts.clear(); 368 listOrder.clear();
| 181 tail = cpu->instList.begin();
|
369} 370 371template <class Impl> 372void
| 182} 183 184template <class Impl> 185void
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373InstructionQueue<Impl>::setActiveThreads(list<unsigned> *at_ptr)
| 186InstructionQueue<Impl>::setIssueToExecuteQueue( 187 TimeBuffer<IssueStruct> *i2e_ptr)
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374{
| 188{
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375 DPRINTF(IQ, "Setting active threads list pointer.\n"); 376 activeThreads = at_ptr; 377} 378 379template <class Impl> 380void 381InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 382{ 383 DPRINTF(IQ, "Set the issue to execute queue.\n");
| 189 DPRINTF(IQ, "IQ: Set the issue to execute queue.\n");
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384 issueToExecuteQueue = i2e_ptr; 385} 386 387template <class Impl> 388void 389InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 390{
| 190 issueToExecuteQueue = i2e_ptr; 191} 192 193template <class Impl> 194void 195InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 196{
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391 DPRINTF(IQ, "Set the time buffer.\n");
| 197 DPRINTF(IQ, "IQ: Set the time buffer.\n");
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392 timeBuffer = tb_ptr; 393 394 fromCommit = timeBuffer->getWire(-commitToIEWDelay); 395} 396 397template <class Impl>
| 198 timeBuffer = tb_ptr; 199 200 fromCommit = timeBuffer->getWire(-commitToIEWDelay); 201} 202 203template <class Impl>
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398void 399InstructionQueue<Impl>::switchOut() 400{ 401 resetState(); 402 dependGraph.reset(); 403 switchedOut = true; 404 for (int i = 0; i < numThreads; ++i) { 405 memDepUnit[i].switchOut(); 406 } 407} 408 409template <class Impl> 410void 411InstructionQueue<Impl>::takeOverFrom() 412{ 413 switchedOut = false; 414} 415 416template <class Impl> 417int 418InstructionQueue<Impl>::entryAmount(int num_threads) 419{ 420 if (iqPolicy == Partitioned) { 421 return numEntries / num_threads; 422 } else { 423 return 0; 424 } 425} 426 427 428template <class Impl> 429void 430InstructionQueue<Impl>::resetEntries() 431{ 432 if (iqPolicy != Dynamic || numThreads > 1) { 433 int active_threads = (*activeThreads).size(); 434 435 list<unsigned>::iterator threads = (*activeThreads).begin(); 436 list<unsigned>::iterator list_end = (*activeThreads).end(); 437 438 while (threads != list_end) { 439 if (iqPolicy == Partitioned) { 440 maxEntries[*threads++] = numEntries / active_threads; 441 } else if(iqPolicy == Threshold && active_threads == 1) { 442 maxEntries[*threads++] = numEntries; 443 } 444 } 445 } 446} 447 448template <class Impl>
| |
449unsigned 450InstructionQueue<Impl>::numFreeEntries() 451{ 452 return freeEntries; 453} 454
| 204unsigned 205InstructionQueue<Impl>::numFreeEntries() 206{ 207 return freeEntries; 208} 209
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455template <class Impl> 456unsigned 457InstructionQueue<Impl>::numFreeEntries(unsigned tid) 458{ 459 return maxEntries[tid] - count[tid]; 460} 461
| |
462// Might want to do something more complex if it knows how many instructions 463// will be issued this cycle. 464template <class Impl> 465bool 466InstructionQueue<Impl>::isFull() 467{ 468 if (freeEntries == 0) { 469 return(true); 470 } else { 471 return(false); 472 } 473} 474 475template <class Impl>
| 210// Might want to do something more complex if it knows how many instructions 211// will be issued this cycle. 212template <class Impl> 213bool 214InstructionQueue<Impl>::isFull() 215{ 216 if (freeEntries == 0) { 217 return(true); 218 } else { 219 return(false); 220 } 221} 222 223template <class Impl>
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476bool 477InstructionQueue<Impl>::isFull(unsigned tid) 478{ 479 if (numFreeEntries(tid) == 0) { 480 return(true); 481 } else { 482 return(false); 483 } 484} 485 486template <class Impl> 487bool 488InstructionQueue<Impl>::hasReadyInsts() 489{ 490 if (!listOrder.empty()) { 491 return true; 492 } 493 494 for (int i = 0; i < Num_OpClasses; ++i) { 495 if (!readyInsts[i].empty()) { 496 return true; 497 } 498 } 499 500 return false; 501} 502 503template <class Impl>
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504void 505InstructionQueue<Impl>::insert(DynInstPtr &new_inst) 506{ 507 // Make sure the instruction is valid 508 assert(new_inst); 509
| 224void 225InstructionQueue<Impl>::insert(DynInstPtr &new_inst) 226{ 227 // Make sure the instruction is valid 228 assert(new_inst); 229
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510 DPRINTF(IQ, "Adding instruction [sn:%lli] PC %#x to the IQ.\n", 511 new_inst->seqNum, new_inst->readPC());
| 230 DPRINTF(IQ, "IQ: Adding instruction PC %#x to the IQ.\n", 231 new_inst->readPC());
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512
| 232
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| 233 // Check if there are any free entries. Panic if there are none. 234 // Might want to have this return a fault in the future instead of 235 // panicing.
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513 assert(freeEntries != 0); 514
| 236 assert(freeEntries != 0); 237
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515 instList[new_inst->threadNumber].push_back(new_inst);
| 238 // If the IQ currently has nothing in it, then there's a possibility 239 // that the tail iterator is invalid (might have been pointing at an 240 // instruction that was retired). Reset the tail iterator. 241 if (freeEntries == numEntries) { 242 tail = cpu->instList.begin(); 243 }
|
516
| 244
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517 --freeEntries;
| 245 // Move the tail iterator. Instructions may not have been issued 246 // to the IQ, so we may have to increment the iterator more than once. 247 while ((*tail) != new_inst) { 248 tail++;
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518
| 249
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519 new_inst->setInIQ();
| 250 // Make sure the tail iterator points at something legal. 251 assert(tail != cpu->instList.end()); 252 }
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520
| 253
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| 254 255 // Decrease the number of free entries. 256 --freeEntries; 257
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521 // Look through its source registers (physical regs), and mark any 522 // dependencies. 523 addToDependents(new_inst); 524 525 // Have this instruction set itself as the producer of its destination 526 // register(s).
| 258 // Look through its source registers (physical regs), and mark any 259 // dependencies. 260 addToDependents(new_inst); 261 262 // Have this instruction set itself as the producer of its destination 263 // register(s).
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527 addToProducers(new_inst);
| 264 createDependency(new_inst);
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528
| 265
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| 266 // If it's a memory instruction, add it to the memory dependency 267 // unit.
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529 if (new_inst->isMemRef()) {
| 268 if (new_inst->isMemRef()) {
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530 memDepUnit[new_inst->threadNumber].insert(new_inst);
| 269 memDepUnit.insert(new_inst); 270 // Uh..forgot to look it up and put it on the proper dependency list 271 // if the instruction should not go yet.
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531 } else {
| 272 } else {
|
| 273 // If the instruction is ready then add it to the ready list.
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532 addIfReady(new_inst); 533 } 534 535 ++iqInstsAdded; 536
| 274 addIfReady(new_inst); 275 } 276 277 ++iqInstsAdded; 278
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537 count[new_inst->threadNumber]++; 538
| |
539 assert(freeEntries == (numEntries - countInsts())); 540} 541 542template <class Impl> 543void
| 279 assert(freeEntries == (numEntries - countInsts())); 280} 281 282template <class Impl> 283void
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544InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst)
| 284InstructionQueue::insertNonSpec(DynInstPtr &inst)
|
545{
| 285{
|
| 286 nonSpecInsts[inst->seqNum] = inst; 287
|
546 // @todo: Clean up this code; can do it by setting inst as unable 547 // to issue, then calling normal insert on the inst. 548
| 288 // @todo: Clean up this code; can do it by setting inst as unable 289 // to issue, then calling normal insert on the inst. 290
|
549 assert(new_inst);
| 291 // Make sure the instruction is valid 292 assert(inst);
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550
| 293
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551 nonSpecInsts[new_inst->seqNum] = new_inst;
| 294 DPRINTF(IQ, "IQ: Adding instruction PC %#x to the IQ.\n", 295 inst->readPC());
|
552
| 296
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553 DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %#x " 554 "to the IQ.\n", 555 new_inst->seqNum, new_inst->readPC()); 556
| 297 // Check if there are any free entries. Panic if there are none. 298 // Might want to have this return a fault in the future instead of 299 // panicing.
|
557 assert(freeEntries != 0); 558
| 300 assert(freeEntries != 0); 301
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559 instList[new_inst->threadNumber].push_back(new_inst);
| 302 // If the IQ currently has nothing in it, then there's a possibility 303 // that the tail iterator is invalid (might have been pointing at an 304 // instruction that was retired). Reset the tail iterator. 305 if (freeEntries == numEntries) { 306 tail = cpu->instList.begin(); 307 }
|
560
| 308
|
561 --freeEntries;
| 309 // Move the tail iterator. Instructions may not have been issued 310 // to the IQ, so we may have to increment the iterator more than once. 311 while ((*tail) != inst) { 312 tail++;
|
562
| 313
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563 new_inst->setInIQ();
| 314 // Make sure the tail iterator points at something legal. 315 assert(tail != cpu->instList.end()); 316 }
|
564
| 317
|
| 318 // Decrease the number of free entries. 319 --freeEntries; 320
|
565 // Have this instruction set itself as the producer of its destination 566 // register(s).
| 321 // Have this instruction set itself as the producer of its destination 322 // register(s).
|
567 addToProducers(new_inst);
| 323 createDependency(inst);
|
568 569 // If it's a memory instruction, add it to the memory dependency 570 // unit.
| 324 325 // If it's a memory instruction, add it to the memory dependency 326 // unit.
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571 if (new_inst->isMemRef()) { 572 memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst);
| 327 if (inst->isMemRef()) { 328 memDepUnit.insertNonSpec(inst);
|
573 } 574 575 ++iqNonSpecInstsAdded;
| 329 } 330 331 ++iqNonSpecInstsAdded;
|
576 577 count[new_inst->threadNumber]++; 578 579 assert(freeEntries == (numEntries - countInsts()));
| |
580} 581
| 332} 333
|
| 334// Slightly hack function to advance the tail iterator in the case that 335// the IEW stage issues an instruction that is not added to the IQ. This 336// is needed in case a long chain of such instructions occurs. 337// I don't think this is used anymore.
|
582template <class Impl> 583void
| 338template <class Impl> 339void
|
584InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst)
| 340InstructionQueue<Impl>::advanceTail(DynInstPtr &inst)
|
585{
| 341{
|
586 memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst);
| 342 // Make sure the instruction is valid 343 assert(inst);
|
587
| 344
|
588 insertNonSpec(barr_inst); 589}
| 345 DPRINTF(IQ, "IQ: Adding instruction PC %#x to the IQ.\n", 346 inst->readPC());
|
590
| 347
|
591template <class Impl> 592typename Impl::DynInstPtr 593InstructionQueue<Impl>::getInstToExecute() 594{ 595 assert(!instsToExecute.empty()); 596 DynInstPtr inst = instsToExecute.front(); 597 instsToExecute.pop_front(); 598 return inst;
| 348 // Check if there are any free entries. Panic if there are none. 349 // Might want to have this return a fault in the future instead of 350 // panicing. 351 assert(freeEntries != 0); 352 353 // If the IQ currently has nothing in it, then there's a possibility 354 // that the tail iterator is invalid (might have been pointing at an 355 // instruction that was retired). Reset the tail iterator. 356 if (freeEntries == numEntries) { 357 tail = cpu->instList.begin(); 358 } 359 360 // Move the tail iterator. Instructions may not have been issued 361 // to the IQ, so we may have to increment the iterator more than once. 362 while ((*tail) != inst) { 363 tail++; 364 365 // Make sure the tail iterator points at something legal. 366 assert(tail != cpu->instList.end()); 367 } 368 369 assert(freeEntries <= numEntries); 370 371 // Have this instruction set itself as the producer of its destination 372 // register(s). 373 createDependency(inst);
|
599} 600
| 374} 375
|
| 376// Need to make sure the number of float and integer instructions 377// issued does not exceed the total issue bandwidth. 378// @todo: Figure out a better way to remove the squashed items from the 379// lists. Checking the top item of each list to see if it's squashed 380// wastes time and forces jumps.
|
601template <class Impl> 602void
| 381template <class Impl> 382void
|
603InstructionQueue<Impl>::addToOrderList(OpClass op_class)
| 383InstructionQueue<Impl>::scheduleReadyInsts()
|
604{
| 384{
|
605 assert(!readyInsts[op_class].empty());
| 385 DPRINTF(IQ, "IQ: Attempting to schedule ready instructions from " 386 "the IQ.\n");
|
606
| 387
|
607 ListOrderEntry queue_entry;
| 388 int int_issued = 0; 389 int float_issued = 0; 390 int branch_issued = 0; 391 int memory_issued = 0; 392 int squashed_issued = 0; 393 int total_issued = 0;
|
608
| 394
|
609 queue_entry.queueType = op_class;
| 395 IssueStruct *i2e_info = issueToExecuteQueue->access(0);
|
610
| 396
|
611 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
| 397 bool insts_available = !readyBranchInsts.empty() || 398 !readyIntInsts.empty() || 399 !readyFloatInsts.empty() || 400 !memDepUnit.empty() || 401 !readyMiscInsts.empty() || 402 !squashedInsts.empty();
|
612
| 403
|
613 ListOrderIt list_it = listOrder.begin(); 614 ListOrderIt list_end_it = listOrder.end();
| 404 // Note: Requires a globally defined constant. 405 InstSeqNum oldest_inst = MaxInstSeqNum; 406 InstList list_with_oldest = None;
|
615
| 407
|
616 while (list_it != list_end_it) { 617 if ((*list_it).oldestInst > queue_entry.oldestInst) { 618 break; 619 }
| 408 // Temporary values. 409 DynInstPtr int_head_inst; 410 DynInstPtr float_head_inst; 411 DynInstPtr branch_head_inst; 412 DynInstPtr mem_head_inst; 413 DynInstPtr misc_head_inst; 414 DynInstPtr squashed_head_inst;
|
620
| 415
|
621 list_it++; 622 }
| 416 // Somewhat nasty code to look at all of the lists where issuable 417 // instructions are located, and choose the oldest instruction among 418 // those lists. Consider a rewrite in the future. 419 while (insts_available && total_issued < totalWidth) 420 { 421 // Set this to false. Each if-block is required to set it to true 422 // if there were instructions available this check. This will cause 423 // this loop to run once more than necessary, but avoids extra calls. 424 insts_available = false;
|
623
| 425
|
624 readyIt[op_class] = listOrder.insert(list_it, queue_entry); 625 queueOnList[op_class] = true; 626}
| 426 oldest_inst = MaxInstSeqNum;
|
627
| 427
|
628template <class Impl> 629void 630InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 631{ 632 // Get iterator of next item on the list 633 // Delete the original iterator 634 // Determine if the next item is either the end of the list or younger 635 // than the new instruction. If so, then add in a new iterator right here. 636 // If not, then move along. 637 ListOrderEntry queue_entry; 638 OpClass op_class = (*list_order_it).queueType; 639 ListOrderIt next_it = list_order_it;
| 428 list_with_oldest = None;
|
640
| 429
|
641 ++next_it;
| 430 if (!readyIntInsts.empty() && 431 int_issued < intWidth) {
|
642
| 432
|
643 queue_entry.queueType = op_class; 644 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
| 433 insts_available = true;
|
645
| 434
|
646 while (next_it != listOrder.end() && 647 (*next_it).oldestInst < queue_entry.oldestInst) { 648 ++next_it; 649 }
| 435 int_head_inst = readyIntInsts.top();
|
650
| 436
|
651 readyIt[op_class] = listOrder.insert(next_it, queue_entry); 652}
| 437 if (int_head_inst->isSquashed()) { 438 readyIntInsts.pop();
|
653
| 439
|
654template <class Impl> 655void 656InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 657{ 658 // The CPU could have been sleeping until this op completed (*extremely* 659 // long latency op). Wake it if it was. This may be overkill. 660 if (isSwitchedOut()) { 661 return; 662 }
| 440 ++iqLoopSquashStalls;
|
663
| 441
|
664 iewStage->wakeCPU();
| 442 continue; 443 }
|
665
| 444
|
666 if (fu_idx > -1) 667 fuPool->freeUnitNextCycle(fu_idx);
| 445 oldest_inst = int_head_inst->seqNum;
|
668
| 446
|
669 // @todo: Ensure that these FU Completions happen at the beginning 670 // of a cycle, otherwise they could add too many instructions to 671 // the queue. 672 // @todo: This could break if there's multiple multi-cycle ops 673 // finishing on this cycle. Maybe implement something like 674 // instToCommit in iew_impl.hh. 675 issueToExecuteQueue->access(0)->size++; 676 instsToExecute.push_back(inst); 677// int &size = issueToExecuteQueue->access(0)->size;
| 447 list_with_oldest = Int; 448 }
|
678
| 449
|
679// issueToExecuteQueue->access(0)->insts[size++] = inst; 680}
| 450 if (!readyFloatInsts.empty() && 451 float_issued < floatWidth) {
|
681
| 452
|
682// @todo: Figure out a better way to remove the squashed items from the 683// lists. Checking the top item of each list to see if it's squashed 684// wastes time and forces jumps. 685template <class Impl> 686void 687InstructionQueue<Impl>::scheduleReadyInsts() 688{ 689 DPRINTF(IQ, "Attempting to schedule ready instructions from " 690 "the IQ.\n");
| 453 insts_available = true;
|
691
| 454
|
692 IssueStruct *i2e_info = issueToExecuteQueue->access(0);
| 455 float_head_inst = readyFloatInsts.top();
|
693
| 456
|
694 // Have iterator to head of the list 695 // While I haven't exceeded bandwidth or reached the end of the list, 696 // Try to get a FU that can do what this op needs. 697 // If successful, change the oldestInst to the new top of the list, put 698 // the queue in the proper place in the list. 699 // Increment the iterator. 700 // This will avoid trying to schedule a certain op class if there are no 701 // FUs that handle it. 702 ListOrderIt order_it = listOrder.begin(); 703 ListOrderIt order_end_it = listOrder.end(); 704 int total_issued = 0;
| 457 if (float_head_inst->isSquashed()) { 458 readyFloatInsts.pop();
|
705
| 459
|
706 while (total_issued < totalWidth && 707 order_it != order_end_it) { 708 OpClass op_class = (*order_it).queueType;
| 460 ++iqLoopSquashStalls;
|
709
| 461
|
710 assert(!readyInsts[op_class].empty());
| 462 continue; 463 } else if (float_head_inst->seqNum < oldest_inst) { 464 oldest_inst = float_head_inst->seqNum;
|
711
| 465
|
712 DynInstPtr issuing_inst = readyInsts[op_class].top();
| 466 list_with_oldest = Float; 467 } 468 }
|
713
| 469
|
714 assert(issuing_inst->seqNum == (*order_it).oldestInst);
| 470 if (!readyBranchInsts.empty() && 471 branch_issued < branchWidth) {
|
715
| 472
|
716 if (issuing_inst->isSquashed()) { 717 readyInsts[op_class].pop();
| 473 insts_available = true;
|
718
| 474
|
719 if (!readyInsts[op_class].empty()) { 720 moveToYoungerInst(order_it); 721 } else { 722 readyIt[op_class] = listOrder.end(); 723 queueOnList[op_class] = false; 724 }
| 475 branch_head_inst = readyBranchInsts.top();
|
725
| 476
|
726 listOrder.erase(order_it++);
| 477 if (branch_head_inst->isSquashed()) { 478 readyBranchInsts.pop();
|
727
| 479
|
728 ++iqSquashedInstsIssued;
| 480 ++iqLoopSquashStalls;
|
729
| 481
|
730 continue;
| 482 continue; 483 } else if (branch_head_inst->seqNum < oldest_inst) { 484 oldest_inst = branch_head_inst->seqNum; 485 486 list_with_oldest = Branch; 487 } 488
|
731 } 732
| 489 } 490
|
733 int idx = -2; 734 int op_latency = 1; 735 int tid = issuing_inst->threadNumber;
| 491 if (!memDepUnit.empty() && 492 memory_issued < memoryWidth) {
|
736
| 493
|
737 if (op_class != No_OpClass) { 738 idx = fuPool->getUnit(op_class);
| 494 insts_available = true;
|
739
| 495
|
740 if (idx > -1) { 741 op_latency = fuPool->getOpLatency(op_class);
| 496 mem_head_inst = memDepUnit.top(); 497 498 if (mem_head_inst->isSquashed()) { 499 memDepUnit.pop(); 500 501 ++iqLoopSquashStalls; 502 503 continue; 504 } else if (mem_head_inst->seqNum < oldest_inst) { 505 oldest_inst = mem_head_inst->seqNum; 506 507 list_with_oldest = Memory;
|
742 } 743 } 744
| 508 } 509 } 510
|
745 if (idx == -2 || idx != -1) { 746 if (op_latency == 1) { 747// i2e_info->insts[exec_queue_slot++] = issuing_inst; 748 i2e_info->size++; 749 instsToExecute.push_back(issuing_inst);
| 511 if (!readyMiscInsts.empty()) {
|
750
| 512
|
751 // Add the FU onto the list of FU's to be freed next 752 // cycle if we used one. 753 if (idx >= 0) 754 fuPool->freeUnitNextCycle(idx); 755 } else { 756 int issue_latency = fuPool->getIssueLatency(op_class); 757 // Generate completion event for the FU 758 FUCompletion *execution = new FUCompletion(issuing_inst, 759 idx, this);
| 513 insts_available = true;
|
760
| 514
|
761 execution->schedule(curTick + cpu->cycles(issue_latency - 1));
| 515 misc_head_inst = readyMiscInsts.top();
|
762
| 516
|
763 // @todo: Enforce that issue_latency == 1 or op_latency 764 if (issue_latency > 1) { 765 execution->setFreeFU(); 766 } else { 767 // @todo: Not sure I'm accounting for the 768 // multi-cycle op in a pipelined FU properly, or 769 // the number of instructions issued in one cycle. 770// i2e_info->insts[exec_queue_slot++] = issuing_inst; 771// i2e_info->size++;
| 517 if (misc_head_inst->isSquashed()) { 518 readyMiscInsts.pop();
|
772
| 519
|
773 // Add the FU onto the list of FU's to be freed next cycle. 774 fuPool->freeUnitNextCycle(idx); 775 }
| 520 ++iqLoopSquashStalls; 521 522 continue; 523 } else if (misc_head_inst->seqNum < oldest_inst) { 524 oldest_inst = misc_head_inst->seqNum; 525 526 list_with_oldest = Misc;
|
776 }
| 527 }
|
| 528 }
|
777
| 529
|
778 DPRINTF(IQ, "Thread %i: Issuing instruction PC %#x " 779 "[sn:%lli]\n", 780 tid, issuing_inst->readPC(), 781 issuing_inst->seqNum);
| 530 if (!squashedInsts.empty()) {
|
782
| 531
|
783 readyInsts[op_class].pop();
| 532 insts_available = true;
|
784
| 533
|
785 if (!readyInsts[op_class].empty()) { 786 moveToYoungerInst(order_it); 787 } else { 788 readyIt[op_class] = listOrder.end(); 789 queueOnList[op_class] = false;
| 534 squashed_head_inst = squashedInsts.top(); 535 536 if (squashed_head_inst->seqNum < oldest_inst) { 537 list_with_oldest = Squashed;
|
790 } 791
| 538 } 539
|
792 issuing_inst->setIssued(); 793 ++total_issued;
| 540 }
|
794
| 541
|
795 if (!issuing_inst->isMemRef()) { 796 // Memory instructions can not be freed from the IQ until they 797 // complete. 798 ++freeEntries; 799 count[tid]--; 800 issuing_inst->removeInIQ(); 801 } else { 802 memDepUnit[tid].issue(issuing_inst); 803 }
| 542 DynInstPtr issuing_inst = NULL;
|
804
| 543
|
805 listOrder.erase(order_it++); 806 statIssuedInstType[tid][op_class]++; 807 } else { 808 statFuBusy[op_class]++; 809 fuBusy[tid]++; 810 ++order_it;
| 544 switch (list_with_oldest) { 545 case None: 546 DPRINTF(IQ, "IQ: Not able to schedule any instructions. Issuing " 547 "inst is %#x.\n", issuing_inst); 548 break; 549 550 case Int: 551 issuing_inst = int_head_inst; 552 readyIntInsts.pop(); 553 ++int_issued; 554 DPRINTF(IQ, "IQ: Issuing integer instruction PC %#x.\n", 555 issuing_inst->readPC()); 556 break; 557 558 case Float: 559 issuing_inst = float_head_inst; 560 readyFloatInsts.pop(); 561 ++float_issued; 562 DPRINTF(IQ, "IQ: Issuing float instruction PC %#x.\n", 563 issuing_inst->readPC()); 564 break; 565 566 case Branch: 567 issuing_inst = branch_head_inst; 568 readyBranchInsts.pop(); 569 ++branch_issued; 570 DPRINTF(IQ, "IQ: Issuing branch instruction PC %#x.\n", 571 issuing_inst->readPC()); 572 break; 573 574 case Memory: 575 issuing_inst = mem_head_inst; 576 577 memDepUnit.pop(); 578 ++memory_issued; 579 DPRINTF(IQ, "IQ: Issuing memory instruction PC %#x.\n", 580 issuing_inst->readPC()); 581 break; 582 583 case Misc: 584 issuing_inst = misc_head_inst; 585 readyMiscInsts.pop(); 586 587 ++iqMiscInstsIssued; 588 589 DPRINTF(IQ, "IQ: Issuing a miscellaneous instruction PC %#x.\n", 590 issuing_inst->readPC()); 591 break; 592 593 case Squashed: 594 assert(0 && "Squashed insts should not issue any more!"); 595 squashedInsts.pop(); 596 // Set the squashed instruction as able to commit so that commit 597 // can just drop it from the ROB. This is a bit faked. 598 ++squashed_issued; 599 ++freeEntries; 600 601 DPRINTF(IQ, "IQ: Issuing squashed instruction PC %#x.\n", 602 squashed_head_inst->readPC()); 603 break;
|
811 }
| 604 }
|
812 }
| |
813
| 605
|
814 numIssuedDist.sample(total_issued); 815 iqInstsIssued+= total_issued;
| 606 if (list_with_oldest != None && list_with_oldest != Squashed) { 607 i2e_info->insts[total_issued] = issuing_inst; 608 i2e_info->size++;
|
816
| 609
|
817 if (total_issued) { 818 cpu->activityThisCycle(); 819 } else { 820 DPRINTF(IQ, "Not able to schedule any instructions.\n");
| 610 issuing_inst->setIssued(); 611 612 ++freeEntries; 613 ++total_issued; 614 } 615 616 assert(freeEntries == (numEntries - countInsts()));
|
821 }
| 617 }
|
| 618 619 iqIntInstsIssued += int_issued; 620 iqFloatInstsIssued += float_issued; 621 iqBranchInstsIssued += branch_issued; 622 iqMemInstsIssued += memory_issued; 623 iqSquashedInstsIssued += squashed_issued;
|
822} 823 824template <class Impl> 825void 826InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 827{
| 624} 625 626template <class Impl> 627void 628InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 629{
|
828 DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 829 "to execute.\n", inst);
| 630 DPRINTF(IQ, "IQ: Marking nonspeculative instruction with sequence " 631 "number %i as ready to execute.\n", inst);
|
830
| 632
|
831 NonSpecMapIt inst_it = nonSpecInsts.find(inst);
| 633 non_spec_it_t inst_it = nonSpecInsts.find(inst);
|
832 833 assert(inst_it != nonSpecInsts.end()); 834
| 634 635 assert(inst_it != nonSpecInsts.end()); 636
|
835 unsigned tid = (*inst_it).second->threadNumber; 836
| 637 // Mark this instruction as ready to issue.
|
837 (*inst_it).second->setCanIssue(); 838
| 638 (*inst_it).second->setCanIssue(); 639
|
| 640 // Now schedule the instruction.
|
839 if (!(*inst_it).second->isMemRef()) { 840 addIfReady((*inst_it).second); 841 } else {
| 641 if (!(*inst_it).second->isMemRef()) { 642 addIfReady((*inst_it).second); 643 } else {
|
842 memDepUnit[tid].nonSpecInstReady((*inst_it).second);
| 644 memDepUnit.nonSpecInstReady((*inst_it).second);
|
843 } 844
| 645 } 646
|
845 (*inst_it).second = NULL; 846
| |
847 nonSpecInsts.erase(inst_it); 848} 849 850template <class Impl> 851void
| 647 nonSpecInsts.erase(inst_it); 648} 649 650template <class Impl> 651void
|
852InstructionQueue<Impl>::commit(const InstSeqNum &inst, unsigned tid) 853{ 854 DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 855 tid,inst); 856 857 ListIt iq_it = instList[tid].begin(); 858 859 while (iq_it != instList[tid].end() && 860 (*iq_it)->seqNum <= inst) { 861 ++iq_it; 862 instList[tid].pop_front(); 863 } 864 865 assert(freeEntries == (numEntries - countInsts())); 866} 867 868template <class Impl> 869int
| |
870InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 871{
| 652InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 653{
|
872 int dependents = 0;
| 654 DPRINTF(IQ, "IQ: Waking dependents of completed instruction.\n"); 655 //Look at the physical destination register of the DynInst 656 //and look it up on the dependency graph. Then mark as ready 657 //any instructions within the instruction queue. 658 DependencyEntry *curr;
|
873
| 659
|
874 DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 875 876 assert(!completed_inst->isSquashed()); 877
| |
878 // Tell the memory dependence unit to wake any dependents on this
| 660 // Tell the memory dependence unit to wake any dependents on this
|
879 // instruction if it is a memory instruction. Also complete the memory 880 // instruction at this point since we know it executed without issues. 881 // @todo: Might want to rename "completeMemInst" to something that 882 // indicates that it won't need to be replayed, and call this 883 // earlier. Might not be a big deal.
| 661 // instruction if it is a memory instruction. 662
|
884 if (completed_inst->isMemRef()) {
| 663 if (completed_inst->isMemRef()) {
|
885 memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 886 completeMemInst(completed_inst); 887 } else if (completed_inst->isMemBarrier() || 888 completed_inst->isWriteBarrier()) { 889 memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst);
| 664 memDepUnit.wakeDependents(completed_inst);
|
890 } 891 892 for (int dest_reg_idx = 0; 893 dest_reg_idx < completed_inst->numDestRegs(); 894 dest_reg_idx++) 895 { 896 PhysRegIndex dest_reg = 897 completed_inst->renamedDestRegIdx(dest_reg_idx); 898 899 // Special case of uniq or control registers. They are not 900 // handled by the IQ and thus have no dependency graph entry. 901 // @todo Figure out a cleaner way to handle this. 902 if (dest_reg >= numPhysRegs) { 903 continue; 904 } 905
| 665 } 666 667 for (int dest_reg_idx = 0; 668 dest_reg_idx < completed_inst->numDestRegs(); 669 dest_reg_idx++) 670 { 671 PhysRegIndex dest_reg = 672 completed_inst->renamedDestRegIdx(dest_reg_idx); 673 674 // Special case of uniq or control registers. They are not 675 // handled by the IQ and thus have no dependency graph entry. 676 // @todo Figure out a cleaner way to handle this. 677 if (dest_reg >= numPhysRegs) { 678 continue; 679 } 680
|
906 DPRINTF(IQ, "Waking any dependents on register %i.\n",
| 681 DPRINTF(IQ, "IQ: Waking any dependents on register %i.\n",
|
907 (int) dest_reg); 908
| 682 (int) dest_reg); 683
|
909 //Go through the dependency chain, marking the registers as 910 //ready within the waiting instructions. 911 DynInstPtr dep_inst = dependGraph.pop(dest_reg);
| 684 //Maybe abstract this part into a function. 685 //Go through the dependency chain, marking the registers as ready 686 //within the waiting instructions. 687 while (dependGraph[dest_reg].next) {
|
912
| 688
|
913 while (dep_inst) { 914 DPRINTF(IQ, "Waking up a dependent instruction, PC%#x.\n", 915 dep_inst->readPC());
| 689 curr = dependGraph[dest_reg].next;
|
916
| 690
|
| 691 DPRINTF(IQ, "IQ: Waking up a dependent instruction, PC%#x.\n", 692 curr->inst->readPC()); 693
|
917 // Might want to give more information to the instruction
| 694 // Might want to give more information to the instruction
|
918 // so that it knows which of its source registers is 919 // ready. However that would mean that the dependency 920 // graph entries would need to hold the src_reg_idx. 921 dep_inst->markSrcRegReady();
| 695 // so that it knows which of its source registers is ready. 696 // However that would mean that the dependency graph entries 697 // would need to hold the src_reg_idx. 698 curr->inst->markSrcRegReady();
|
922
| 699
|
923 addIfReady(dep_inst);
| 700 addIfReady(curr->inst);
|
924
| 701
|
925 dep_inst = dependGraph.pop(dest_reg);
| 702 dependGraph[dest_reg].next = curr->next;
|
926
| 703
|
927 ++dependents;
| 704 DependencyEntry::mem_alloc_counter--; 705 706 curr->inst = NULL; 707 708 delete curr;
|
928 } 929
| 709 } 710
|
930 // Reset the head node now that all of its dependents have 931 // been woken up. 932 assert(dependGraph.empty(dest_reg)); 933 dependGraph.clearInst(dest_reg);
| 711 // Reset the head node now that all of its dependents have been woken 712 // up. 713 dependGraph[dest_reg].next = NULL; 714 dependGraph[dest_reg].inst = NULL;
|
934 935 // Mark the scoreboard as having that register ready. 936 regScoreboard[dest_reg] = true; 937 }
| 715 716 // Mark the scoreboard as having that register ready. 717 regScoreboard[dest_reg] = true; 718 }
|
938 return dependents;
| |
939} 940 941template <class Impl> 942void
| 719} 720 721template <class Impl> 722void
|
943InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 944{ 945 OpClass op_class = ready_inst->opClass(); 946 947 readyInsts[op_class].push(ready_inst); 948 949 // Will need to reorder the list if either a queue is not on the list, 950 // or it has an older instruction than last time. 951 if (!queueOnList[op_class]) { 952 addToOrderList(op_class); 953 } else if (readyInsts[op_class].top()->seqNum < 954 (*readyIt[op_class]).oldestInst) { 955 listOrder.erase(readyIt[op_class]); 956 addToOrderList(op_class); 957 } 958 959 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 960 "the ready list, PC %#x opclass:%i [sn:%lli].\n", 961 ready_inst->readPC(), op_class, ready_inst->seqNum); 962} 963 964template <class Impl> 965void 966InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 967{ 968 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 969} 970 971template <class Impl> 972void 973InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 974{ 975 memDepUnit[replay_inst->threadNumber].replay(replay_inst); 976} 977 978template <class Impl> 979void 980InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 981{ 982 int tid = completed_inst->threadNumber; 983 984 DPRINTF(IQ, "Completing mem instruction PC:%#x [sn:%lli]\n", 985 completed_inst->readPC(), completed_inst->seqNum); 986 987 ++freeEntries; 988 989 completed_inst->memOpDone = true; 990 991 memDepUnit[tid].completed(completed_inst); 992 993 count[tid]--; 994} 995 996template <class Impl> 997void
| |
998InstructionQueue<Impl>::violation(DynInstPtr &store, 999 DynInstPtr &faulting_load) 1000{
| 723InstructionQueue<Impl>::violation(DynInstPtr &store, 724 DynInstPtr &faulting_load) 725{
|
1001 memDepUnit[store->threadNumber].violation(store, faulting_load);
| 726 memDepUnit.violation(store, faulting_load);
|
1002} 1003 1004template <class Impl> 1005void
| 727} 728 729template <class Impl> 730void
|
1006InstructionQueue<Impl>::squash(unsigned tid)
| 731InstructionQueue::squash()
|
1007{
| 732{
|
1008 DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 1009 "the IQ.\n", tid);
| 733 DPRINTF(IQ, "IQ: Starting to squash instructions in the IQ.\n");
|
1010 1011 // Read instruction sequence number of last instruction out of the 1012 // time buffer.
| 734 735 // Read instruction sequence number of last instruction out of the 736 // time buffer.
|
1013 squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
| 737 squashedSeqNum = fromCommit->commitInfo.doneSeqNum;
|
1014
| 738
|
| 739 // Setup the squash iterator to point to the tail. 740 squashIt = tail; 741
|
1015 // Call doSquash if there are insts in the IQ
| 742 // Call doSquash if there are insts in the IQ
|
1016 if (count[tid] > 0) { 1017 doSquash(tid);
| 743 if (freeEntries != numEntries) { 744 doSquash();
|
1018 } 1019 1020 // Also tell the memory dependence unit to squash.
| 745 } 746 747 // Also tell the memory dependence unit to squash.
|
1021 memDepUnit[tid].squash(squashedSeqNum[tid], tid);
| 748 memDepUnit.squash(squashedSeqNum);
|
1022} 1023 1024template <class Impl> 1025void
| 749} 750 751template <class Impl> 752void
|
1026InstructionQueue<Impl>::doSquash(unsigned tid)
| 753InstructionQueue::doSquash()
|
1027{
| 754{
|
1028 // Start at the tail. 1029 ListIt squash_it = instList[tid].end(); 1030 --squash_it;
| 755 // Make sure the squash iterator isn't pointing to nothing. 756 assert(squashIt != cpu->instList.end()); 757 // Make sure the squashed sequence number is valid. 758 assert(squashedSeqNum != 0);
|
1031
| 759
|
1032 DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 1033 tid, squashedSeqNum[tid]);
| 760 DPRINTF(IQ, "IQ: Squashing instructions in the IQ.\n");
|
1034 1035 // Squash any instructions younger than the squashed sequence number 1036 // given.
| 761 762 // Squash any instructions younger than the squashed sequence number 763 // given.
|
1037 while (squash_it != instList[tid].end() && 1038 (*squash_it)->seqNum > squashedSeqNum[tid]) {
| 764 while ((*squashIt)->seqNum > squashedSeqNum) { 765 DynInstPtr squashed_inst = (*squashIt);
|
1039
| 766
|
1040 DynInstPtr squashed_inst = (*squash_it); 1041
| |
1042 // Only handle the instruction if it actually is in the IQ and 1043 // hasn't already been squashed in the IQ.
| 767 // Only handle the instruction if it actually is in the IQ and 768 // hasn't already been squashed in the IQ.
|
1044 if (squashed_inst->threadNumber != tid || 1045 squashed_inst->isSquashedInIQ()) { 1046 --squash_it; 1047 continue; 1048 }
| 769 if (!squashed_inst->isIssued() && 770 !squashed_inst->isSquashedInIQ()) {
|
1049
| 771
|
1050 if (!squashed_inst->isIssued() || 1051 (squashed_inst->isMemRef() && 1052 !squashed_inst->memOpDone)) { 1053
| |
1054 // Remove the instruction from the dependency list.
| 772 // Remove the instruction from the dependency list.
|
1055 if (!squashed_inst->isNonSpeculative() && 1056 !squashed_inst->isStoreConditional() && 1057 !squashed_inst->isMemBarrier() && 1058 !squashed_inst->isWriteBarrier()) {
| 773 // Hack for now: These below don't add themselves to the 774 // dependency list, so don't try to remove them. 775 if (!squashed_inst->isNonSpeculative()/* && 776 !squashed_inst->isStore()*/ 777 ) {
|
1059 1060 for (int src_reg_idx = 0; 1061 src_reg_idx < squashed_inst->numSrcRegs(); 1062 src_reg_idx++) 1063 { 1064 PhysRegIndex src_reg = 1065 squashed_inst->renamedSrcRegIdx(src_reg_idx); 1066
| 778 779 for (int src_reg_idx = 0; 780 src_reg_idx < squashed_inst->numSrcRegs(); 781 src_reg_idx++) 782 { 783 PhysRegIndex src_reg = 784 squashed_inst->renamedSrcRegIdx(src_reg_idx); 785
|
1067 // Only remove it from the dependency graph if it 1068 // was placed there in the first place. 1069 1070 // Instead of doing a linked list traversal, we 1071 // can just remove these squashed instructions 1072 // either at issue time, or when the register is 1073 // overwritten. The only downside to this is it 1074 // leaves more room for error. 1075
| 786 // Only remove it from the dependency graph if it was 787 // placed there in the first place. 788 // HACK: This assumes that instructions woken up from the 789 // dependency chain aren't informed that a specific src 790 // register has become ready. This may not always be true 791 // in the future.
|
1076 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 1077 src_reg < numPhysRegs) {
| 792 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 793 src_reg < numPhysRegs) {
|
1078 dependGraph.remove(src_reg, squashed_inst);
| 794 dependGraph[src_reg].remove(squashed_inst);
|
1079 } 1080
| 795 } 796
|
1081
| |
1082 ++iqSquashedOperandsExamined; 1083 }
| 797 ++iqSquashedOperandsExamined; 798 }
|
| 799 800 // Might want to remove producers as well.
|
1084 } else {
| 801 } else {
|
1085 NonSpecMapIt ns_inst_it = 1086 nonSpecInsts.find(squashed_inst->seqNum); 1087 assert(ns_inst_it != nonSpecInsts.end());
| 802 nonSpecInsts[squashed_inst->seqNum] = NULL;
|
1088
| 803
|
1089 (*ns_inst_it).second = NULL;
| 804 nonSpecInsts.erase(squashed_inst->seqNum);
|
1090
| 805
|
1091 nonSpecInsts.erase(ns_inst_it); 1092
| |
1093 ++iqSquashedNonSpecRemoved; 1094 } 1095 1096 // Might want to also clear out the head of the dependency graph. 1097 1098 // Mark it as squashed within the IQ. 1099 squashed_inst->setSquashedInIQ(); 1100
| 806 ++iqSquashedNonSpecRemoved; 807 } 808 809 // Might want to also clear out the head of the dependency graph. 810 811 // Mark it as squashed within the IQ. 812 squashed_inst->setSquashedInIQ(); 813
|
1101 // @todo: Remove this hack where several statuses are set so the 1102 // inst will flow through the rest of the pipeline.
| 814// squashedInsts.push(squashed_inst);
|
1103 squashed_inst->setIssued(); 1104 squashed_inst->setCanCommit();
| 815 squashed_inst->setIssued(); 816 squashed_inst->setCanCommit();
|
1105 squashed_inst->removeInIQ();
| |
1106
| 817
|
1107 //Update Thread IQ Count 1108 count[squashed_inst->threadNumber]--; 1109
| |
1110 ++freeEntries; 1111
| 818 ++freeEntries; 819
|
1112 DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x " 1113 "squashed.\n", 1114 tid, squashed_inst->seqNum, squashed_inst->readPC());
| 820 DPRINTF(IQ, "IQ: Instruction PC %#x squashed.\n", 821 squashed_inst->readPC());
|
1115 } 1116
| 822 } 823
|
1117 instList[tid].erase(squash_it--);
| 824 --squashIt;
|
1118 ++iqSquashedInstsExamined; 1119 }
| 825 ++iqSquashedInstsExamined; 826 }
|
| 827 828 assert(freeEntries <= numEntries); 829 830 if (freeEntries == numEntries) { 831 tail = cpu->instList.end(); 832 } 833
|
1120} 1121 1122template <class Impl>
| 834} 835 836template <class Impl>
|
| 837void 838InstructionQueue<Impl>::stopSquash() 839{ 840 // Clear up the squash variables to ensure that squashing doesn't 841 // get called improperly. 842 squashedSeqNum = 0; 843 844 squashIt = cpu->instList.end(); 845} 846 847template <class Impl> 848void 849InstructionQueue<Impl>::DependencyEntry::insert(DynInstPtr &new_inst) 850{ 851 //Add this new, dependent instruction at the head of the dependency 852 //chain. 853 854 // First create the entry that will be added to the head of the 855 // dependency chain. 856 DependencyEntry *new_entry = new DependencyEntry; 857 new_entry->next = this->next; 858 new_entry->inst = new_inst; 859 860 // Then actually add it to the chain. 861 this->next = new_entry; 862 863 ++mem_alloc_counter; 864} 865 866template <class Impl> 867void 868InstructionQueue<Impl>::DependencyEntry::remove(DynInstPtr &inst_to_remove) 869{ 870 DependencyEntry *prev = this; 871 DependencyEntry *curr = this->next; 872 873 // Make sure curr isn't NULL. Because this instruction is being 874 // removed from a dependency list, it must have been placed there at 875 // an earlier time. The dependency chain should not be empty, 876 // unless the instruction dependent upon it is already ready. 877 if (curr == NULL) { 878 return; 879 } 880 881 // Find the instruction to remove within the dependency linked list. 882 while(curr->inst != inst_to_remove) 883 { 884 prev = curr; 885 curr = curr->next; 886 887 assert(curr != NULL); 888 } 889 890 // Now remove this instruction from the list. 891 prev->next = curr->next; 892 893 --mem_alloc_counter; 894 895 // Could push this off to the destructor of DependencyEntry 896 curr->inst = NULL; 897 898 delete curr; 899} 900 901template <class Impl>
|
1123bool 1124InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 1125{ 1126 // Loop through the instruction's source registers, adding 1127 // them to the dependency list if they are not ready. 1128 int8_t total_src_regs = new_inst->numSrcRegs(); 1129 bool return_val = false; 1130 1131 for (int src_reg_idx = 0; 1132 src_reg_idx < total_src_regs; 1133 src_reg_idx++) 1134 { 1135 // Only add it to the dependency graph if it's not ready. 1136 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 1137 PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 1138 1139 // Check the IQ's scoreboard to make sure the register 1140 // hasn't become ready while the instruction was in flight 1141 // between stages. Only if it really isn't ready should 1142 // it be added to the dependency graph. 1143 if (src_reg >= numPhysRegs) { 1144 continue; 1145 } else if (regScoreboard[src_reg] == false) {
| 902bool 903InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 904{ 905 // Loop through the instruction's source registers, adding 906 // them to the dependency list if they are not ready. 907 int8_t total_src_regs = new_inst->numSrcRegs(); 908 bool return_val = false; 909 910 for (int src_reg_idx = 0; 911 src_reg_idx < total_src_regs; 912 src_reg_idx++) 913 { 914 // Only add it to the dependency graph if it's not ready. 915 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 916 PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 917 918 // Check the IQ's scoreboard to make sure the register 919 // hasn't become ready while the instruction was in flight 920 // between stages. Only if it really isn't ready should 921 // it be added to the dependency graph. 922 if (src_reg >= numPhysRegs) { 923 continue; 924 } else if (regScoreboard[src_reg] == false) {
|
1146 DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
| 925 DPRINTF(IQ, "IQ: Instruction PC %#x has src reg %i that "
|
1147 "is being added to the dependency chain.\n", 1148 new_inst->readPC(), src_reg); 1149
| 926 "is being added to the dependency chain.\n", 927 new_inst->readPC(), src_reg); 928
|
1150 dependGraph.insert(src_reg, new_inst);
| 929 dependGraph[src_reg].insert(new_inst);
|
1151 1152 // Change the return value to indicate that something 1153 // was added to the dependency graph. 1154 return_val = true; 1155 } else {
| 930 931 // Change the return value to indicate that something 932 // was added to the dependency graph. 933 return_val = true; 934 } else {
|
1156 DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
| 935 DPRINTF(IQ, "IQ: Instruction PC %#x has src reg %i that "
|
1157 "became ready before it reached the IQ.\n", 1158 new_inst->readPC(), src_reg); 1159 // Mark a register ready within the instruction.
| 936 "became ready before it reached the IQ.\n", 937 new_inst->readPC(), src_reg); 938 // Mark a register ready within the instruction.
|
1160 new_inst->markSrcRegReady(src_reg_idx);
| 939 new_inst->markSrcRegReady();
|
1161 } 1162 } 1163 } 1164 1165 return return_val; 1166} 1167 1168template <class Impl> 1169void
| 940 } 941 } 942 } 943 944 return return_val; 945} 946 947template <class Impl> 948void
|
1170InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst)
| 949InstructionQueue<Impl>::createDependency(DynInstPtr &new_inst)
|
1171{
| 950{
|
1172 // Nothing really needs to be marked when an instruction becomes 1173 // the producer of a register's value, but for convenience a ptr 1174 // to the producing instruction will be placed in the head node of 1175 // the dependency links.
| 951 //Actually nothing really needs to be marked when an 952 //instruction becomes the producer of a register's value, 953 //but for convenience a ptr to the producing instruction will 954 //be placed in the head node of the dependency links.
|
1176 int8_t total_dest_regs = new_inst->numDestRegs(); 1177 1178 for (int dest_reg_idx = 0; 1179 dest_reg_idx < total_dest_regs; 1180 dest_reg_idx++) 1181 { 1182 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 1183 1184 // Instructions that use the misc regs will have a reg number 1185 // higher than the normal physical registers. In this case these 1186 // registers are not renamed, and there is no need to track 1187 // dependencies as these instructions must be executed at commit. 1188 if (dest_reg >= numPhysRegs) { 1189 continue; 1190 } 1191
| 955 int8_t total_dest_regs = new_inst->numDestRegs(); 956 957 for (int dest_reg_idx = 0; 958 dest_reg_idx < total_dest_regs; 959 dest_reg_idx++) 960 { 961 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 962 963 // Instructions that use the misc regs will have a reg number 964 // higher than the normal physical registers. In this case these 965 // registers are not renamed, and there is no need to track 966 // dependencies as these instructions must be executed at commit. 967 if (dest_reg >= numPhysRegs) { 968 continue; 969 } 970
|
1192 if (!dependGraph.empty(dest_reg)) { 1193 dependGraph.dump(); 1194 panic("Dependency graph %i not empty!", dest_reg);
| 971 dependGraph[dest_reg].inst = new_inst; 972 973 if (dependGraph[dest_reg].next) { 974 dumpDependGraph(); 975 panic("IQ: Dependency graph not empty!");
|
1195 } 1196
| 976 } 977
|
1197 dependGraph.setInst(dest_reg, new_inst); 1198
| |
1199 // Mark the scoreboard to say it's not yet ready. 1200 regScoreboard[dest_reg] = false; 1201 } 1202} 1203 1204template <class Impl> 1205void 1206InstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 1207{
| 978 // Mark the scoreboard to say it's not yet ready. 979 regScoreboard[dest_reg] = false; 980 } 981} 982 983template <class Impl> 984void 985InstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 986{
|
1208 // If the instruction now has all of its source registers
| 987 //If the instruction now has all of its source registers
|
1209 // available, then add it to the list of ready instructions. 1210 if (inst->readyToIssue()) { 1211 1212 //Add the instruction to the proper ready list.
| 988 // available, then add it to the list of ready instructions. 989 if (inst->readyToIssue()) { 990 991 //Add the instruction to the proper ready list.
|
1213 if (inst->isMemRef()) {
| 992 if (inst->isControl()) {
|
1214
| 993
|
1215 DPRINTF(IQ, "Checking if memory instruction can issue.\n");
| 994 DPRINTF(IQ, "IQ: Branch instruction is ready to issue, " 995 "putting it onto the ready list, PC %#x.\n", 996 inst->readPC()); 997 readyBranchInsts.push(inst);
|
1216
| 998
|
| 999 } else if (inst->isMemRef()) { 1000 1001 DPRINTF(IQ, "IQ: Checking if memory instruction can issue.\n"); 1002
|
1217 // Message to the mem dependence unit that this instruction has 1218 // its registers ready.
| 1003 // Message to the mem dependence unit that this instruction has 1004 // its registers ready.
|
1219 memDepUnit[inst->threadNumber].regsReady(inst);
| |
1220
| 1005
|
1221 return; 1222 }
| 1006 memDepUnit.regsReady(inst);
|
1223
| 1007
|
1224 OpClass op_class = inst->opClass();
| 1008#if 0 1009 if (memDepUnit.readyToIssue(inst)) { 1010 DPRINTF(IQ, "IQ: Memory instruction is ready to issue, " 1011 "putting it onto the ready list, PC %#x.\n", 1012 inst->readPC()); 1013 readyMemInsts.push(inst); 1014 } else { 1015 // Make dependent on the store. 1016 // Will need some way to get the store instruction it should 1017 // be dependent upon; then when the store issues it can 1018 // put the instruction on the ready list. 1019 // Yet another tree? 1020 assert(0 && "Instruction has no way to actually issue"); 1021 } 1022#endif
|
1225
| 1023
|
1226 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 1227 "the ready list, PC %#x opclass:%i [sn:%lli].\n", 1228 inst->readPC(), op_class, inst->seqNum);
| 1024 } else if (inst->isInteger()) {
|
1229
| 1025
|
1230 readyInsts[op_class].push(inst);
| 1026 DPRINTF(IQ, "IQ: Integer instruction is ready to issue, " 1027 "putting it onto the ready list, PC %#x.\n", 1028 inst->readPC()); 1029 readyIntInsts.push(inst);
|
1231
| 1030
|
1232 // Will need to reorder the list if either a queue is not on the list, 1233 // or it has an older instruction than last time. 1234 if (!queueOnList[op_class]) { 1235 addToOrderList(op_class); 1236 } else if (readyInsts[op_class].top()->seqNum < 1237 (*readyIt[op_class]).oldestInst) { 1238 listOrder.erase(readyIt[op_class]); 1239 addToOrderList(op_class);
| 1031 } else if (inst->isFloating()) { 1032 1033 DPRINTF(IQ, "IQ: Floating instruction is ready to issue, " 1034 "putting it onto the ready list, PC %#x.\n", 1035 inst->readPC()); 1036 readyFloatInsts.push(inst); 1037 1038 } else { 1039 DPRINTF(IQ, "IQ: Miscellaneous instruction is ready to issue, " 1040 "putting it onto the ready list, PC %#x..\n", 1041 inst->readPC()); 1042 1043 readyMiscInsts.push(inst);
|
1240 } 1241 } 1242} 1243
| 1044 } 1045 } 1046} 1047
|
| 1048/* 1049 * Caution, this function must not be called prior to tail being updated at 1050 * least once, otherwise it will fail the assertion. This is because 1051 * instList.begin() actually changes upon the insertion of an element into the 1052 * list when the list is empty. 1053 */
|
1244template <class Impl> 1245int 1246InstructionQueue<Impl>::countInsts() 1247{
| 1054template <class Impl> 1055int 1056InstructionQueue<Impl>::countInsts() 1057{
|
1248 //ksewell:This works but definitely could use a cleaner write 1249 //with a more intuitive way of counting. Right now it's 1250 //just brute force .... 1251 1252#if 0
| 1058 ListIt count_it = cpu->instList.begin();
|
1253 int total_insts = 0; 1254
| 1059 int total_insts = 0; 1060
|
1255 for (int i = 0; i < numThreads; ++i) { 1256 ListIt count_it = instList[i].begin();
| 1061 if (tail == cpu->instList.end()) 1062 return 0;
|
1257
| 1063
|
1258 while (count_it != instList[i].end()) { 1259 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 1260 if (!(*count_it)->isIssued()) { 1261 ++total_insts; 1262 } else if ((*count_it)->isMemRef() && 1263 !(*count_it)->memOpDone) { 1264 // Loads that have not been marked as executed still count 1265 // towards the total instructions. 1266 ++total_insts; 1267 } 1268 } 1269 1270 ++count_it;
| 1064 while (count_it != tail) { 1065 if (!(*count_it)->isIssued()) { 1066 ++total_insts;
|
1271 }
| 1067 }
|
| 1068 1069 ++count_it; 1070 1071 assert(count_it != cpu->instList.end());
|
1272 } 1273
| 1072 } 1073
|
| 1074 // Need to count the tail iterator as well. 1075 if (count_it != cpu->instList.end() && 1076 (*count_it) && 1077 !(*count_it)->isIssued()) { 1078 ++total_insts; 1079 } 1080
|
1274 return total_insts;
| 1081 return total_insts;
|
1275#else 1276 return numEntries - freeEntries; 1277#endif
| |
1278} 1279 1280template <class Impl> 1281void
| 1082} 1083 1084template <class Impl> 1085void
|
1282InstructionQueue<Impl>::dumpLists()
| 1086InstructionQueue<Impl>::dumpDependGraph()
|
1283{
| 1087{
|
1284 for (int i = 0; i < Num_OpClasses; ++i) { 1285 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size());
| 1088 DependencyEntry *curr;
|
1286
| 1089
|
1287 cprintf("\n"); 1288 }
| 1090 for (int i = 0; i < numPhysRegs; ++i) 1091 { 1092 curr = &dependGraph[i];
|
1289
| 1093
|
1290 cprintf("Non speculative list size: %i\n", nonSpecInsts.size());
| 1094 if (curr->inst) { 1095 cprintf("dependGraph[%i]: producer: %#x consumer: ", i, 1096 curr->inst->readPC()); 1097 } else { 1098 cprintf("dependGraph[%i]: No producer. consumer: ", i); 1099 }
|
1291
| 1100
|
1292 NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 1293 NonSpecMapIt non_spec_end_it = nonSpecInsts.end();
| 1101 while (curr->next != NULL) { 1102 curr = curr->next;
|
1294
| 1103
|
1295 cprintf("Non speculative list: ");
| 1104 cprintf("%#x ", curr->inst->readPC()); 1105 }
|
1296
| 1106
|
1297 while (non_spec_it != non_spec_end_it) { 1298 cprintf("%#x [sn:%lli]", (*non_spec_it).second->readPC(), 1299 (*non_spec_it).second->seqNum); 1300 ++non_spec_it;
| 1107 cprintf("\n");
|
1301 }
| 1108 }
|
1302 1303 cprintf("\n"); 1304 1305 ListOrderIt list_order_it = listOrder.begin(); 1306 ListOrderIt list_order_end_it = listOrder.end(); 1307 int i = 1; 1308 1309 cprintf("List order: "); 1310 1311 while (list_order_it != list_order_end_it) { 1312 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 1313 (*list_order_it).oldestInst); 1314 1315 ++list_order_it; 1316 ++i; 1317 } 1318 1319 cprintf("\n");
| |
1320} 1321
| 1109} 1110
|
1322
| |
1323template <class Impl> 1324void
| 1111template <class Impl> 1112void
|
1325InstructionQueue<Impl>::dumpInsts()
| 1113InstructionQueue<Impl>::dumpLists()
|
1326{
| 1114{
|
1327 for (int i = 0; i < numThreads; ++i) { 1328 int num = 0; 1329 int valid_num = 0; 1330 ListIt inst_list_it = instList[i].begin();
| 1115 cprintf("Ready integer list size: %i\n", readyIntInsts.size());
|
1331
| 1116
|
1332 while (inst_list_it != instList[i].end()) 1333 { 1334 cprintf("Instruction:%i\n", 1335 num); 1336 if (!(*inst_list_it)->isSquashed()) { 1337 if (!(*inst_list_it)->isIssued()) { 1338 ++valid_num; 1339 cprintf("Count:%i\n", valid_num); 1340 } else if ((*inst_list_it)->isMemRef() && 1341 !(*inst_list_it)->memOpDone) { 1342 // Loads that have not been marked as executed 1343 // still count towards the total instructions. 1344 ++valid_num; 1345 cprintf("Count:%i\n", valid_num); 1346 } 1347 }
| 1117 cprintf("Ready float list size: %i\n", readyFloatInsts.size());
|
1348
| 1118
|
1349 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n" 1350 "Issued:%i\nSquashed:%i\n", 1351 (*inst_list_it)->readPC(), 1352 (*inst_list_it)->seqNum, 1353 (*inst_list_it)->threadNumber, 1354 (*inst_list_it)->isIssued(), 1355 (*inst_list_it)->isSquashed());
| 1119 cprintf("Ready branch list size: %i\n", readyBranchInsts.size());
|
1356
| 1120
|
1357 if ((*inst_list_it)->isMemRef()) { 1358 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 1359 }
| 1121 cprintf("Ready misc list size: %i\n", readyMiscInsts.size());
|
1360
| 1122
|
1361 cprintf("\n");
| 1123 cprintf("Squashed list size: %i\n", squashedInsts.size());
|
1362
| 1124
|
1363 inst_list_it++; 1364 ++num; 1365 }
| 1125 cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 1126 1127 non_spec_it_t non_spec_it = nonSpecInsts.begin(); 1128 1129 cprintf("Non speculative list: "); 1130 1131 while (non_spec_it != nonSpecInsts.end()) { 1132 cprintf("%#x ", (*non_spec_it).second->readPC()); 1133 ++non_spec_it;
|
1366 }
| 1134 }
|
| 1135 1136 cprintf("\n"); 1137
|
1367}
| 1138}
|