1/*
2 * Copyright (c) 2011-2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 */
44
45#ifndef __CPU_O3_INST_QUEUE_IMPL_HH__
46#define __CPU_O3_INST_QUEUE_IMPL_HH__
47
48#include <limits>
49#include <vector>
50
51#include "cpu/o3/fu_pool.hh"
52#include "cpu/o3/inst_queue.hh"
53#include "debug/IQ.hh"
54#include "enums/OpClass.hh"
55#include "params/DerivO3CPU.hh"
56#include "sim/core.hh"
57
58// clang complains about std::set being overloaded with Packet::set if
59// we open up the entire namespace std
60using std::list;
61
62template <class Impl>
63InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
64 int fu_idx, InstructionQueue<Impl> *iq_ptr)
65 : Event(Stat_Event_Pri, AutoDelete),
66 inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false)
67{
68}
69
70template <class Impl>
71void
72InstructionQueue<Impl>::FUCompletion::process()
73{
74 iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1);
75 inst = NULL;
76}
77
78
79template <class Impl>
80const char *
81InstructionQueue<Impl>::FUCompletion::description() const
82{
83 return "Functional unit completion";
84}
85
86template <class Impl>
87InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr,
88 DerivO3CPUParams *params)
89 : cpu(cpu_ptr),
90 iewStage(iew_ptr),
91 fuPool(params->fuPool),
92 numEntries(params->numIQEntries),
93 totalWidth(params->issueWidth),
94 commitToIEWDelay(params->commitToIEWDelay)
95{
96 assert(fuPool);
97
98 numThreads = params->numThreads;
99
100 // Set the number of total physical registers
101 numPhysRegs = params->numPhysIntRegs + params->numPhysFloatRegs +
102 params->numPhysCCRegs;
103
104 //Create an entry for each physical register within the
105 //dependency graph.
106 dependGraph.resize(numPhysRegs);
107
108 // Resize the register scoreboard.
109 regScoreboard.resize(numPhysRegs);
110
111 //Initialize Mem Dependence Units
112 for (ThreadID tid = 0; tid < numThreads; tid++) {
113 memDepUnit[tid].init(params, tid);
114 memDepUnit[tid].setIQ(this);
115 }
116
117 resetState();
118
119 std::string policy = params->smtIQPolicy;
120
121 //Convert string to lowercase
122 std::transform(policy.begin(), policy.end(), policy.begin(),
123 (int(*)(int)) tolower);
124
125 //Figure out resource sharing policy
126 if (policy == "dynamic") {
127 iqPolicy = Dynamic;
128
129 //Set Max Entries to Total ROB Capacity
130 for (ThreadID tid = 0; tid < numThreads; tid++) {
131 maxEntries[tid] = numEntries;
132 }
133
134 } else if (policy == "partitioned") {
135 iqPolicy = Partitioned;
136
137 //@todo:make work if part_amt doesnt divide evenly.
138 int part_amt = numEntries / numThreads;
139
140 //Divide ROB up evenly
141 for (ThreadID tid = 0; tid < numThreads; tid++) {
142 maxEntries[tid] = part_amt;
143 }
144
145 DPRINTF(IQ, "IQ sharing policy set to Partitioned:"
146 "%i entries per thread.\n",part_amt);
147 } else if (policy == "threshold") {
148 iqPolicy = Threshold;
149
150 double threshold = (double)params->smtIQThreshold / 100;
151
152 int thresholdIQ = (int)((double)threshold * numEntries);
153
154 //Divide up by threshold amount
155 for (ThreadID tid = 0; tid < numThreads; tid++) {
156 maxEntries[tid] = thresholdIQ;
157 }
158
159 DPRINTF(IQ, "IQ sharing policy set to Threshold:"
160 "%i entries per thread.\n",thresholdIQ);
161 } else {
162 assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
163 "Partitioned, Threshold}");
164 }
165}
166
167template <class Impl>
168InstructionQueue<Impl>::~InstructionQueue()
169{
170 dependGraph.reset();
171#ifdef DEBUG
172 cprintf("Nodes traversed: %i, removed: %i\n",
173 dependGraph.nodesTraversed, dependGraph.nodesRemoved);
174#endif
175}
176
177template <class Impl>
178std::string
179InstructionQueue<Impl>::name() const
180{
181 return cpu->name() + ".iq";
182}
183
184template <class Impl>
185void
186InstructionQueue<Impl>::regStats()
187{
188 using namespace Stats;
189 iqInstsAdded
190 .name(name() + ".iqInstsAdded")
191 .desc("Number of instructions added to the IQ (excludes non-spec)")
192 .prereq(iqInstsAdded);
193
194 iqNonSpecInstsAdded
195 .name(name() + ".iqNonSpecInstsAdded")
196 .desc("Number of non-speculative instructions added to the IQ")
197 .prereq(iqNonSpecInstsAdded);
198
199 iqInstsIssued
200 .name(name() + ".iqInstsIssued")
201 .desc("Number of instructions issued")
202 .prereq(iqInstsIssued);
203
204 iqIntInstsIssued
205 .name(name() + ".iqIntInstsIssued")
206 .desc("Number of integer instructions issued")
207 .prereq(iqIntInstsIssued);
208
209 iqFloatInstsIssued
210 .name(name() + ".iqFloatInstsIssued")
211 .desc("Number of float instructions issued")
212 .prereq(iqFloatInstsIssued);
213
214 iqBranchInstsIssued
215 .name(name() + ".iqBranchInstsIssued")
216 .desc("Number of branch instructions issued")
217 .prereq(iqBranchInstsIssued);
218
219 iqMemInstsIssued
220 .name(name() + ".iqMemInstsIssued")
221 .desc("Number of memory instructions issued")
222 .prereq(iqMemInstsIssued);
223
224 iqMiscInstsIssued
225 .name(name() + ".iqMiscInstsIssued")
226 .desc("Number of miscellaneous instructions issued")
227 .prereq(iqMiscInstsIssued);
228
229 iqSquashedInstsIssued
230 .name(name() + ".iqSquashedInstsIssued")
231 .desc("Number of squashed instructions issued")
232 .prereq(iqSquashedInstsIssued);
233
234 iqSquashedInstsExamined
235 .name(name() + ".iqSquashedInstsExamined")
236 .desc("Number of squashed instructions iterated over during squash;"
237 " mainly for profiling")
238 .prereq(iqSquashedInstsExamined);
239
240 iqSquashedOperandsExamined
241 .name(name() + ".iqSquashedOperandsExamined")
242 .desc("Number of squashed operands that are examined and possibly "
243 "removed from graph")
244 .prereq(iqSquashedOperandsExamined);
245
246 iqSquashedNonSpecRemoved
247 .name(name() + ".iqSquashedNonSpecRemoved")
248 .desc("Number of squashed non-spec instructions that were removed")
249 .prereq(iqSquashedNonSpecRemoved);
250/*
251 queueResDist
252 .init(Num_OpClasses, 0, 99, 2)
253 .name(name() + ".IQ:residence:")
254 .desc("cycles from dispatch to issue")
255 .flags(total | pdf | cdf )
256 ;
257 for (int i = 0; i < Num_OpClasses; ++i) {
258 queueResDist.subname(i, opClassStrings[i]);
259 }
260*/
261 numIssuedDist
262 .init(0,totalWidth,1)
263 .name(name() + ".issued_per_cycle")
264 .desc("Number of insts issued each cycle")
265 .flags(pdf)
266 ;
267/*
268 dist_unissued
269 .init(Num_OpClasses+2)
270 .name(name() + ".unissued_cause")
271 .desc("Reason ready instruction not issued")
272 .flags(pdf | dist)
273 ;
274 for (int i=0; i < (Num_OpClasses + 2); ++i) {
275 dist_unissued.subname(i, unissued_names[i]);
276 }
277*/
278 statIssuedInstType
279 .init(numThreads,Enums::Num_OpClass)
280 .name(name() + ".FU_type")
281 .desc("Type of FU issued")
282 .flags(total | pdf | dist)
283 ;
284 statIssuedInstType.ysubnames(Enums::OpClassStrings);
285
286 //
287 // How long did instructions for a particular FU type wait prior to issue
288 //
289/*
290 issueDelayDist
291 .init(Num_OpClasses,0,99,2)
292 .name(name() + ".")
293 .desc("cycles from operands ready to issue")
294 .flags(pdf | cdf)
295 ;
296
297 for (int i=0; i<Num_OpClasses; ++i) {
298 std::stringstream subname;
299 subname << opClassStrings[i] << "_delay";
300 issueDelayDist.subname(i, subname.str());
301 }
302*/
303 issueRate
304 .name(name() + ".rate")
305 .desc("Inst issue rate")
306 .flags(total)
307 ;
308 issueRate = iqInstsIssued / cpu->numCycles;
309
310 statFuBusy
311 .init(Num_OpClasses)
312 .name(name() + ".fu_full")
313 .desc("attempts to use FU when none available")
314 .flags(pdf | dist)
315 ;
316 for (int i=0; i < Num_OpClasses; ++i) {
317 statFuBusy.subname(i, Enums::OpClassStrings[i]);
318 }
319
320 fuBusy
321 .init(numThreads)
322 .name(name() + ".fu_busy_cnt")
323 .desc("FU busy when requested")
324 .flags(total)
325 ;
326
327 fuBusyRate
328 .name(name() + ".fu_busy_rate")
329 .desc("FU busy rate (busy events/executed inst)")
330 .flags(total)
331 ;
332 fuBusyRate = fuBusy / iqInstsIssued;
333
334 for (ThreadID tid = 0; tid < numThreads; tid++) {
335 // Tell mem dependence unit to reg stats as well.
336 memDepUnit[tid].regStats();
337 }
338
339 intInstQueueReads
340 .name(name() + ".int_inst_queue_reads")
341 .desc("Number of integer instruction queue reads")
342 .flags(total);
343
344 intInstQueueWrites
345 .name(name() + ".int_inst_queue_writes")
346 .desc("Number of integer instruction queue writes")
347 .flags(total);
348
349 intInstQueueWakeupAccesses
350 .name(name() + ".int_inst_queue_wakeup_accesses")
351 .desc("Number of integer instruction queue wakeup accesses")
352 .flags(total);
353
354 fpInstQueueReads
355 .name(name() + ".fp_inst_queue_reads")
356 .desc("Number of floating instruction queue reads")
357 .flags(total);
358
359 fpInstQueueWrites
360 .name(name() + ".fp_inst_queue_writes")
361 .desc("Number of floating instruction queue writes")
362 .flags(total);
363
364 fpInstQueueWakeupQccesses
365 .name(name() + ".fp_inst_queue_wakeup_accesses")
366 .desc("Number of floating instruction queue wakeup accesses")
367 .flags(total);
368
369 intAluAccesses
370 .name(name() + ".int_alu_accesses")
371 .desc("Number of integer alu accesses")
372 .flags(total);
373
374 fpAluAccesses
375 .name(name() + ".fp_alu_accesses")
376 .desc("Number of floating point alu accesses")
377 .flags(total);
378
379}
380
381template <class Impl>
382void
383InstructionQueue<Impl>::resetState()
384{
385 //Initialize thread IQ counts
386 for (ThreadID tid = 0; tid <numThreads; tid++) {
387 count[tid] = 0;
388 instList[tid].clear();
389 }
390
391 // Initialize the number of free IQ entries.
392 freeEntries = numEntries;
393
394 // Note that in actuality, the registers corresponding to the logical
395 // registers start off as ready. However this doesn't matter for the
396 // IQ as the instruction should have been correctly told if those
397 // registers are ready in rename. Thus it can all be initialized as
398 // unready.
399 for (int i = 0; i < numPhysRegs; ++i) {
400 regScoreboard[i] = false;
401 }
402
403 for (ThreadID tid = 0; tid < numThreads; ++tid) {
404 squashedSeqNum[tid] = 0;
405 }
406
407 for (int i = 0; i < Num_OpClasses; ++i) {
408 while (!readyInsts[i].empty())
409 readyInsts[i].pop();
410 queueOnList[i] = false;
411 readyIt[i] = listOrder.end();
412 }
413 nonSpecInsts.clear();
414 listOrder.clear();
415 deferredMemInsts.clear();
416 blockedMemInsts.clear();
417 retryMemInsts.clear();
418 wbOutstanding = 0;
419}
420
421template <class Impl>
422void
423InstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
424{
425 activeThreads = at_ptr;
426}
427
428template <class Impl>
429void
430InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr)
431{
432 issueToExecuteQueue = i2e_ptr;
433}
434
435template <class Impl>
436void
437InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
438{
439 timeBuffer = tb_ptr;
440
441 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
442}
443
444template <class Impl>
445bool
446InstructionQueue<Impl>::isDrained() const
447{
448 bool drained = dependGraph.empty() &&
449 instsToExecute.empty() &&
450 wbOutstanding == 0;
451 for (ThreadID tid = 0; tid < numThreads; ++tid)
452 drained = drained && memDepUnit[tid].isDrained();
453
454 return drained;
455}
456
457template <class Impl>
458void
459InstructionQueue<Impl>::drainSanityCheck() const
460{
461 assert(dependGraph.empty());
462 assert(instsToExecute.empty());
463 for (ThreadID tid = 0; tid < numThreads; ++tid)
464 memDepUnit[tid].drainSanityCheck();
465}
466
467template <class Impl>
468void
469InstructionQueue<Impl>::takeOverFrom()
470{
471 resetState();
472}
473
474template <class Impl>
475int
476InstructionQueue<Impl>::entryAmount(ThreadID num_threads)
477{
478 if (iqPolicy == Partitioned) {
479 return numEntries / num_threads;
480 } else {
481 return 0;
482 }
483}
484
485
486template <class Impl>
487void
488InstructionQueue<Impl>::resetEntries()
489{
490 if (iqPolicy != Dynamic || numThreads > 1) {
491 int active_threads = activeThreads->size();
492
493 list<ThreadID>::iterator threads = activeThreads->begin();
494 list<ThreadID>::iterator end = activeThreads->end();
495
496 while (threads != end) {
497 ThreadID tid = *threads++;
498
499 if (iqPolicy == Partitioned) {
500 maxEntries[tid] = numEntries / active_threads;
501 } else if(iqPolicy == Threshold && active_threads == 1) {
502 maxEntries[tid] = numEntries;
503 }
504 }
505 }
506}
507
508template <class Impl>
509unsigned
510InstructionQueue<Impl>::numFreeEntries()
511{
512 return freeEntries;
513}
514
515template <class Impl>
516unsigned
517InstructionQueue<Impl>::numFreeEntries(ThreadID tid)
518{
519 return maxEntries[tid] - count[tid];
520}
521
522// Might want to do something more complex if it knows how many instructions
523// will be issued this cycle.
524template <class Impl>
525bool
526InstructionQueue<Impl>::isFull()
527{
528 if (freeEntries == 0) {
529 return(true);
530 } else {
531 return(false);
532 }
533}
534
535template <class Impl>
536bool
537InstructionQueue<Impl>::isFull(ThreadID tid)
538{
539 if (numFreeEntries(tid) == 0) {
540 return(true);
541 } else {
542 return(false);
543 }
544}
545
546template <class Impl>
547bool
548InstructionQueue<Impl>::hasReadyInsts()
549{
550 if (!listOrder.empty()) {
551 return true;
552 }
553
554 for (int i = 0; i < Num_OpClasses; ++i) {
555 if (!readyInsts[i].empty()) {
556 return true;
557 }
558 }
559
560 return false;
561}
562
563template <class Impl>
564void
565InstructionQueue<Impl>::insert(DynInstPtr &new_inst)
566{
567 new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
568 // Make sure the instruction is valid
569 assert(new_inst);
570
571 DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n",
572 new_inst->seqNum, new_inst->pcState());
573
574 assert(freeEntries != 0);
575
576 instList[new_inst->threadNumber].push_back(new_inst);
577
578 --freeEntries;
579
580 new_inst->setInIQ();
581
582 // Look through its source registers (physical regs), and mark any
583 // dependencies.
584 addToDependents(new_inst);
585
586 // Have this instruction set itself as the producer of its destination
587 // register(s).
588 addToProducers(new_inst);
589
590 if (new_inst->isMemRef()) {
591 memDepUnit[new_inst->threadNumber].insert(new_inst);
592 } else {
593 addIfReady(new_inst);
594 }
595
596 ++iqInstsAdded;
597
598 count[new_inst->threadNumber]++;
599
600 assert(freeEntries == (numEntries - countInsts()));
601}
602
603template <class Impl>
604void
605InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst)
606{
607 // @todo: Clean up this code; can do it by setting inst as unable
608 // to issue, then calling normal insert on the inst.
609 new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
610
611 assert(new_inst);
612
613 nonSpecInsts[new_inst->seqNum] = new_inst;
614
615 DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s "
616 "to the IQ.\n",
617 new_inst->seqNum, new_inst->pcState());
618
619 assert(freeEntries != 0);
620
621 instList[new_inst->threadNumber].push_back(new_inst);
622
623 --freeEntries;
624
625 new_inst->setInIQ();
626
627 // Have this instruction set itself as the producer of its destination
628 // register(s).
629 addToProducers(new_inst);
630
631 // If it's a memory instruction, add it to the memory dependency
632 // unit.
633 if (new_inst->isMemRef()) {
634 memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst);
635 }
636
637 ++iqNonSpecInstsAdded;
638
639 count[new_inst->threadNumber]++;
640
641 assert(freeEntries == (numEntries - countInsts()));
642}
643
644template <class Impl>
645void
646InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst)
647{
648 memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst);
649
650 insertNonSpec(barr_inst);
651}
652
653template <class Impl>
654typename Impl::DynInstPtr
655InstructionQueue<Impl>::getInstToExecute()
656{
657 assert(!instsToExecute.empty());
658 DynInstPtr inst = instsToExecute.front();
659 instsToExecute.pop_front();
660 if (inst->isFloating()){
661 fpInstQueueReads++;
662 } else {
663 intInstQueueReads++;
664 }
665 return inst;
666}
667
668template <class Impl>
669void
670InstructionQueue<Impl>::addToOrderList(OpClass op_class)
671{
672 assert(!readyInsts[op_class].empty());
673
674 ListOrderEntry queue_entry;
675
676 queue_entry.queueType = op_class;
677
678 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
679
680 ListOrderIt list_it = listOrder.begin();
681 ListOrderIt list_end_it = listOrder.end();
682
683 while (list_it != list_end_it) {
684 if ((*list_it).oldestInst > queue_entry.oldestInst) {
685 break;
686 }
687
688 list_it++;
689 }
690
691 readyIt[op_class] = listOrder.insert(list_it, queue_entry);
692 queueOnList[op_class] = true;
693}
694
695template <class Impl>
696void
697InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it)
698{
699 // Get iterator of next item on the list
700 // Delete the original iterator
701 // Determine if the next item is either the end of the list or younger
702 // than the new instruction. If so, then add in a new iterator right here.
703 // If not, then move along.
704 ListOrderEntry queue_entry;
705 OpClass op_class = (*list_order_it).queueType;
706 ListOrderIt next_it = list_order_it;
707
708 ++next_it;
709
710 queue_entry.queueType = op_class;
711 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
712
713 while (next_it != listOrder.end() &&
714 (*next_it).oldestInst < queue_entry.oldestInst) {
715 ++next_it;
716 }
717
718 readyIt[op_class] = listOrder.insert(next_it, queue_entry);
719}
720
721template <class Impl>
722void
723InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx)
724{
725 DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum);
726 assert(!cpu->switchedOut());
727 // The CPU could have been sleeping until this op completed (*extremely*
728 // long latency op). Wake it if it was. This may be overkill.
729 --wbOutstanding;
730 iewStage->wakeCPU();
731
732 if (fu_idx > -1)
733 fuPool->freeUnitNextCycle(fu_idx);
734
735 // @todo: Ensure that these FU Completions happen at the beginning
736 // of a cycle, otherwise they could add too many instructions to
737 // the queue.
738 issueToExecuteQueue->access(-1)->size++;
739 instsToExecute.push_back(inst);
740}
741
742// @todo: Figure out a better way to remove the squashed items from the
743// lists. Checking the top item of each list to see if it's squashed
744// wastes time and forces jumps.
745template <class Impl>
746void
747InstructionQueue<Impl>::scheduleReadyInsts()
748{
749 DPRINTF(IQ, "Attempting to schedule ready instructions from "
750 "the IQ.\n");
751
752 IssueStruct *i2e_info = issueToExecuteQueue->access(0);
753
754 DynInstPtr mem_inst;
755 while (mem_inst = getDeferredMemInstToExecute()) {
756 addReadyMemInst(mem_inst);
757 }
758
759 // See if any cache blocked instructions are able to be executed
760 while (mem_inst = getBlockedMemInstToExecute()) {
761 addReadyMemInst(mem_inst);
762 }
763
764 // Have iterator to head of the list
765 // While I haven't exceeded bandwidth or reached the end of the list,
766 // Try to get a FU that can do what this op needs.
767 // If successful, change the oldestInst to the new top of the list, put
768 // the queue in the proper place in the list.
769 // Increment the iterator.
770 // This will avoid trying to schedule a certain op class if there are no
771 // FUs that handle it.
772 int total_issued = 0;
773 ListOrderIt order_it = listOrder.begin();
774 ListOrderIt order_end_it = listOrder.end();
775
776 while (total_issued < totalWidth && order_it != order_end_it) {
777 OpClass op_class = (*order_it).queueType;
778
779 assert(!readyInsts[op_class].empty());
780
781 DynInstPtr issuing_inst = readyInsts[op_class].top();
782
783 issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++;
784
785 assert(issuing_inst->seqNum == (*order_it).oldestInst);
786
787 if (issuing_inst->isSquashed()) {
788 readyInsts[op_class].pop();
789
790 if (!readyInsts[op_class].empty()) {
791 moveToYoungerInst(order_it);
792 } else {
793 readyIt[op_class] = listOrder.end();
794 queueOnList[op_class] = false;
795 }
796
797 listOrder.erase(order_it++);
798
799 ++iqSquashedInstsIssued;
800
801 continue;
802 }
803
804 int idx = -2;
805 Cycles op_latency = Cycles(1);
806 ThreadID tid = issuing_inst->threadNumber;
807
808 if (op_class != No_OpClass) {
809 idx = fuPool->getUnit(op_class);
810 issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++;
811 if (idx > -1) {
812 op_latency = fuPool->getOpLatency(op_class);
813 }
814 }
815
816 // If we have an instruction that doesn't require a FU, or a
817 // valid FU, then schedule for execution.
818 if (idx == -2 || idx != -1) {
819 if (op_latency == Cycles(1)) {
820 i2e_info->size++;
821 instsToExecute.push_back(issuing_inst);
822
823 // Add the FU onto the list of FU's to be freed next
824 // cycle if we used one.
825 if (idx >= 0)
826 fuPool->freeUnitNextCycle(idx);
827 } else {
828 Cycles issue_latency = fuPool->getIssueLatency(op_class);
829 // Generate completion event for the FU
830 ++wbOutstanding;
831 FUCompletion *execution = new FUCompletion(issuing_inst,
832 idx, this);
833
834 cpu->schedule(execution,
835 cpu->clockEdge(Cycles(op_latency - 1)));
836
837 // @todo: Enforce that issue_latency == 1 or op_latency
838 if (issue_latency > Cycles(1)) {
839 // If FU isn't pipelined, then it must be freed
840 // upon the execution completing.
841 execution->setFreeFU();
842 } else {
843 // Add the FU onto the list of FU's to be freed next cycle.
844 fuPool->freeUnitNextCycle(idx);
845 }
846 }
847
848 DPRINTF(IQ, "Thread %i: Issuing instruction PC %s "
849 "[sn:%lli]\n",
850 tid, issuing_inst->pcState(),
851 issuing_inst->seqNum);
852
853 readyInsts[op_class].pop();
854
855 if (!readyInsts[op_class].empty()) {
856 moveToYoungerInst(order_it);
857 } else {
858 readyIt[op_class] = listOrder.end();
859 queueOnList[op_class] = false;
860 }
861
862 issuing_inst->setIssued();
863 ++total_issued;
864
865#if TRACING_ON
866 issuing_inst->issueTick = curTick() - issuing_inst->fetchTick;
867#endif
868
869 if (!issuing_inst->isMemRef()) {
870 // Memory instructions can not be freed from the IQ until they
871 // complete.
872 ++freeEntries;
873 count[tid]--;
874 issuing_inst->clearInIQ();
875 } else {
876 memDepUnit[tid].issue(issuing_inst);
877 }
878
879 listOrder.erase(order_it++);
880 statIssuedInstType[tid][op_class]++;
881 } else {
882 statFuBusy[op_class]++;
883 fuBusy[tid]++;
884 ++order_it;
885 }
886 }
887
888 numIssuedDist.sample(total_issued);
889 iqInstsIssued+= total_issued;
890
891 // If we issued any instructions, tell the CPU we had activity.
892 // @todo If the way deferred memory instructions are handeled due to
893 // translation changes then the deferredMemInsts condition should be removed
894 // from the code below.
895 if (total_issued || !retryMemInsts.empty() || !deferredMemInsts.empty()) {
896 cpu->activityThisCycle();
897 } else {
898 DPRINTF(IQ, "Not able to schedule any instructions.\n");
899 }
900}
901
902template <class Impl>
903void
904InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
905{
906 DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready "
907 "to execute.\n", inst);
908
909 NonSpecMapIt inst_it = nonSpecInsts.find(inst);
910
911 assert(inst_it != nonSpecInsts.end());
912
913 ThreadID tid = (*inst_it).second->threadNumber;
914
915 (*inst_it).second->setAtCommit();
916
917 (*inst_it).second->setCanIssue();
918
919 if (!(*inst_it).second->isMemRef()) {
920 addIfReady((*inst_it).second);
921 } else {
922 memDepUnit[tid].nonSpecInstReady((*inst_it).second);
923 }
924
925 (*inst_it).second = NULL;
926
927 nonSpecInsts.erase(inst_it);
928}
929
930template <class Impl>
931void
932InstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid)
933{
934 DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n",
935 tid,inst);
936
937 ListIt iq_it = instList[tid].begin();
938
939 while (iq_it != instList[tid].end() &&
940 (*iq_it)->seqNum <= inst) {
941 ++iq_it;
942 instList[tid].pop_front();
943 }
944
945 assert(freeEntries == (numEntries - countInsts()));
946}
947
948template <class Impl>
949int
950InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
951{
952 int dependents = 0;
953
954 // The instruction queue here takes care of both floating and int ops
955 if (completed_inst->isFloating()) {
956 fpInstQueueWakeupQccesses++;
957 } else {
958 intInstQueueWakeupAccesses++;
959 }
960
961 DPRINTF(IQ, "Waking dependents of completed instruction.\n");
962
963 assert(!completed_inst->isSquashed());
964
965 // Tell the memory dependence unit to wake any dependents on this
966 // instruction if it is a memory instruction. Also complete the memory
967 // instruction at this point since we know it executed without issues.
968 // @todo: Might want to rename "completeMemInst" to something that
969 // indicates that it won't need to be replayed, and call this
970 // earlier. Might not be a big deal.
971 if (completed_inst->isMemRef()) {
972 memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst);
973 completeMemInst(completed_inst);
974 } else if (completed_inst->isMemBarrier() ||
975 completed_inst->isWriteBarrier()) {
976 memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst);
977 }
978
979 for (int dest_reg_idx = 0;
980 dest_reg_idx < completed_inst->numDestRegs();
981 dest_reg_idx++)
982 {
983 PhysRegIndex dest_reg =
984 completed_inst->renamedDestRegIdx(dest_reg_idx);
985
986 // Special case of uniq or control registers. They are not
987 // handled by the IQ and thus have no dependency graph entry.
988 // @todo Figure out a cleaner way to handle this.
989 if (dest_reg >= numPhysRegs) {
990 DPRINTF(IQ, "dest_reg :%d, numPhysRegs: %d\n", dest_reg,
991 numPhysRegs);
992 continue;
993 }
994
995 DPRINTF(IQ, "Waking any dependents on register %i.\n",
996 (int) dest_reg);
997
998 //Go through the dependency chain, marking the registers as
999 //ready within the waiting instructions.
1000 DynInstPtr dep_inst = dependGraph.pop(dest_reg);
1001
1002 while (dep_inst) {
1003 DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] "
1004 "PC %s.\n", dep_inst->seqNum, dep_inst->pcState());
1005
1006 // Might want to give more information to the instruction
1007 // so that it knows which of its source registers is
1008 // ready. However that would mean that the dependency
1009 // graph entries would need to hold the src_reg_idx.
1010 dep_inst->markSrcRegReady();
1011
1012 addIfReady(dep_inst);
1013
1014 dep_inst = dependGraph.pop(dest_reg);
1015
1016 ++dependents;
1017 }
1018
1019 // Reset the head node now that all of its dependents have
1020 // been woken up.
1021 assert(dependGraph.empty(dest_reg));
1022 dependGraph.clearInst(dest_reg);
1023
1024 // Mark the scoreboard as having that register ready.
1025 regScoreboard[dest_reg] = true;
1026 }
1027 return dependents;
1028}
1029
1030template <class Impl>
1031void
1032InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst)
1033{
1034 OpClass op_class = ready_inst->opClass();
1035
1036 readyInsts[op_class].push(ready_inst);
1037
1038 // Will need to reorder the list if either a queue is not on the list,
1039 // or it has an older instruction than last time.
1040 if (!queueOnList[op_class]) {
1041 addToOrderList(op_class);
1042 } else if (readyInsts[op_class].top()->seqNum <
1043 (*readyIt[op_class]).oldestInst) {
1044 listOrder.erase(readyIt[op_class]);
1045 addToOrderList(op_class);
1046 }
1047
1048 DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1049 "the ready list, PC %s opclass:%i [sn:%lli].\n",
1050 ready_inst->pcState(), op_class, ready_inst->seqNum);
1051}
1052
1053template <class Impl>
1054void
1055InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst)
1056{
1057 DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum);
1058
1059 // Reset DTB translation state
1060 resched_inst->translationStarted(false);
1061 resched_inst->translationCompleted(false);
1062
1063 resched_inst->clearCanIssue();
1064 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
1065}
1066
1067template <class Impl>
1068void
1069InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst)
1070{
1071 memDepUnit[replay_inst->threadNumber].replay();
1072}
1073
1074template <class Impl>
1075void
1076InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst)
1077{
1078 ThreadID tid = completed_inst->threadNumber;
1079
1080 DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n",
1081 completed_inst->pcState(), completed_inst->seqNum);
1082
1083 ++freeEntries;
1084
1085 completed_inst->memOpDone(true);
1086
1087 memDepUnit[tid].completed(completed_inst);
1088 count[tid]--;
1089}
1090
1091template <class Impl>
1092void
1093InstructionQueue<Impl>::deferMemInst(DynInstPtr &deferred_inst)
1094{
1095 deferredMemInsts.push_back(deferred_inst);
1096}
1097
1098template <class Impl>
1099void
1100InstructionQueue<Impl>::blockMemInst(DynInstPtr &blocked_inst)
1101{
1102 blocked_inst->translationStarted(false);
1103 blocked_inst->translationCompleted(false);
1104
1105 blocked_inst->clearIssued();
1106 blocked_inst->clearCanIssue();
1107 blockedMemInsts.push_back(blocked_inst);
1108}
1109
1110template <class Impl>
1111void
1112InstructionQueue<Impl>::cacheUnblocked()
1113{
1114 retryMemInsts.splice(retryMemInsts.end(), blockedMemInsts);
1115 // Get the CPU ticking again
1116 cpu->wakeCPU();
1117}
1118
1119template <class Impl>
1120typename Impl::DynInstPtr
1121InstructionQueue<Impl>::getDeferredMemInstToExecute()
1122{
1123 for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end();
1124 ++it) {
1125 if ((*it)->translationCompleted() || (*it)->isSquashed()) {
1126 DynInstPtr mem_inst = *it;
1127 deferredMemInsts.erase(it);
1128 return mem_inst;
1129 }
1130 }
1131 return nullptr;
1132}
1133
1134template <class Impl>
1135typename Impl::DynInstPtr
1136InstructionQueue<Impl>::getBlockedMemInstToExecute()
1137{
1138 if (retryMemInsts.empty()) {
1139 return nullptr;
1140 } else {
1141 DynInstPtr mem_inst = retryMemInsts.front();
1142 retryMemInsts.pop_front();
1143 return mem_inst;
1144 }
1145}
1146
1147template <class Impl>
1148void
1149InstructionQueue<Impl>::violation(DynInstPtr &store,
1150 DynInstPtr &faulting_load)
1151{
1152 intInstQueueWrites++;
1153 memDepUnit[store->threadNumber].violation(store, faulting_load);
1154}
1155
1156template <class Impl>
1157void
1158InstructionQueue<Impl>::squash(ThreadID tid)
1159{
1160 DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in "
1161 "the IQ.\n", tid);
1162
1163 // Read instruction sequence number of last instruction out of the
1164 // time buffer.
1165 squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
1166
| 1/*
2 * Copyright (c) 2011-2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 */
44
45#ifndef __CPU_O3_INST_QUEUE_IMPL_HH__
46#define __CPU_O3_INST_QUEUE_IMPL_HH__
47
48#include <limits>
49#include <vector>
50
51#include "cpu/o3/fu_pool.hh"
52#include "cpu/o3/inst_queue.hh"
53#include "debug/IQ.hh"
54#include "enums/OpClass.hh"
55#include "params/DerivO3CPU.hh"
56#include "sim/core.hh"
57
58// clang complains about std::set being overloaded with Packet::set if
59// we open up the entire namespace std
60using std::list;
61
62template <class Impl>
63InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
64 int fu_idx, InstructionQueue<Impl> *iq_ptr)
65 : Event(Stat_Event_Pri, AutoDelete),
66 inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false)
67{
68}
69
70template <class Impl>
71void
72InstructionQueue<Impl>::FUCompletion::process()
73{
74 iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1);
75 inst = NULL;
76}
77
78
79template <class Impl>
80const char *
81InstructionQueue<Impl>::FUCompletion::description() const
82{
83 return "Functional unit completion";
84}
85
86template <class Impl>
87InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr,
88 DerivO3CPUParams *params)
89 : cpu(cpu_ptr),
90 iewStage(iew_ptr),
91 fuPool(params->fuPool),
92 numEntries(params->numIQEntries),
93 totalWidth(params->issueWidth),
94 commitToIEWDelay(params->commitToIEWDelay)
95{
96 assert(fuPool);
97
98 numThreads = params->numThreads;
99
100 // Set the number of total physical registers
101 numPhysRegs = params->numPhysIntRegs + params->numPhysFloatRegs +
102 params->numPhysCCRegs;
103
104 //Create an entry for each physical register within the
105 //dependency graph.
106 dependGraph.resize(numPhysRegs);
107
108 // Resize the register scoreboard.
109 regScoreboard.resize(numPhysRegs);
110
111 //Initialize Mem Dependence Units
112 for (ThreadID tid = 0; tid < numThreads; tid++) {
113 memDepUnit[tid].init(params, tid);
114 memDepUnit[tid].setIQ(this);
115 }
116
117 resetState();
118
119 std::string policy = params->smtIQPolicy;
120
121 //Convert string to lowercase
122 std::transform(policy.begin(), policy.end(), policy.begin(),
123 (int(*)(int)) tolower);
124
125 //Figure out resource sharing policy
126 if (policy == "dynamic") {
127 iqPolicy = Dynamic;
128
129 //Set Max Entries to Total ROB Capacity
130 for (ThreadID tid = 0; tid < numThreads; tid++) {
131 maxEntries[tid] = numEntries;
132 }
133
134 } else if (policy == "partitioned") {
135 iqPolicy = Partitioned;
136
137 //@todo:make work if part_amt doesnt divide evenly.
138 int part_amt = numEntries / numThreads;
139
140 //Divide ROB up evenly
141 for (ThreadID tid = 0; tid < numThreads; tid++) {
142 maxEntries[tid] = part_amt;
143 }
144
145 DPRINTF(IQ, "IQ sharing policy set to Partitioned:"
146 "%i entries per thread.\n",part_amt);
147 } else if (policy == "threshold") {
148 iqPolicy = Threshold;
149
150 double threshold = (double)params->smtIQThreshold / 100;
151
152 int thresholdIQ = (int)((double)threshold * numEntries);
153
154 //Divide up by threshold amount
155 for (ThreadID tid = 0; tid < numThreads; tid++) {
156 maxEntries[tid] = thresholdIQ;
157 }
158
159 DPRINTF(IQ, "IQ sharing policy set to Threshold:"
160 "%i entries per thread.\n",thresholdIQ);
161 } else {
162 assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
163 "Partitioned, Threshold}");
164 }
165}
166
167template <class Impl>
168InstructionQueue<Impl>::~InstructionQueue()
169{
170 dependGraph.reset();
171#ifdef DEBUG
172 cprintf("Nodes traversed: %i, removed: %i\n",
173 dependGraph.nodesTraversed, dependGraph.nodesRemoved);
174#endif
175}
176
177template <class Impl>
178std::string
179InstructionQueue<Impl>::name() const
180{
181 return cpu->name() + ".iq";
182}
183
184template <class Impl>
185void
186InstructionQueue<Impl>::regStats()
187{
188 using namespace Stats;
189 iqInstsAdded
190 .name(name() + ".iqInstsAdded")
191 .desc("Number of instructions added to the IQ (excludes non-spec)")
192 .prereq(iqInstsAdded);
193
194 iqNonSpecInstsAdded
195 .name(name() + ".iqNonSpecInstsAdded")
196 .desc("Number of non-speculative instructions added to the IQ")
197 .prereq(iqNonSpecInstsAdded);
198
199 iqInstsIssued
200 .name(name() + ".iqInstsIssued")
201 .desc("Number of instructions issued")
202 .prereq(iqInstsIssued);
203
204 iqIntInstsIssued
205 .name(name() + ".iqIntInstsIssued")
206 .desc("Number of integer instructions issued")
207 .prereq(iqIntInstsIssued);
208
209 iqFloatInstsIssued
210 .name(name() + ".iqFloatInstsIssued")
211 .desc("Number of float instructions issued")
212 .prereq(iqFloatInstsIssued);
213
214 iqBranchInstsIssued
215 .name(name() + ".iqBranchInstsIssued")
216 .desc("Number of branch instructions issued")
217 .prereq(iqBranchInstsIssued);
218
219 iqMemInstsIssued
220 .name(name() + ".iqMemInstsIssued")
221 .desc("Number of memory instructions issued")
222 .prereq(iqMemInstsIssued);
223
224 iqMiscInstsIssued
225 .name(name() + ".iqMiscInstsIssued")
226 .desc("Number of miscellaneous instructions issued")
227 .prereq(iqMiscInstsIssued);
228
229 iqSquashedInstsIssued
230 .name(name() + ".iqSquashedInstsIssued")
231 .desc("Number of squashed instructions issued")
232 .prereq(iqSquashedInstsIssued);
233
234 iqSquashedInstsExamined
235 .name(name() + ".iqSquashedInstsExamined")
236 .desc("Number of squashed instructions iterated over during squash;"
237 " mainly for profiling")
238 .prereq(iqSquashedInstsExamined);
239
240 iqSquashedOperandsExamined
241 .name(name() + ".iqSquashedOperandsExamined")
242 .desc("Number of squashed operands that are examined and possibly "
243 "removed from graph")
244 .prereq(iqSquashedOperandsExamined);
245
246 iqSquashedNonSpecRemoved
247 .name(name() + ".iqSquashedNonSpecRemoved")
248 .desc("Number of squashed non-spec instructions that were removed")
249 .prereq(iqSquashedNonSpecRemoved);
250/*
251 queueResDist
252 .init(Num_OpClasses, 0, 99, 2)
253 .name(name() + ".IQ:residence:")
254 .desc("cycles from dispatch to issue")
255 .flags(total | pdf | cdf )
256 ;
257 for (int i = 0; i < Num_OpClasses; ++i) {
258 queueResDist.subname(i, opClassStrings[i]);
259 }
260*/
261 numIssuedDist
262 .init(0,totalWidth,1)
263 .name(name() + ".issued_per_cycle")
264 .desc("Number of insts issued each cycle")
265 .flags(pdf)
266 ;
267/*
268 dist_unissued
269 .init(Num_OpClasses+2)
270 .name(name() + ".unissued_cause")
271 .desc("Reason ready instruction not issued")
272 .flags(pdf | dist)
273 ;
274 for (int i=0; i < (Num_OpClasses + 2); ++i) {
275 dist_unissued.subname(i, unissued_names[i]);
276 }
277*/
278 statIssuedInstType
279 .init(numThreads,Enums::Num_OpClass)
280 .name(name() + ".FU_type")
281 .desc("Type of FU issued")
282 .flags(total | pdf | dist)
283 ;
284 statIssuedInstType.ysubnames(Enums::OpClassStrings);
285
286 //
287 // How long did instructions for a particular FU type wait prior to issue
288 //
289/*
290 issueDelayDist
291 .init(Num_OpClasses,0,99,2)
292 .name(name() + ".")
293 .desc("cycles from operands ready to issue")
294 .flags(pdf | cdf)
295 ;
296
297 for (int i=0; i<Num_OpClasses; ++i) {
298 std::stringstream subname;
299 subname << opClassStrings[i] << "_delay";
300 issueDelayDist.subname(i, subname.str());
301 }
302*/
303 issueRate
304 .name(name() + ".rate")
305 .desc("Inst issue rate")
306 .flags(total)
307 ;
308 issueRate = iqInstsIssued / cpu->numCycles;
309
310 statFuBusy
311 .init(Num_OpClasses)
312 .name(name() + ".fu_full")
313 .desc("attempts to use FU when none available")
314 .flags(pdf | dist)
315 ;
316 for (int i=0; i < Num_OpClasses; ++i) {
317 statFuBusy.subname(i, Enums::OpClassStrings[i]);
318 }
319
320 fuBusy
321 .init(numThreads)
322 .name(name() + ".fu_busy_cnt")
323 .desc("FU busy when requested")
324 .flags(total)
325 ;
326
327 fuBusyRate
328 .name(name() + ".fu_busy_rate")
329 .desc("FU busy rate (busy events/executed inst)")
330 .flags(total)
331 ;
332 fuBusyRate = fuBusy / iqInstsIssued;
333
334 for (ThreadID tid = 0; tid < numThreads; tid++) {
335 // Tell mem dependence unit to reg stats as well.
336 memDepUnit[tid].regStats();
337 }
338
339 intInstQueueReads
340 .name(name() + ".int_inst_queue_reads")
341 .desc("Number of integer instruction queue reads")
342 .flags(total);
343
344 intInstQueueWrites
345 .name(name() + ".int_inst_queue_writes")
346 .desc("Number of integer instruction queue writes")
347 .flags(total);
348
349 intInstQueueWakeupAccesses
350 .name(name() + ".int_inst_queue_wakeup_accesses")
351 .desc("Number of integer instruction queue wakeup accesses")
352 .flags(total);
353
354 fpInstQueueReads
355 .name(name() + ".fp_inst_queue_reads")
356 .desc("Number of floating instruction queue reads")
357 .flags(total);
358
359 fpInstQueueWrites
360 .name(name() + ".fp_inst_queue_writes")
361 .desc("Number of floating instruction queue writes")
362 .flags(total);
363
364 fpInstQueueWakeupQccesses
365 .name(name() + ".fp_inst_queue_wakeup_accesses")
366 .desc("Number of floating instruction queue wakeup accesses")
367 .flags(total);
368
369 intAluAccesses
370 .name(name() + ".int_alu_accesses")
371 .desc("Number of integer alu accesses")
372 .flags(total);
373
374 fpAluAccesses
375 .name(name() + ".fp_alu_accesses")
376 .desc("Number of floating point alu accesses")
377 .flags(total);
378
379}
380
381template <class Impl>
382void
383InstructionQueue<Impl>::resetState()
384{
385 //Initialize thread IQ counts
386 for (ThreadID tid = 0; tid <numThreads; tid++) {
387 count[tid] = 0;
388 instList[tid].clear();
389 }
390
391 // Initialize the number of free IQ entries.
392 freeEntries = numEntries;
393
394 // Note that in actuality, the registers corresponding to the logical
395 // registers start off as ready. However this doesn't matter for the
396 // IQ as the instruction should have been correctly told if those
397 // registers are ready in rename. Thus it can all be initialized as
398 // unready.
399 for (int i = 0; i < numPhysRegs; ++i) {
400 regScoreboard[i] = false;
401 }
402
403 for (ThreadID tid = 0; tid < numThreads; ++tid) {
404 squashedSeqNum[tid] = 0;
405 }
406
407 for (int i = 0; i < Num_OpClasses; ++i) {
408 while (!readyInsts[i].empty())
409 readyInsts[i].pop();
410 queueOnList[i] = false;
411 readyIt[i] = listOrder.end();
412 }
413 nonSpecInsts.clear();
414 listOrder.clear();
415 deferredMemInsts.clear();
416 blockedMemInsts.clear();
417 retryMemInsts.clear();
418 wbOutstanding = 0;
419}
420
421template <class Impl>
422void
423InstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
424{
425 activeThreads = at_ptr;
426}
427
428template <class Impl>
429void
430InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr)
431{
432 issueToExecuteQueue = i2e_ptr;
433}
434
435template <class Impl>
436void
437InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
438{
439 timeBuffer = tb_ptr;
440
441 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
442}
443
444template <class Impl>
445bool
446InstructionQueue<Impl>::isDrained() const
447{
448 bool drained = dependGraph.empty() &&
449 instsToExecute.empty() &&
450 wbOutstanding == 0;
451 for (ThreadID tid = 0; tid < numThreads; ++tid)
452 drained = drained && memDepUnit[tid].isDrained();
453
454 return drained;
455}
456
457template <class Impl>
458void
459InstructionQueue<Impl>::drainSanityCheck() const
460{
461 assert(dependGraph.empty());
462 assert(instsToExecute.empty());
463 for (ThreadID tid = 0; tid < numThreads; ++tid)
464 memDepUnit[tid].drainSanityCheck();
465}
466
467template <class Impl>
468void
469InstructionQueue<Impl>::takeOverFrom()
470{
471 resetState();
472}
473
474template <class Impl>
475int
476InstructionQueue<Impl>::entryAmount(ThreadID num_threads)
477{
478 if (iqPolicy == Partitioned) {
479 return numEntries / num_threads;
480 } else {
481 return 0;
482 }
483}
484
485
486template <class Impl>
487void
488InstructionQueue<Impl>::resetEntries()
489{
490 if (iqPolicy != Dynamic || numThreads > 1) {
491 int active_threads = activeThreads->size();
492
493 list<ThreadID>::iterator threads = activeThreads->begin();
494 list<ThreadID>::iterator end = activeThreads->end();
495
496 while (threads != end) {
497 ThreadID tid = *threads++;
498
499 if (iqPolicy == Partitioned) {
500 maxEntries[tid] = numEntries / active_threads;
501 } else if(iqPolicy == Threshold && active_threads == 1) {
502 maxEntries[tid] = numEntries;
503 }
504 }
505 }
506}
507
508template <class Impl>
509unsigned
510InstructionQueue<Impl>::numFreeEntries()
511{
512 return freeEntries;
513}
514
515template <class Impl>
516unsigned
517InstructionQueue<Impl>::numFreeEntries(ThreadID tid)
518{
519 return maxEntries[tid] - count[tid];
520}
521
522// Might want to do something more complex if it knows how many instructions
523// will be issued this cycle.
524template <class Impl>
525bool
526InstructionQueue<Impl>::isFull()
527{
528 if (freeEntries == 0) {
529 return(true);
530 } else {
531 return(false);
532 }
533}
534
535template <class Impl>
536bool
537InstructionQueue<Impl>::isFull(ThreadID tid)
538{
539 if (numFreeEntries(tid) == 0) {
540 return(true);
541 } else {
542 return(false);
543 }
544}
545
546template <class Impl>
547bool
548InstructionQueue<Impl>::hasReadyInsts()
549{
550 if (!listOrder.empty()) {
551 return true;
552 }
553
554 for (int i = 0; i < Num_OpClasses; ++i) {
555 if (!readyInsts[i].empty()) {
556 return true;
557 }
558 }
559
560 return false;
561}
562
563template <class Impl>
564void
565InstructionQueue<Impl>::insert(DynInstPtr &new_inst)
566{
567 new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
568 // Make sure the instruction is valid
569 assert(new_inst);
570
571 DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n",
572 new_inst->seqNum, new_inst->pcState());
573
574 assert(freeEntries != 0);
575
576 instList[new_inst->threadNumber].push_back(new_inst);
577
578 --freeEntries;
579
580 new_inst->setInIQ();
581
582 // Look through its source registers (physical regs), and mark any
583 // dependencies.
584 addToDependents(new_inst);
585
586 // Have this instruction set itself as the producer of its destination
587 // register(s).
588 addToProducers(new_inst);
589
590 if (new_inst->isMemRef()) {
591 memDepUnit[new_inst->threadNumber].insert(new_inst);
592 } else {
593 addIfReady(new_inst);
594 }
595
596 ++iqInstsAdded;
597
598 count[new_inst->threadNumber]++;
599
600 assert(freeEntries == (numEntries - countInsts()));
601}
602
603template <class Impl>
604void
605InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst)
606{
607 // @todo: Clean up this code; can do it by setting inst as unable
608 // to issue, then calling normal insert on the inst.
609 new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
610
611 assert(new_inst);
612
613 nonSpecInsts[new_inst->seqNum] = new_inst;
614
615 DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s "
616 "to the IQ.\n",
617 new_inst->seqNum, new_inst->pcState());
618
619 assert(freeEntries != 0);
620
621 instList[new_inst->threadNumber].push_back(new_inst);
622
623 --freeEntries;
624
625 new_inst->setInIQ();
626
627 // Have this instruction set itself as the producer of its destination
628 // register(s).
629 addToProducers(new_inst);
630
631 // If it's a memory instruction, add it to the memory dependency
632 // unit.
633 if (new_inst->isMemRef()) {
634 memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst);
635 }
636
637 ++iqNonSpecInstsAdded;
638
639 count[new_inst->threadNumber]++;
640
641 assert(freeEntries == (numEntries - countInsts()));
642}
643
644template <class Impl>
645void
646InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst)
647{
648 memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst);
649
650 insertNonSpec(barr_inst);
651}
652
653template <class Impl>
654typename Impl::DynInstPtr
655InstructionQueue<Impl>::getInstToExecute()
656{
657 assert(!instsToExecute.empty());
658 DynInstPtr inst = instsToExecute.front();
659 instsToExecute.pop_front();
660 if (inst->isFloating()){
661 fpInstQueueReads++;
662 } else {
663 intInstQueueReads++;
664 }
665 return inst;
666}
667
668template <class Impl>
669void
670InstructionQueue<Impl>::addToOrderList(OpClass op_class)
671{
672 assert(!readyInsts[op_class].empty());
673
674 ListOrderEntry queue_entry;
675
676 queue_entry.queueType = op_class;
677
678 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
679
680 ListOrderIt list_it = listOrder.begin();
681 ListOrderIt list_end_it = listOrder.end();
682
683 while (list_it != list_end_it) {
684 if ((*list_it).oldestInst > queue_entry.oldestInst) {
685 break;
686 }
687
688 list_it++;
689 }
690
691 readyIt[op_class] = listOrder.insert(list_it, queue_entry);
692 queueOnList[op_class] = true;
693}
694
695template <class Impl>
696void
697InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it)
698{
699 // Get iterator of next item on the list
700 // Delete the original iterator
701 // Determine if the next item is either the end of the list or younger
702 // than the new instruction. If so, then add in a new iterator right here.
703 // If not, then move along.
704 ListOrderEntry queue_entry;
705 OpClass op_class = (*list_order_it).queueType;
706 ListOrderIt next_it = list_order_it;
707
708 ++next_it;
709
710 queue_entry.queueType = op_class;
711 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
712
713 while (next_it != listOrder.end() &&
714 (*next_it).oldestInst < queue_entry.oldestInst) {
715 ++next_it;
716 }
717
718 readyIt[op_class] = listOrder.insert(next_it, queue_entry);
719}
720
721template <class Impl>
722void
723InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx)
724{
725 DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum);
726 assert(!cpu->switchedOut());
727 // The CPU could have been sleeping until this op completed (*extremely*
728 // long latency op). Wake it if it was. This may be overkill.
729 --wbOutstanding;
730 iewStage->wakeCPU();
731
732 if (fu_idx > -1)
733 fuPool->freeUnitNextCycle(fu_idx);
734
735 // @todo: Ensure that these FU Completions happen at the beginning
736 // of a cycle, otherwise they could add too many instructions to
737 // the queue.
738 issueToExecuteQueue->access(-1)->size++;
739 instsToExecute.push_back(inst);
740}
741
742// @todo: Figure out a better way to remove the squashed items from the
743// lists. Checking the top item of each list to see if it's squashed
744// wastes time and forces jumps.
745template <class Impl>
746void
747InstructionQueue<Impl>::scheduleReadyInsts()
748{
749 DPRINTF(IQ, "Attempting to schedule ready instructions from "
750 "the IQ.\n");
751
752 IssueStruct *i2e_info = issueToExecuteQueue->access(0);
753
754 DynInstPtr mem_inst;
755 while (mem_inst = getDeferredMemInstToExecute()) {
756 addReadyMemInst(mem_inst);
757 }
758
759 // See if any cache blocked instructions are able to be executed
760 while (mem_inst = getBlockedMemInstToExecute()) {
761 addReadyMemInst(mem_inst);
762 }
763
764 // Have iterator to head of the list
765 // While I haven't exceeded bandwidth or reached the end of the list,
766 // Try to get a FU that can do what this op needs.
767 // If successful, change the oldestInst to the new top of the list, put
768 // the queue in the proper place in the list.
769 // Increment the iterator.
770 // This will avoid trying to schedule a certain op class if there are no
771 // FUs that handle it.
772 int total_issued = 0;
773 ListOrderIt order_it = listOrder.begin();
774 ListOrderIt order_end_it = listOrder.end();
775
776 while (total_issued < totalWidth && order_it != order_end_it) {
777 OpClass op_class = (*order_it).queueType;
778
779 assert(!readyInsts[op_class].empty());
780
781 DynInstPtr issuing_inst = readyInsts[op_class].top();
782
783 issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++;
784
785 assert(issuing_inst->seqNum == (*order_it).oldestInst);
786
787 if (issuing_inst->isSquashed()) {
788 readyInsts[op_class].pop();
789
790 if (!readyInsts[op_class].empty()) {
791 moveToYoungerInst(order_it);
792 } else {
793 readyIt[op_class] = listOrder.end();
794 queueOnList[op_class] = false;
795 }
796
797 listOrder.erase(order_it++);
798
799 ++iqSquashedInstsIssued;
800
801 continue;
802 }
803
804 int idx = -2;
805 Cycles op_latency = Cycles(1);
806 ThreadID tid = issuing_inst->threadNumber;
807
808 if (op_class != No_OpClass) {
809 idx = fuPool->getUnit(op_class);
810 issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++;
811 if (idx > -1) {
812 op_latency = fuPool->getOpLatency(op_class);
813 }
814 }
815
816 // If we have an instruction that doesn't require a FU, or a
817 // valid FU, then schedule for execution.
818 if (idx == -2 || idx != -1) {
819 if (op_latency == Cycles(1)) {
820 i2e_info->size++;
821 instsToExecute.push_back(issuing_inst);
822
823 // Add the FU onto the list of FU's to be freed next
824 // cycle if we used one.
825 if (idx >= 0)
826 fuPool->freeUnitNextCycle(idx);
827 } else {
828 Cycles issue_latency = fuPool->getIssueLatency(op_class);
829 // Generate completion event for the FU
830 ++wbOutstanding;
831 FUCompletion *execution = new FUCompletion(issuing_inst,
832 idx, this);
833
834 cpu->schedule(execution,
835 cpu->clockEdge(Cycles(op_latency - 1)));
836
837 // @todo: Enforce that issue_latency == 1 or op_latency
838 if (issue_latency > Cycles(1)) {
839 // If FU isn't pipelined, then it must be freed
840 // upon the execution completing.
841 execution->setFreeFU();
842 } else {
843 // Add the FU onto the list of FU's to be freed next cycle.
844 fuPool->freeUnitNextCycle(idx);
845 }
846 }
847
848 DPRINTF(IQ, "Thread %i: Issuing instruction PC %s "
849 "[sn:%lli]\n",
850 tid, issuing_inst->pcState(),
851 issuing_inst->seqNum);
852
853 readyInsts[op_class].pop();
854
855 if (!readyInsts[op_class].empty()) {
856 moveToYoungerInst(order_it);
857 } else {
858 readyIt[op_class] = listOrder.end();
859 queueOnList[op_class] = false;
860 }
861
862 issuing_inst->setIssued();
863 ++total_issued;
864
865#if TRACING_ON
866 issuing_inst->issueTick = curTick() - issuing_inst->fetchTick;
867#endif
868
869 if (!issuing_inst->isMemRef()) {
870 // Memory instructions can not be freed from the IQ until they
871 // complete.
872 ++freeEntries;
873 count[tid]--;
874 issuing_inst->clearInIQ();
875 } else {
876 memDepUnit[tid].issue(issuing_inst);
877 }
878
879 listOrder.erase(order_it++);
880 statIssuedInstType[tid][op_class]++;
881 } else {
882 statFuBusy[op_class]++;
883 fuBusy[tid]++;
884 ++order_it;
885 }
886 }
887
888 numIssuedDist.sample(total_issued);
889 iqInstsIssued+= total_issued;
890
891 // If we issued any instructions, tell the CPU we had activity.
892 // @todo If the way deferred memory instructions are handeled due to
893 // translation changes then the deferredMemInsts condition should be removed
894 // from the code below.
895 if (total_issued || !retryMemInsts.empty() || !deferredMemInsts.empty()) {
896 cpu->activityThisCycle();
897 } else {
898 DPRINTF(IQ, "Not able to schedule any instructions.\n");
899 }
900}
901
902template <class Impl>
903void
904InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
905{
906 DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready "
907 "to execute.\n", inst);
908
909 NonSpecMapIt inst_it = nonSpecInsts.find(inst);
910
911 assert(inst_it != nonSpecInsts.end());
912
913 ThreadID tid = (*inst_it).second->threadNumber;
914
915 (*inst_it).second->setAtCommit();
916
917 (*inst_it).second->setCanIssue();
918
919 if (!(*inst_it).second->isMemRef()) {
920 addIfReady((*inst_it).second);
921 } else {
922 memDepUnit[tid].nonSpecInstReady((*inst_it).second);
923 }
924
925 (*inst_it).second = NULL;
926
927 nonSpecInsts.erase(inst_it);
928}
929
930template <class Impl>
931void
932InstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid)
933{
934 DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n",
935 tid,inst);
936
937 ListIt iq_it = instList[tid].begin();
938
939 while (iq_it != instList[tid].end() &&
940 (*iq_it)->seqNum <= inst) {
941 ++iq_it;
942 instList[tid].pop_front();
943 }
944
945 assert(freeEntries == (numEntries - countInsts()));
946}
947
948template <class Impl>
949int
950InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
951{
952 int dependents = 0;
953
954 // The instruction queue here takes care of both floating and int ops
955 if (completed_inst->isFloating()) {
956 fpInstQueueWakeupQccesses++;
957 } else {
958 intInstQueueWakeupAccesses++;
959 }
960
961 DPRINTF(IQ, "Waking dependents of completed instruction.\n");
962
963 assert(!completed_inst->isSquashed());
964
965 // Tell the memory dependence unit to wake any dependents on this
966 // instruction if it is a memory instruction. Also complete the memory
967 // instruction at this point since we know it executed without issues.
968 // @todo: Might want to rename "completeMemInst" to something that
969 // indicates that it won't need to be replayed, and call this
970 // earlier. Might not be a big deal.
971 if (completed_inst->isMemRef()) {
972 memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst);
973 completeMemInst(completed_inst);
974 } else if (completed_inst->isMemBarrier() ||
975 completed_inst->isWriteBarrier()) {
976 memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst);
977 }
978
979 for (int dest_reg_idx = 0;
980 dest_reg_idx < completed_inst->numDestRegs();
981 dest_reg_idx++)
982 {
983 PhysRegIndex dest_reg =
984 completed_inst->renamedDestRegIdx(dest_reg_idx);
985
986 // Special case of uniq or control registers. They are not
987 // handled by the IQ and thus have no dependency graph entry.
988 // @todo Figure out a cleaner way to handle this.
989 if (dest_reg >= numPhysRegs) {
990 DPRINTF(IQ, "dest_reg :%d, numPhysRegs: %d\n", dest_reg,
991 numPhysRegs);
992 continue;
993 }
994
995 DPRINTF(IQ, "Waking any dependents on register %i.\n",
996 (int) dest_reg);
997
998 //Go through the dependency chain, marking the registers as
999 //ready within the waiting instructions.
1000 DynInstPtr dep_inst = dependGraph.pop(dest_reg);
1001
1002 while (dep_inst) {
1003 DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] "
1004 "PC %s.\n", dep_inst->seqNum, dep_inst->pcState());
1005
1006 // Might want to give more information to the instruction
1007 // so that it knows which of its source registers is
1008 // ready. However that would mean that the dependency
1009 // graph entries would need to hold the src_reg_idx.
1010 dep_inst->markSrcRegReady();
1011
1012 addIfReady(dep_inst);
1013
1014 dep_inst = dependGraph.pop(dest_reg);
1015
1016 ++dependents;
1017 }
1018
1019 // Reset the head node now that all of its dependents have
1020 // been woken up.
1021 assert(dependGraph.empty(dest_reg));
1022 dependGraph.clearInst(dest_reg);
1023
1024 // Mark the scoreboard as having that register ready.
1025 regScoreboard[dest_reg] = true;
1026 }
1027 return dependents;
1028}
1029
1030template <class Impl>
1031void
1032InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst)
1033{
1034 OpClass op_class = ready_inst->opClass();
1035
1036 readyInsts[op_class].push(ready_inst);
1037
1038 // Will need to reorder the list if either a queue is not on the list,
1039 // or it has an older instruction than last time.
1040 if (!queueOnList[op_class]) {
1041 addToOrderList(op_class);
1042 } else if (readyInsts[op_class].top()->seqNum <
1043 (*readyIt[op_class]).oldestInst) {
1044 listOrder.erase(readyIt[op_class]);
1045 addToOrderList(op_class);
1046 }
1047
1048 DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1049 "the ready list, PC %s opclass:%i [sn:%lli].\n",
1050 ready_inst->pcState(), op_class, ready_inst->seqNum);
1051}
1052
1053template <class Impl>
1054void
1055InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst)
1056{
1057 DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum);
1058
1059 // Reset DTB translation state
1060 resched_inst->translationStarted(false);
1061 resched_inst->translationCompleted(false);
1062
1063 resched_inst->clearCanIssue();
1064 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
1065}
1066
1067template <class Impl>
1068void
1069InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst)
1070{
1071 memDepUnit[replay_inst->threadNumber].replay();
1072}
1073
1074template <class Impl>
1075void
1076InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst)
1077{
1078 ThreadID tid = completed_inst->threadNumber;
1079
1080 DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n",
1081 completed_inst->pcState(), completed_inst->seqNum);
1082
1083 ++freeEntries;
1084
1085 completed_inst->memOpDone(true);
1086
1087 memDepUnit[tid].completed(completed_inst);
1088 count[tid]--;
1089}
1090
1091template <class Impl>
1092void
1093InstructionQueue<Impl>::deferMemInst(DynInstPtr &deferred_inst)
1094{
1095 deferredMemInsts.push_back(deferred_inst);
1096}
1097
1098template <class Impl>
1099void
1100InstructionQueue<Impl>::blockMemInst(DynInstPtr &blocked_inst)
1101{
1102 blocked_inst->translationStarted(false);
1103 blocked_inst->translationCompleted(false);
1104
1105 blocked_inst->clearIssued();
1106 blocked_inst->clearCanIssue();
1107 blockedMemInsts.push_back(blocked_inst);
1108}
1109
1110template <class Impl>
1111void
1112InstructionQueue<Impl>::cacheUnblocked()
1113{
1114 retryMemInsts.splice(retryMemInsts.end(), blockedMemInsts);
1115 // Get the CPU ticking again
1116 cpu->wakeCPU();
1117}
1118
1119template <class Impl>
1120typename Impl::DynInstPtr
1121InstructionQueue<Impl>::getDeferredMemInstToExecute()
1122{
1123 for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end();
1124 ++it) {
1125 if ((*it)->translationCompleted() || (*it)->isSquashed()) {
1126 DynInstPtr mem_inst = *it;
1127 deferredMemInsts.erase(it);
1128 return mem_inst;
1129 }
1130 }
1131 return nullptr;
1132}
1133
1134template <class Impl>
1135typename Impl::DynInstPtr
1136InstructionQueue<Impl>::getBlockedMemInstToExecute()
1137{
1138 if (retryMemInsts.empty()) {
1139 return nullptr;
1140 } else {
1141 DynInstPtr mem_inst = retryMemInsts.front();
1142 retryMemInsts.pop_front();
1143 return mem_inst;
1144 }
1145}
1146
1147template <class Impl>
1148void
1149InstructionQueue<Impl>::violation(DynInstPtr &store,
1150 DynInstPtr &faulting_load)
1151{
1152 intInstQueueWrites++;
1153 memDepUnit[store->threadNumber].violation(store, faulting_load);
1154}
1155
1156template <class Impl>
1157void
1158InstructionQueue<Impl>::squash(ThreadID tid)
1159{
1160 DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in "
1161 "the IQ.\n", tid);
1162
1163 // Read instruction sequence number of last instruction out of the
1164 // time buffer.
1165 squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
1166
|
1171
1172 // Also tell the memory dependence unit to squash.
1173 memDepUnit[tid].squash(squashedSeqNum[tid], tid);
1174}
1175
1176template <class Impl>
1177void
1178InstructionQueue<Impl>::doSquash(ThreadID tid)
1179{
1180 // Start at the tail.
1181 ListIt squash_it = instList[tid].end();
1182 --squash_it;
1183
1184 DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n",
1185 tid, squashedSeqNum[tid]);
1186
1187 // Squash any instructions younger than the squashed sequence number
1188 // given.
1189 while (squash_it != instList[tid].end() &&
1190 (*squash_it)->seqNum > squashedSeqNum[tid]) {
1191
1192 DynInstPtr squashed_inst = (*squash_it);
1193 squashed_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
1194
1195 // Only handle the instruction if it actually is in the IQ and
1196 // hasn't already been squashed in the IQ.
1197 if (squashed_inst->threadNumber != tid ||
1198 squashed_inst->isSquashedInIQ()) {
1199 --squash_it;
1200 continue;
1201 }
1202
1203 if (!squashed_inst->isIssued() ||
1204 (squashed_inst->isMemRef() &&
1205 !squashed_inst->memOpDone())) {
1206
1207 DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n",
1208 tid, squashed_inst->seqNum, squashed_inst->pcState());
1209
1210 bool is_acq_rel = squashed_inst->isMemBarrier() &&
1211 (squashed_inst->isLoad() ||
1212 (squashed_inst->isStore() &&
1213 !squashed_inst->isStoreConditional()));
1214
1215 // Remove the instruction from the dependency list.
1216 if (is_acq_rel ||
1217 (!squashed_inst->isNonSpeculative() &&
1218 !squashed_inst->isStoreConditional() &&
1219 !squashed_inst->isMemBarrier() &&
1220 !squashed_inst->isWriteBarrier())) {
1221
1222 for (int src_reg_idx = 0;
1223 src_reg_idx < squashed_inst->numSrcRegs();
1224 src_reg_idx++)
1225 {
1226 PhysRegIndex src_reg =
1227 squashed_inst->renamedSrcRegIdx(src_reg_idx);
1228
1229 // Only remove it from the dependency graph if it
1230 // was placed there in the first place.
1231
1232 // Instead of doing a linked list traversal, we
1233 // can just remove these squashed instructions
1234 // either at issue time, or when the register is
1235 // overwritten. The only downside to this is it
1236 // leaves more room for error.
1237
1238 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) &&
1239 src_reg < numPhysRegs) {
1240 dependGraph.remove(src_reg, squashed_inst);
1241 }
1242
1243
1244 ++iqSquashedOperandsExamined;
1245 }
1246 } else if (!squashed_inst->isStoreConditional() ||
1247 !squashed_inst->isCompleted()) {
1248 NonSpecMapIt ns_inst_it =
1249 nonSpecInsts.find(squashed_inst->seqNum);
1250
1251 // we remove non-speculative instructions from
1252 // nonSpecInsts already when they are ready, and so we
1253 // cannot always expect to find them
1254 if (ns_inst_it == nonSpecInsts.end()) {
1255 // loads that became ready but stalled on a
1256 // blocked cache are alreayd removed from
1257 // nonSpecInsts, and have not faulted
1258 assert(squashed_inst->getFault() != NoFault ||
1259 squashed_inst->isMemRef());
1260 } else {
1261
1262 (*ns_inst_it).second = NULL;
1263
1264 nonSpecInsts.erase(ns_inst_it);
1265
1266 ++iqSquashedNonSpecRemoved;
1267 }
1268 }
1269
1270 // Might want to also clear out the head of the dependency graph.
1271
1272 // Mark it as squashed within the IQ.
1273 squashed_inst->setSquashedInIQ();
1274
1275 // @todo: Remove this hack where several statuses are set so the
1276 // inst will flow through the rest of the pipeline.
1277 squashed_inst->setIssued();
1278 squashed_inst->setCanCommit();
1279 squashed_inst->clearInIQ();
1280
1281 //Update Thread IQ Count
1282 count[squashed_inst->threadNumber]--;
1283
1284 ++freeEntries;
1285 }
1286
1287 instList[tid].erase(squash_it--);
1288 ++iqSquashedInstsExamined;
1289 }
1290}
1291
1292template <class Impl>
1293bool
1294InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst)
1295{
1296 // Loop through the instruction's source registers, adding
1297 // them to the dependency list if they are not ready.
1298 int8_t total_src_regs = new_inst->numSrcRegs();
1299 bool return_val = false;
1300
1301 for (int src_reg_idx = 0;
1302 src_reg_idx < total_src_regs;
1303 src_reg_idx++)
1304 {
1305 // Only add it to the dependency graph if it's not ready.
1306 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) {
1307 PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx);
1308
1309 // Check the IQ's scoreboard to make sure the register
1310 // hasn't become ready while the instruction was in flight
1311 // between stages. Only if it really isn't ready should
1312 // it be added to the dependency graph.
1313 if (src_reg >= numPhysRegs) {
1314 continue;
1315 } else if (!regScoreboard[src_reg]) {
1316 DPRINTF(IQ, "Instruction PC %s has src reg %i that "
1317 "is being added to the dependency chain.\n",
1318 new_inst->pcState(), src_reg);
1319
1320 dependGraph.insert(src_reg, new_inst);
1321
1322 // Change the return value to indicate that something
1323 // was added to the dependency graph.
1324 return_val = true;
1325 } else {
1326 DPRINTF(IQ, "Instruction PC %s has src reg %i that "
1327 "became ready before it reached the IQ.\n",
1328 new_inst->pcState(), src_reg);
1329 // Mark a register ready within the instruction.
1330 new_inst->markSrcRegReady(src_reg_idx);
1331 }
1332 }
1333 }
1334
1335 return return_val;
1336}
1337
1338template <class Impl>
1339void
1340InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst)
1341{
1342 // Nothing really needs to be marked when an instruction becomes
1343 // the producer of a register's value, but for convenience a ptr
1344 // to the producing instruction will be placed in the head node of
1345 // the dependency links.
1346 int8_t total_dest_regs = new_inst->numDestRegs();
1347
1348 for (int dest_reg_idx = 0;
1349 dest_reg_idx < total_dest_regs;
1350 dest_reg_idx++)
1351 {
1352 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx);
1353
1354 // Instructions that use the misc regs will have a reg number
1355 // higher than the normal physical registers. In this case these
1356 // registers are not renamed, and there is no need to track
1357 // dependencies as these instructions must be executed at commit.
1358 if (dest_reg >= numPhysRegs) {
1359 continue;
1360 }
1361
1362 if (!dependGraph.empty(dest_reg)) {
1363 dependGraph.dump();
1364 panic("Dependency graph %i not empty!", dest_reg);
1365 }
1366
1367 dependGraph.setInst(dest_reg, new_inst);
1368
1369 // Mark the scoreboard to say it's not yet ready.
1370 regScoreboard[dest_reg] = false;
1371 }
1372}
1373
1374template <class Impl>
1375void
1376InstructionQueue<Impl>::addIfReady(DynInstPtr &inst)
1377{
1378 // If the instruction now has all of its source registers
1379 // available, then add it to the list of ready instructions.
1380 if (inst->readyToIssue()) {
1381
1382 //Add the instruction to the proper ready list.
1383 if (inst->isMemRef()) {
1384
1385 DPRINTF(IQ, "Checking if memory instruction can issue.\n");
1386
1387 // Message to the mem dependence unit that this instruction has
1388 // its registers ready.
1389 memDepUnit[inst->threadNumber].regsReady(inst);
1390
1391 return;
1392 }
1393
1394 OpClass op_class = inst->opClass();
1395
1396 DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1397 "the ready list, PC %s opclass:%i [sn:%lli].\n",
1398 inst->pcState(), op_class, inst->seqNum);
1399
1400 readyInsts[op_class].push(inst);
1401
1402 // Will need to reorder the list if either a queue is not on the list,
1403 // or it has an older instruction than last time.
1404 if (!queueOnList[op_class]) {
1405 addToOrderList(op_class);
1406 } else if (readyInsts[op_class].top()->seqNum <
1407 (*readyIt[op_class]).oldestInst) {
1408 listOrder.erase(readyIt[op_class]);
1409 addToOrderList(op_class);
1410 }
1411 }
1412}
1413
1414template <class Impl>
1415int
1416InstructionQueue<Impl>::countInsts()
1417{
1418#if 0
1419 //ksewell:This works but definitely could use a cleaner write
1420 //with a more intuitive way of counting. Right now it's
1421 //just brute force ....
1422 // Change the #if if you want to use this method.
1423 int total_insts = 0;
1424
1425 for (ThreadID tid = 0; tid < numThreads; ++tid) {
1426 ListIt count_it = instList[tid].begin();
1427
1428 while (count_it != instList[tid].end()) {
1429 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) {
1430 if (!(*count_it)->isIssued()) {
1431 ++total_insts;
1432 } else if ((*count_it)->isMemRef() &&
1433 !(*count_it)->memOpDone) {
1434 // Loads that have not been marked as executed still count
1435 // towards the total instructions.
1436 ++total_insts;
1437 }
1438 }
1439
1440 ++count_it;
1441 }
1442 }
1443
1444 return total_insts;
1445#else
1446 return numEntries - freeEntries;
1447#endif
1448}
1449
1450template <class Impl>
1451void
1452InstructionQueue<Impl>::dumpLists()
1453{
1454 for (int i = 0; i < Num_OpClasses; ++i) {
1455 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size());
1456
1457 cprintf("\n");
1458 }
1459
1460 cprintf("Non speculative list size: %i\n", nonSpecInsts.size());
1461
1462 NonSpecMapIt non_spec_it = nonSpecInsts.begin();
1463 NonSpecMapIt non_spec_end_it = nonSpecInsts.end();
1464
1465 cprintf("Non speculative list: ");
1466
1467 while (non_spec_it != non_spec_end_it) {
1468 cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(),
1469 (*non_spec_it).second->seqNum);
1470 ++non_spec_it;
1471 }
1472
1473 cprintf("\n");
1474
1475 ListOrderIt list_order_it = listOrder.begin();
1476 ListOrderIt list_order_end_it = listOrder.end();
1477 int i = 1;
1478
1479 cprintf("List order: ");
1480
1481 while (list_order_it != list_order_end_it) {
1482 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType,
1483 (*list_order_it).oldestInst);
1484
1485 ++list_order_it;
1486 ++i;
1487 }
1488
1489 cprintf("\n");
1490}
1491
1492
1493template <class Impl>
1494void
1495InstructionQueue<Impl>::dumpInsts()
1496{
1497 for (ThreadID tid = 0; tid < numThreads; ++tid) {
1498 int num = 0;
1499 int valid_num = 0;
1500 ListIt inst_list_it = instList[tid].begin();
1501
1502 while (inst_list_it != instList[tid].end()) {
1503 cprintf("Instruction:%i\n", num);
1504 if (!(*inst_list_it)->isSquashed()) {
1505 if (!(*inst_list_it)->isIssued()) {
1506 ++valid_num;
1507 cprintf("Count:%i\n", valid_num);
1508 } else if ((*inst_list_it)->isMemRef() &&
1509 !(*inst_list_it)->memOpDone()) {
1510 // Loads that have not been marked as executed
1511 // still count towards the total instructions.
1512 ++valid_num;
1513 cprintf("Count:%i\n", valid_num);
1514 }
1515 }
1516
1517 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n"
1518 "Issued:%i\nSquashed:%i\n",
1519 (*inst_list_it)->pcState(),
1520 (*inst_list_it)->seqNum,
1521 (*inst_list_it)->threadNumber,
1522 (*inst_list_it)->isIssued(),
1523 (*inst_list_it)->isSquashed());
1524
1525 if ((*inst_list_it)->isMemRef()) {
1526 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone());
1527 }
1528
1529 cprintf("\n");
1530
1531 inst_list_it++;
1532 ++num;
1533 }
1534 }
1535
1536 cprintf("Insts to Execute list:\n");
1537
1538 int num = 0;
1539 int valid_num = 0;
1540 ListIt inst_list_it = instsToExecute.begin();
1541
1542 while (inst_list_it != instsToExecute.end())
1543 {
1544 cprintf("Instruction:%i\n",
1545 num);
1546 if (!(*inst_list_it)->isSquashed()) {
1547 if (!(*inst_list_it)->isIssued()) {
1548 ++valid_num;
1549 cprintf("Count:%i\n", valid_num);
1550 } else if ((*inst_list_it)->isMemRef() &&
1551 !(*inst_list_it)->memOpDone()) {
1552 // Loads that have not been marked as executed
1553 // still count towards the total instructions.
1554 ++valid_num;
1555 cprintf("Count:%i\n", valid_num);
1556 }
1557 }
1558
1559 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n"
1560 "Issued:%i\nSquashed:%i\n",
1561 (*inst_list_it)->pcState(),
1562 (*inst_list_it)->seqNum,
1563 (*inst_list_it)->threadNumber,
1564 (*inst_list_it)->isIssued(),
1565 (*inst_list_it)->isSquashed());
1566
1567 if ((*inst_list_it)->isMemRef()) {
1568 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone());
1569 }
1570
1571 cprintf("\n");
1572
1573 inst_list_it++;
1574 ++num;
1575 }
1576}
1577
1578#endif//__CPU_O3_INST_QUEUE_IMPL_HH__
| 1168
1169 // Also tell the memory dependence unit to squash.
1170 memDepUnit[tid].squash(squashedSeqNum[tid], tid);
1171}
1172
1173template <class Impl>
1174void
1175InstructionQueue<Impl>::doSquash(ThreadID tid)
1176{
1177 // Start at the tail.
1178 ListIt squash_it = instList[tid].end();
1179 --squash_it;
1180
1181 DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n",
1182 tid, squashedSeqNum[tid]);
1183
1184 // Squash any instructions younger than the squashed sequence number
1185 // given.
1186 while (squash_it != instList[tid].end() &&
1187 (*squash_it)->seqNum > squashedSeqNum[tid]) {
1188
1189 DynInstPtr squashed_inst = (*squash_it);
1190 squashed_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
1191
1192 // Only handle the instruction if it actually is in the IQ and
1193 // hasn't already been squashed in the IQ.
1194 if (squashed_inst->threadNumber != tid ||
1195 squashed_inst->isSquashedInIQ()) {
1196 --squash_it;
1197 continue;
1198 }
1199
1200 if (!squashed_inst->isIssued() ||
1201 (squashed_inst->isMemRef() &&
1202 !squashed_inst->memOpDone())) {
1203
1204 DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n",
1205 tid, squashed_inst->seqNum, squashed_inst->pcState());
1206
1207 bool is_acq_rel = squashed_inst->isMemBarrier() &&
1208 (squashed_inst->isLoad() ||
1209 (squashed_inst->isStore() &&
1210 !squashed_inst->isStoreConditional()));
1211
1212 // Remove the instruction from the dependency list.
1213 if (is_acq_rel ||
1214 (!squashed_inst->isNonSpeculative() &&
1215 !squashed_inst->isStoreConditional() &&
1216 !squashed_inst->isMemBarrier() &&
1217 !squashed_inst->isWriteBarrier())) {
1218
1219 for (int src_reg_idx = 0;
1220 src_reg_idx < squashed_inst->numSrcRegs();
1221 src_reg_idx++)
1222 {
1223 PhysRegIndex src_reg =
1224 squashed_inst->renamedSrcRegIdx(src_reg_idx);
1225
1226 // Only remove it from the dependency graph if it
1227 // was placed there in the first place.
1228
1229 // Instead of doing a linked list traversal, we
1230 // can just remove these squashed instructions
1231 // either at issue time, or when the register is
1232 // overwritten. The only downside to this is it
1233 // leaves more room for error.
1234
1235 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) &&
1236 src_reg < numPhysRegs) {
1237 dependGraph.remove(src_reg, squashed_inst);
1238 }
1239
1240
1241 ++iqSquashedOperandsExamined;
1242 }
1243 } else if (!squashed_inst->isStoreConditional() ||
1244 !squashed_inst->isCompleted()) {
1245 NonSpecMapIt ns_inst_it =
1246 nonSpecInsts.find(squashed_inst->seqNum);
1247
1248 // we remove non-speculative instructions from
1249 // nonSpecInsts already when they are ready, and so we
1250 // cannot always expect to find them
1251 if (ns_inst_it == nonSpecInsts.end()) {
1252 // loads that became ready but stalled on a
1253 // blocked cache are alreayd removed from
1254 // nonSpecInsts, and have not faulted
1255 assert(squashed_inst->getFault() != NoFault ||
1256 squashed_inst->isMemRef());
1257 } else {
1258
1259 (*ns_inst_it).second = NULL;
1260
1261 nonSpecInsts.erase(ns_inst_it);
1262
1263 ++iqSquashedNonSpecRemoved;
1264 }
1265 }
1266
1267 // Might want to also clear out the head of the dependency graph.
1268
1269 // Mark it as squashed within the IQ.
1270 squashed_inst->setSquashedInIQ();
1271
1272 // @todo: Remove this hack where several statuses are set so the
1273 // inst will flow through the rest of the pipeline.
1274 squashed_inst->setIssued();
1275 squashed_inst->setCanCommit();
1276 squashed_inst->clearInIQ();
1277
1278 //Update Thread IQ Count
1279 count[squashed_inst->threadNumber]--;
1280
1281 ++freeEntries;
1282 }
1283
1284 instList[tid].erase(squash_it--);
1285 ++iqSquashedInstsExamined;
1286 }
1287}
1288
1289template <class Impl>
1290bool
1291InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst)
1292{
1293 // Loop through the instruction's source registers, adding
1294 // them to the dependency list if they are not ready.
1295 int8_t total_src_regs = new_inst->numSrcRegs();
1296 bool return_val = false;
1297
1298 for (int src_reg_idx = 0;
1299 src_reg_idx < total_src_regs;
1300 src_reg_idx++)
1301 {
1302 // Only add it to the dependency graph if it's not ready.
1303 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) {
1304 PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx);
1305
1306 // Check the IQ's scoreboard to make sure the register
1307 // hasn't become ready while the instruction was in flight
1308 // between stages. Only if it really isn't ready should
1309 // it be added to the dependency graph.
1310 if (src_reg >= numPhysRegs) {
1311 continue;
1312 } else if (!regScoreboard[src_reg]) {
1313 DPRINTF(IQ, "Instruction PC %s has src reg %i that "
1314 "is being added to the dependency chain.\n",
1315 new_inst->pcState(), src_reg);
1316
1317 dependGraph.insert(src_reg, new_inst);
1318
1319 // Change the return value to indicate that something
1320 // was added to the dependency graph.
1321 return_val = true;
1322 } else {
1323 DPRINTF(IQ, "Instruction PC %s has src reg %i that "
1324 "became ready before it reached the IQ.\n",
1325 new_inst->pcState(), src_reg);
1326 // Mark a register ready within the instruction.
1327 new_inst->markSrcRegReady(src_reg_idx);
1328 }
1329 }
1330 }
1331
1332 return return_val;
1333}
1334
1335template <class Impl>
1336void
1337InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst)
1338{
1339 // Nothing really needs to be marked when an instruction becomes
1340 // the producer of a register's value, but for convenience a ptr
1341 // to the producing instruction will be placed in the head node of
1342 // the dependency links.
1343 int8_t total_dest_regs = new_inst->numDestRegs();
1344
1345 for (int dest_reg_idx = 0;
1346 dest_reg_idx < total_dest_regs;
1347 dest_reg_idx++)
1348 {
1349 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx);
1350
1351 // Instructions that use the misc regs will have a reg number
1352 // higher than the normal physical registers. In this case these
1353 // registers are not renamed, and there is no need to track
1354 // dependencies as these instructions must be executed at commit.
1355 if (dest_reg >= numPhysRegs) {
1356 continue;
1357 }
1358
1359 if (!dependGraph.empty(dest_reg)) {
1360 dependGraph.dump();
1361 panic("Dependency graph %i not empty!", dest_reg);
1362 }
1363
1364 dependGraph.setInst(dest_reg, new_inst);
1365
1366 // Mark the scoreboard to say it's not yet ready.
1367 regScoreboard[dest_reg] = false;
1368 }
1369}
1370
1371template <class Impl>
1372void
1373InstructionQueue<Impl>::addIfReady(DynInstPtr &inst)
1374{
1375 // If the instruction now has all of its source registers
1376 // available, then add it to the list of ready instructions.
1377 if (inst->readyToIssue()) {
1378
1379 //Add the instruction to the proper ready list.
1380 if (inst->isMemRef()) {
1381
1382 DPRINTF(IQ, "Checking if memory instruction can issue.\n");
1383
1384 // Message to the mem dependence unit that this instruction has
1385 // its registers ready.
1386 memDepUnit[inst->threadNumber].regsReady(inst);
1387
1388 return;
1389 }
1390
1391 OpClass op_class = inst->opClass();
1392
1393 DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1394 "the ready list, PC %s opclass:%i [sn:%lli].\n",
1395 inst->pcState(), op_class, inst->seqNum);
1396
1397 readyInsts[op_class].push(inst);
1398
1399 // Will need to reorder the list if either a queue is not on the list,
1400 // or it has an older instruction than last time.
1401 if (!queueOnList[op_class]) {
1402 addToOrderList(op_class);
1403 } else if (readyInsts[op_class].top()->seqNum <
1404 (*readyIt[op_class]).oldestInst) {
1405 listOrder.erase(readyIt[op_class]);
1406 addToOrderList(op_class);
1407 }
1408 }
1409}
1410
1411template <class Impl>
1412int
1413InstructionQueue<Impl>::countInsts()
1414{
1415#if 0
1416 //ksewell:This works but definitely could use a cleaner write
1417 //with a more intuitive way of counting. Right now it's
1418 //just brute force ....
1419 // Change the #if if you want to use this method.
1420 int total_insts = 0;
1421
1422 for (ThreadID tid = 0; tid < numThreads; ++tid) {
1423 ListIt count_it = instList[tid].begin();
1424
1425 while (count_it != instList[tid].end()) {
1426 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) {
1427 if (!(*count_it)->isIssued()) {
1428 ++total_insts;
1429 } else if ((*count_it)->isMemRef() &&
1430 !(*count_it)->memOpDone) {
1431 // Loads that have not been marked as executed still count
1432 // towards the total instructions.
1433 ++total_insts;
1434 }
1435 }
1436
1437 ++count_it;
1438 }
1439 }
1440
1441 return total_insts;
1442#else
1443 return numEntries - freeEntries;
1444#endif
1445}
1446
1447template <class Impl>
1448void
1449InstructionQueue<Impl>::dumpLists()
1450{
1451 for (int i = 0; i < Num_OpClasses; ++i) {
1452 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size());
1453
1454 cprintf("\n");
1455 }
1456
1457 cprintf("Non speculative list size: %i\n", nonSpecInsts.size());
1458
1459 NonSpecMapIt non_spec_it = nonSpecInsts.begin();
1460 NonSpecMapIt non_spec_end_it = nonSpecInsts.end();
1461
1462 cprintf("Non speculative list: ");
1463
1464 while (non_spec_it != non_spec_end_it) {
1465 cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(),
1466 (*non_spec_it).second->seqNum);
1467 ++non_spec_it;
1468 }
1469
1470 cprintf("\n");
1471
1472 ListOrderIt list_order_it = listOrder.begin();
1473 ListOrderIt list_order_end_it = listOrder.end();
1474 int i = 1;
1475
1476 cprintf("List order: ");
1477
1478 while (list_order_it != list_order_end_it) {
1479 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType,
1480 (*list_order_it).oldestInst);
1481
1482 ++list_order_it;
1483 ++i;
1484 }
1485
1486 cprintf("\n");
1487}
1488
1489
1490template <class Impl>
1491void
1492InstructionQueue<Impl>::dumpInsts()
1493{
1494 for (ThreadID tid = 0; tid < numThreads; ++tid) {
1495 int num = 0;
1496 int valid_num = 0;
1497 ListIt inst_list_it = instList[tid].begin();
1498
1499 while (inst_list_it != instList[tid].end()) {
1500 cprintf("Instruction:%i\n", num);
1501 if (!(*inst_list_it)->isSquashed()) {
1502 if (!(*inst_list_it)->isIssued()) {
1503 ++valid_num;
1504 cprintf("Count:%i\n", valid_num);
1505 } else if ((*inst_list_it)->isMemRef() &&
1506 !(*inst_list_it)->memOpDone()) {
1507 // Loads that have not been marked as executed
1508 // still count towards the total instructions.
1509 ++valid_num;
1510 cprintf("Count:%i\n", valid_num);
1511 }
1512 }
1513
1514 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n"
1515 "Issued:%i\nSquashed:%i\n",
1516 (*inst_list_it)->pcState(),
1517 (*inst_list_it)->seqNum,
1518 (*inst_list_it)->threadNumber,
1519 (*inst_list_it)->isIssued(),
1520 (*inst_list_it)->isSquashed());
1521
1522 if ((*inst_list_it)->isMemRef()) {
1523 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone());
1524 }
1525
1526 cprintf("\n");
1527
1528 inst_list_it++;
1529 ++num;
1530 }
1531 }
1532
1533 cprintf("Insts to Execute list:\n");
1534
1535 int num = 0;
1536 int valid_num = 0;
1537 ListIt inst_list_it = instsToExecute.begin();
1538
1539 while (inst_list_it != instsToExecute.end())
1540 {
1541 cprintf("Instruction:%i\n",
1542 num);
1543 if (!(*inst_list_it)->isSquashed()) {
1544 if (!(*inst_list_it)->isIssued()) {
1545 ++valid_num;
1546 cprintf("Count:%i\n", valid_num);
1547 } else if ((*inst_list_it)->isMemRef() &&
1548 !(*inst_list_it)->memOpDone()) {
1549 // Loads that have not been marked as executed
1550 // still count towards the total instructions.
1551 ++valid_num;
1552 cprintf("Count:%i\n", valid_num);
1553 }
1554 }
1555
1556 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n"
1557 "Issued:%i\nSquashed:%i\n",
1558 (*inst_list_it)->pcState(),
1559 (*inst_list_it)->seqNum,
1560 (*inst_list_it)->threadNumber,
1561 (*inst_list_it)->isIssued(),
1562 (*inst_list_it)->isSquashed());
1563
1564 if ((*inst_list_it)->isMemRef()) {
1565 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone());
1566 }
1567
1568 cprintf("\n");
1569
1570 inst_list_it++;
1571 ++num;
1572 }
1573}
1574
1575#endif//__CPU_O3_INST_QUEUE_IMPL_HH__
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