inst_queue_impl.hh (10231:cb2e6950956d) | inst_queue_impl.hh (10327:5b6279635c49) |
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1/* 2 * Copyright (c) 2011-2013 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 742 unchanged lines hidden (view full) --- 751 // Increment the iterator. 752 // This will avoid trying to schedule a certain op class if there are no 753 // FUs that handle it. 754 ListOrderIt order_it = listOrder.begin(); 755 ListOrderIt order_end_it = listOrder.end(); 756 int total_issued = 0; 757 758 while (total_issued < (totalWidth - total_deferred_mem_issued) && | 1/* 2 * Copyright (c) 2011-2013 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 742 unchanged lines hidden (view full) --- 751 // Increment the iterator. 752 // This will avoid trying to schedule a certain op class if there are no 753 // FUs that handle it. 754 ListOrderIt order_it = listOrder.begin(); 755 ListOrderIt order_end_it = listOrder.end(); 756 int total_issued = 0; 757 758 while (total_issued < (totalWidth - total_deferred_mem_issued) && |
759 iewStage->canIssue() && | |
760 order_it != order_end_it) { 761 OpClass op_class = (*order_it).queueType; 762 763 assert(!readyInsts[op_class].empty()); 764 765 DynInstPtr issuing_inst = readyInsts[op_class].top(); 766 767 issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++; --- 88 unchanged lines hidden (view full) --- 856 count[tid]--; 857 issuing_inst->clearInIQ(); 858 } else { 859 memDepUnit[tid].issue(issuing_inst); 860 } 861 862 listOrder.erase(order_it++); 863 statIssuedInstType[tid][op_class]++; | 759 order_it != order_end_it) { 760 OpClass op_class = (*order_it).queueType; 761 762 assert(!readyInsts[op_class].empty()); 763 764 DynInstPtr issuing_inst = readyInsts[op_class].top(); 765 766 issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++; --- 88 unchanged lines hidden (view full) --- 855 count[tid]--; 856 issuing_inst->clearInIQ(); 857 } else { 858 memDepUnit[tid].issue(issuing_inst); 859 } 860 861 listOrder.erase(order_it++); 862 statIssuedInstType[tid][op_class]++; |
864 iewStage->incrWb(issuing_inst->seqNum); | |
865 } else { 866 statFuBusy[op_class]++; 867 fuBusy[tid]++; 868 ++order_it; 869 } 870 } 871 872 numIssuedDist.sample(total_issued); --- 656 unchanged lines hidden --- | 863 } else { 864 statFuBusy[op_class]++; 865 fuBusy[tid]++; 866 ++order_it; 867 } 868 } 869 870 numIssuedDist.sample(total_issued); --- 656 unchanged lines hidden --- |