1/*
2 * Copyright (c) 2011-2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 */
44
45#ifndef __CPU_O3_INST_QUEUE_IMPL_HH__
46#define __CPU_O3_INST_QUEUE_IMPL_HH__
47
48#include <limits>
49#include <vector>
50
51#include "cpu/o3/fu_pool.hh"
52#include "cpu/o3/inst_queue.hh"
53#include "debug/IQ.hh"
54#include "enums/OpClass.hh"
55#include "params/DerivO3CPU.hh"
56#include "sim/core.hh"
57
58// clang complains about std::set being overloaded with Packet::set if
59// we open up the entire namespace std
60using std::list;
61
62template <class Impl>
63InstructionQueue<Impl>::FUCompletion::FUCompletion(const DynInstPtr &_inst,
64 int fu_idx, InstructionQueue<Impl> *iq_ptr)
65 : Event(Stat_Event_Pri, AutoDelete),
66 inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false)
67{
68}
69
70template <class Impl>
71void
72InstructionQueue<Impl>::FUCompletion::process()
73{
74 iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1);
75 inst = NULL;
76}
77
78
79template <class Impl>
80const char *
81InstructionQueue<Impl>::FUCompletion::description() const
82{
83 return "Functional unit completion";
84}
85
86template <class Impl>
87InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr,
88 DerivO3CPUParams *params)
89 : cpu(cpu_ptr),
90 iewStage(iew_ptr),
91 fuPool(params->fuPool),
92 numEntries(params->numIQEntries),
93 totalWidth(params->issueWidth),
94 commitToIEWDelay(params->commitToIEWDelay)
95{
96 assert(fuPool);
97
98 numThreads = params->numThreads;
99
100 // Set the number of total physical registers
101 // As the vector registers have two addressing modes, they are added twice
102 numPhysRegs = params->numPhysIntRegs + params->numPhysFloatRegs +
103 params->numPhysVecRegs +
104 params->numPhysVecRegs * TheISA::NumVecElemPerVecReg +
105 params->numPhysCCRegs;
106
107 //Create an entry for each physical register within the
108 //dependency graph.
109 dependGraph.resize(numPhysRegs);
110
111 // Resize the register scoreboard.
112 regScoreboard.resize(numPhysRegs);
113
114 //Initialize Mem Dependence Units
115 for (ThreadID tid = 0; tid < numThreads; tid++) {
116 memDepUnit[tid].init(params, tid);
117 memDepUnit[tid].setIQ(this);
118 }
119
120 resetState();
121
122 std::string policy = params->smtIQPolicy;
123
124 //Convert string to lowercase
125 std::transform(policy.begin(), policy.end(), policy.begin(),
126 (int(*)(int)) tolower);
127
128 //Figure out resource sharing policy
129 if (policy == "dynamic") {
130 iqPolicy = Dynamic;
131
132 //Set Max Entries to Total ROB Capacity
133 for (ThreadID tid = 0; tid < numThreads; tid++) {
134 maxEntries[tid] = numEntries;
135 }
136
137 } else if (policy == "partitioned") {
138 iqPolicy = Partitioned;
139
140 //@todo:make work if part_amt doesnt divide evenly.
141 int part_amt = numEntries / numThreads;
142
143 //Divide ROB up evenly
144 for (ThreadID tid = 0; tid < numThreads; tid++) {
145 maxEntries[tid] = part_amt;
146 }
147
148 DPRINTF(IQ, "IQ sharing policy set to Partitioned:"
149 "%i entries per thread.\n",part_amt);
150 } else if (policy == "threshold") {
151 iqPolicy = Threshold;
152
153 double threshold = (double)params->smtIQThreshold / 100;
154
155 int thresholdIQ = (int)((double)threshold * numEntries);
156
157 //Divide up by threshold amount
158 for (ThreadID tid = 0; tid < numThreads; tid++) {
159 maxEntries[tid] = thresholdIQ;
160 }
161
162 DPRINTF(IQ, "IQ sharing policy set to Threshold:"
163 "%i entries per thread.\n",thresholdIQ);
164 } else {
165 assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
166 "Partitioned, Threshold}");
167 }
168}
169
170template <class Impl>
171InstructionQueue<Impl>::~InstructionQueue()
172{
173 dependGraph.reset();
174#ifdef DEBUG
175 cprintf("Nodes traversed: %i, removed: %i\n",
176 dependGraph.nodesTraversed, dependGraph.nodesRemoved);
177#endif
178}
179
180template <class Impl>
181std::string
182InstructionQueue<Impl>::name() const
183{
184 return cpu->name() + ".iq";
185}
186
187template <class Impl>
188void
189InstructionQueue<Impl>::regStats()
190{
191 using namespace Stats;
192 iqInstsAdded
193 .name(name() + ".iqInstsAdded")
194 .desc("Number of instructions added to the IQ (excludes non-spec)")
195 .prereq(iqInstsAdded);
196
197 iqNonSpecInstsAdded
198 .name(name() + ".iqNonSpecInstsAdded")
199 .desc("Number of non-speculative instructions added to the IQ")
200 .prereq(iqNonSpecInstsAdded);
201
202 iqInstsIssued
203 .name(name() + ".iqInstsIssued")
204 .desc("Number of instructions issued")
205 .prereq(iqInstsIssued);
206
207 iqIntInstsIssued
208 .name(name() + ".iqIntInstsIssued")
209 .desc("Number of integer instructions issued")
210 .prereq(iqIntInstsIssued);
211
212 iqFloatInstsIssued
213 .name(name() + ".iqFloatInstsIssued")
214 .desc("Number of float instructions issued")
215 .prereq(iqFloatInstsIssued);
216
217 iqBranchInstsIssued
218 .name(name() + ".iqBranchInstsIssued")
219 .desc("Number of branch instructions issued")
220 .prereq(iqBranchInstsIssued);
221
222 iqMemInstsIssued
223 .name(name() + ".iqMemInstsIssued")
224 .desc("Number of memory instructions issued")
225 .prereq(iqMemInstsIssued);
226
227 iqMiscInstsIssued
228 .name(name() + ".iqMiscInstsIssued")
229 .desc("Number of miscellaneous instructions issued")
230 .prereq(iqMiscInstsIssued);
231
232 iqSquashedInstsIssued
233 .name(name() + ".iqSquashedInstsIssued")
234 .desc("Number of squashed instructions issued")
235 .prereq(iqSquashedInstsIssued);
236
237 iqSquashedInstsExamined
238 .name(name() + ".iqSquashedInstsExamined")
239 .desc("Number of squashed instructions iterated over during squash;"
240 " mainly for profiling")
241 .prereq(iqSquashedInstsExamined);
242
243 iqSquashedOperandsExamined
244 .name(name() + ".iqSquashedOperandsExamined")
245 .desc("Number of squashed operands that are examined and possibly "
246 "removed from graph")
247 .prereq(iqSquashedOperandsExamined);
248
249 iqSquashedNonSpecRemoved
250 .name(name() + ".iqSquashedNonSpecRemoved")
251 .desc("Number of squashed non-spec instructions that were removed")
252 .prereq(iqSquashedNonSpecRemoved);
253/*
254 queueResDist
255 .init(Num_OpClasses, 0, 99, 2)
256 .name(name() + ".IQ:residence:")
257 .desc("cycles from dispatch to issue")
258 .flags(total | pdf | cdf )
259 ;
260 for (int i = 0; i < Num_OpClasses; ++i) {
261 queueResDist.subname(i, opClassStrings[i]);
262 }
263*/
264 numIssuedDist
265 .init(0,totalWidth,1)
266 .name(name() + ".issued_per_cycle")
267 .desc("Number of insts issued each cycle")
268 .flags(pdf)
269 ;
270/*
271 dist_unissued
272 .init(Num_OpClasses+2)
273 .name(name() + ".unissued_cause")
274 .desc("Reason ready instruction not issued")
275 .flags(pdf | dist)
276 ;
277 for (int i=0; i < (Num_OpClasses + 2); ++i) {
278 dist_unissued.subname(i, unissued_names[i]);
279 }
280*/
281 statIssuedInstType
282 .init(numThreads,Enums::Num_OpClass)
283 .name(name() + ".FU_type")
284 .desc("Type of FU issued")
285 .flags(total | pdf | dist)
286 ;
287 statIssuedInstType.ysubnames(Enums::OpClassStrings);
288
289 //
290 // How long did instructions for a particular FU type wait prior to issue
291 //
292/*
293 issueDelayDist
294 .init(Num_OpClasses,0,99,2)
295 .name(name() + ".")
296 .desc("cycles from operands ready to issue")
297 .flags(pdf | cdf)
298 ;
299
300 for (int i=0; i<Num_OpClasses; ++i) {
301 std::stringstream subname;
302 subname << opClassStrings[i] << "_delay";
303 issueDelayDist.subname(i, subname.str());
304 }
305*/
306 issueRate
307 .name(name() + ".rate")
308 .desc("Inst issue rate")
309 .flags(total)
310 ;
311 issueRate = iqInstsIssued / cpu->numCycles;
312
313 statFuBusy
314 .init(Num_OpClasses)
315 .name(name() + ".fu_full")
316 .desc("attempts to use FU when none available")
317 .flags(pdf | dist)
318 ;
319 for (int i=0; i < Num_OpClasses; ++i) {
320 statFuBusy.subname(i, Enums::OpClassStrings[i]);
321 }
322
323 fuBusy
324 .init(numThreads)
325 .name(name() + ".fu_busy_cnt")
326 .desc("FU busy when requested")
327 .flags(total)
328 ;
329
330 fuBusyRate
331 .name(name() + ".fu_busy_rate")
332 .desc("FU busy rate (busy events/executed inst)")
333 .flags(total)
334 ;
335 fuBusyRate = fuBusy / iqInstsIssued;
336
337 for (ThreadID tid = 0; tid < numThreads; tid++) {
338 // Tell mem dependence unit to reg stats as well.
339 memDepUnit[tid].regStats();
340 }
341
342 intInstQueueReads
343 .name(name() + ".int_inst_queue_reads")
344 .desc("Number of integer instruction queue reads")
345 .flags(total);
346
347 intInstQueueWrites
348 .name(name() + ".int_inst_queue_writes")
349 .desc("Number of integer instruction queue writes")
350 .flags(total);
351
352 intInstQueueWakeupAccesses
353 .name(name() + ".int_inst_queue_wakeup_accesses")
354 .desc("Number of integer instruction queue wakeup accesses")
355 .flags(total);
356
357 fpInstQueueReads
358 .name(name() + ".fp_inst_queue_reads")
359 .desc("Number of floating instruction queue reads")
360 .flags(total);
361
362 fpInstQueueWrites
363 .name(name() + ".fp_inst_queue_writes")
364 .desc("Number of floating instruction queue writes")
365 .flags(total);
366
367 fpInstQueueWakeupAccesses
368 .name(name() + ".fp_inst_queue_wakeup_accesses")
369 .desc("Number of floating instruction queue wakeup accesses")
370 .flags(total);
371
372 vecInstQueueReads
373 .name(name() + ".vec_inst_queue_reads")
374 .desc("Number of vector instruction queue reads")
375 .flags(total);
376
377 vecInstQueueWrites
378 .name(name() + ".vec_inst_queue_writes")
379 .desc("Number of vector instruction queue writes")
380 .flags(total);
381
382 vecInstQueueWakeupAccesses
383 .name(name() + ".vec_inst_queue_wakeup_accesses")
384 .desc("Number of vector instruction queue wakeup accesses")
385 .flags(total);
386
387 intAluAccesses
388 .name(name() + ".int_alu_accesses")
389 .desc("Number of integer alu accesses")
390 .flags(total);
391
392 fpAluAccesses
393 .name(name() + ".fp_alu_accesses")
394 .desc("Number of floating point alu accesses")
395 .flags(total);
396
397 vecAluAccesses
398 .name(name() + ".vec_alu_accesses")
399 .desc("Number of vector alu accesses")
400 .flags(total);
401
402}
403
404template <class Impl>
405void
406InstructionQueue<Impl>::resetState()
407{
408 //Initialize thread IQ counts
409 for (ThreadID tid = 0; tid <numThreads; tid++) {
410 count[tid] = 0;
411 instList[tid].clear();
412 }
413
414 // Initialize the number of free IQ entries.
415 freeEntries = numEntries;
416
417 // Note that in actuality, the registers corresponding to the logical
418 // registers start off as ready. However this doesn't matter for the
419 // IQ as the instruction should have been correctly told if those
420 // registers are ready in rename. Thus it can all be initialized as
421 // unready.
422 for (int i = 0; i < numPhysRegs; ++i) {
423 regScoreboard[i] = false;
424 }
425
426 for (ThreadID tid = 0; tid < numThreads; ++tid) {
427 squashedSeqNum[tid] = 0;
428 }
429
430 for (int i = 0; i < Num_OpClasses; ++i) {
431 while (!readyInsts[i].empty())
432 readyInsts[i].pop();
433 queueOnList[i] = false;
434 readyIt[i] = listOrder.end();
435 }
436 nonSpecInsts.clear();
437 listOrder.clear();
438 deferredMemInsts.clear();
439 blockedMemInsts.clear();
440 retryMemInsts.clear();
441 wbOutstanding = 0;
442}
443
444template <class Impl>
445void
446InstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
447{
448 activeThreads = at_ptr;
449}
450
451template <class Impl>
452void
453InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr)
454{
455 issueToExecuteQueue = i2e_ptr;
456}
457
458template <class Impl>
459void
460InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
461{
462 timeBuffer = tb_ptr;
463
464 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
465}
466
467template <class Impl>
468bool
469InstructionQueue<Impl>::isDrained() const
470{
471 bool drained = dependGraph.empty() &&
472 instsToExecute.empty() &&
473 wbOutstanding == 0;
474 for (ThreadID tid = 0; tid < numThreads; ++tid)
475 drained = drained && memDepUnit[tid].isDrained();
476
477 return drained;
478}
479
480template <class Impl>
481void
482InstructionQueue<Impl>::drainSanityCheck() const
483{
484 assert(dependGraph.empty());
485 assert(instsToExecute.empty());
486 for (ThreadID tid = 0; tid < numThreads; ++tid)
487 memDepUnit[tid].drainSanityCheck();
488}
489
490template <class Impl>
491void
492InstructionQueue<Impl>::takeOverFrom()
493{
494 resetState();
495}
496
497template <class Impl>
498int
499InstructionQueue<Impl>::entryAmount(ThreadID num_threads)
500{
501 if (iqPolicy == Partitioned) {
502 return numEntries / num_threads;
503 } else {
504 return 0;
505 }
506}
507
508
509template <class Impl>
510void
511InstructionQueue<Impl>::resetEntries()
512{
513 if (iqPolicy != Dynamic || numThreads > 1) {
514 int active_threads = activeThreads->size();
515
516 list<ThreadID>::iterator threads = activeThreads->begin();
517 list<ThreadID>::iterator end = activeThreads->end();
518
519 while (threads != end) {
520 ThreadID tid = *threads++;
521
522 if (iqPolicy == Partitioned) {
523 maxEntries[tid] = numEntries / active_threads;
524 } else if (iqPolicy == Threshold && active_threads == 1) {
525 maxEntries[tid] = numEntries;
526 }
527 }
528 }
529}
530
531template <class Impl>
532unsigned
533InstructionQueue<Impl>::numFreeEntries()
534{
535 return freeEntries;
536}
537
538template <class Impl>
539unsigned
540InstructionQueue<Impl>::numFreeEntries(ThreadID tid)
541{
542 return maxEntries[tid] - count[tid];
543}
544
545// Might want to do something more complex if it knows how many instructions
546// will be issued this cycle.
547template <class Impl>
548bool
549InstructionQueue<Impl>::isFull()
550{
551 if (freeEntries == 0) {
552 return(true);
553 } else {
554 return(false);
555 }
556}
557
558template <class Impl>
559bool
560InstructionQueue<Impl>::isFull(ThreadID tid)
561{
562 if (numFreeEntries(tid) == 0) {
563 return(true);
564 } else {
565 return(false);
566 }
567}
568
569template <class Impl>
570bool
571InstructionQueue<Impl>::hasReadyInsts()
572{
573 if (!listOrder.empty()) {
574 return true;
575 }
576
577 for (int i = 0; i < Num_OpClasses; ++i) {
578 if (!readyInsts[i].empty()) {
579 return true;
580 }
581 }
582
583 return false;
584}
585
586template <class Impl>
587void
588InstructionQueue<Impl>::insert(const DynInstPtr &new_inst)
589{
590 if (new_inst->isFloating()) {
591 fpInstQueueWrites++;
592 } else if (new_inst->isVector()) {
593 vecInstQueueWrites++;
594 } else {
595 intInstQueueWrites++;
596 }
597 // Make sure the instruction is valid
598 assert(new_inst);
599
600 DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n",
601 new_inst->seqNum, new_inst->pcState());
602
603 assert(freeEntries != 0);
604
605 instList[new_inst->threadNumber].push_back(new_inst);
606
607 --freeEntries;
608
609 new_inst->setInIQ();
610
611 // Look through its source registers (physical regs), and mark any
612 // dependencies.
613 addToDependents(new_inst);
614
615 // Have this instruction set itself as the producer of its destination
616 // register(s).
617 addToProducers(new_inst);
618
619 if (new_inst->isMemRef()) {
620 memDepUnit[new_inst->threadNumber].insert(new_inst);
621 } else {
622 addIfReady(new_inst);
623 }
624
625 ++iqInstsAdded;
626
627 count[new_inst->threadNumber]++;
628
629 assert(freeEntries == (numEntries - countInsts()));
630}
631
632template <class Impl>
633void
634InstructionQueue<Impl>::insertNonSpec(const DynInstPtr &new_inst)
635{
636 // @todo: Clean up this code; can do it by setting inst as unable
637 // to issue, then calling normal insert on the inst.
638 if (new_inst->isFloating()) {
639 fpInstQueueWrites++;
640 } else if (new_inst->isVector()) {
641 vecInstQueueWrites++;
642 } else {
643 intInstQueueWrites++;
644 }
645
646 assert(new_inst);
647
648 nonSpecInsts[new_inst->seqNum] = new_inst;
649
650 DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s "
651 "to the IQ.\n",
652 new_inst->seqNum, new_inst->pcState());
653
654 assert(freeEntries != 0);
655
656 instList[new_inst->threadNumber].push_back(new_inst);
657
658 --freeEntries;
659
660 new_inst->setInIQ();
661
662 // Have this instruction set itself as the producer of its destination
663 // register(s).
664 addToProducers(new_inst);
665
666 // If it's a memory instruction, add it to the memory dependency
667 // unit.
668 if (new_inst->isMemRef()) {
669 memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst);
670 }
671
672 ++iqNonSpecInstsAdded;
673
674 count[new_inst->threadNumber]++;
675
676 assert(freeEntries == (numEntries - countInsts()));
677}
678
679template <class Impl>
680void
681InstructionQueue<Impl>::insertBarrier(const DynInstPtr &barr_inst)
682{
683 memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst);
684
685 insertNonSpec(barr_inst);
686}
687
688template <class Impl>
689typename Impl::DynInstPtr
690InstructionQueue<Impl>::getInstToExecute()
691{
692 assert(!instsToExecute.empty());
693 DynInstPtr inst = std::move(instsToExecute.front());
694 instsToExecute.pop_front();
695 if (inst->isFloating()) {
696 fpInstQueueReads++;
697 } else if (inst->isVector()) {
698 vecInstQueueReads++;
699 } else {
700 intInstQueueReads++;
701 }
702 return inst;
703}
704
705template <class Impl>
706void
707InstructionQueue<Impl>::addToOrderList(OpClass op_class)
708{
709 assert(!readyInsts[op_class].empty());
710
711 ListOrderEntry queue_entry;
712
713 queue_entry.queueType = op_class;
714
715 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
716
717 ListOrderIt list_it = listOrder.begin();
718 ListOrderIt list_end_it = listOrder.end();
719
720 while (list_it != list_end_it) {
721 if ((*list_it).oldestInst > queue_entry.oldestInst) {
722 break;
723 }
724
725 list_it++;
726 }
727
728 readyIt[op_class] = listOrder.insert(list_it, queue_entry);
729 queueOnList[op_class] = true;
730}
731
732template <class Impl>
733void
734InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it)
735{
736 // Get iterator of next item on the list
737 // Delete the original iterator
738 // Determine if the next item is either the end of the list or younger
739 // than the new instruction. If so, then add in a new iterator right here.
740 // If not, then move along.
741 ListOrderEntry queue_entry;
742 OpClass op_class = (*list_order_it).queueType;
743 ListOrderIt next_it = list_order_it;
744
745 ++next_it;
746
747 queue_entry.queueType = op_class;
748 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
749
750 while (next_it != listOrder.end() &&
751 (*next_it).oldestInst < queue_entry.oldestInst) {
752 ++next_it;
753 }
754
755 readyIt[op_class] = listOrder.insert(next_it, queue_entry);
756}
757
758template <class Impl>
759void
760InstructionQueue<Impl>::processFUCompletion(const DynInstPtr &inst, int fu_idx)
761{
762 DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum);
763 assert(!cpu->switchedOut());
764 // The CPU could have been sleeping until this op completed (*extremely*
765 // long latency op). Wake it if it was. This may be overkill.
766 --wbOutstanding;
767 iewStage->wakeCPU();
768
769 if (fu_idx > -1)
770 fuPool->freeUnitNextCycle(fu_idx);
771
772 // @todo: Ensure that these FU Completions happen at the beginning
773 // of a cycle, otherwise they could add too many instructions to
774 // the queue.
775 issueToExecuteQueue->access(-1)->size++;
776 instsToExecute.push_back(inst);
777}
778
779// @todo: Figure out a better way to remove the squashed items from the
780// lists. Checking the top item of each list to see if it's squashed
781// wastes time and forces jumps.
782template <class Impl>
783void
784InstructionQueue<Impl>::scheduleReadyInsts()
785{
786 DPRINTF(IQ, "Attempting to schedule ready instructions from "
787 "the IQ.\n");
788
789 IssueStruct *i2e_info = issueToExecuteQueue->access(0);
790
791 DynInstPtr mem_inst;
792 while (mem_inst = std::move(getDeferredMemInstToExecute())) {
793 addReadyMemInst(mem_inst);
794 }
795
796 // See if any cache blocked instructions are able to be executed
797 while (mem_inst = std::move(getBlockedMemInstToExecute())) {
798 addReadyMemInst(mem_inst);
799 }
800
801 // Have iterator to head of the list
802 // While I haven't exceeded bandwidth or reached the end of the list,
803 // Try to get a FU that can do what this op needs.
804 // If successful, change the oldestInst to the new top of the list, put
805 // the queue in the proper place in the list.
806 // Increment the iterator.
807 // This will avoid trying to schedule a certain op class if there are no
808 // FUs that handle it.
809 int total_issued = 0;
810 ListOrderIt order_it = listOrder.begin();
811 ListOrderIt order_end_it = listOrder.end();
812
813 while (total_issued < totalWidth && order_it != order_end_it) {
814 OpClass op_class = (*order_it).queueType;
815
816 assert(!readyInsts[op_class].empty());
817
818 DynInstPtr issuing_inst = readyInsts[op_class].top();
819
820 if (issuing_inst->isFloating()) {
821 fpInstQueueReads++;
822 } else if (issuing_inst->isVector()) {
823 vecInstQueueReads++;
824 } else {
825 intInstQueueReads++;
826 }
827
828 assert(issuing_inst->seqNum == (*order_it).oldestInst);
829
830 if (issuing_inst->isSquashed()) {
831 readyInsts[op_class].pop();
832
833 if (!readyInsts[op_class].empty()) {
834 moveToYoungerInst(order_it);
835 } else {
836 readyIt[op_class] = listOrder.end();
837 queueOnList[op_class] = false;
838 }
839
840 listOrder.erase(order_it++);
841
842 ++iqSquashedInstsIssued;
843
844 continue;
845 }
846
847 int idx = FUPool::NoCapableFU;
848 Cycles op_latency = Cycles(1);
849 ThreadID tid = issuing_inst->threadNumber;
850
851 if (op_class != No_OpClass) {
852 idx = fuPool->getUnit(op_class);
853 if (issuing_inst->isFloating()) {
854 fpAluAccesses++;
855 } else if (issuing_inst->isVector()) {
856 vecAluAccesses++;
857 } else {
858 intAluAccesses++;
859 }
860 if (idx > FUPool::NoFreeFU) {
861 op_latency = fuPool->getOpLatency(op_class);
862 }
863 }
864
865 // If we have an instruction that doesn't require a FU, or a
866 // valid FU, then schedule for execution.
867 if (idx != FUPool::NoFreeFU) {
868 if (op_latency == Cycles(1)) {
869 i2e_info->size++;
870 instsToExecute.push_back(issuing_inst);
871
872 // Add the FU onto the list of FU's to be freed next
873 // cycle if we used one.
874 if (idx >= 0)
875 fuPool->freeUnitNextCycle(idx);
876 } else {
877 bool pipelined = fuPool->isPipelined(op_class);
878 // Generate completion event for the FU
879 ++wbOutstanding;
880 FUCompletion *execution = new FUCompletion(issuing_inst,
881 idx, this);
882
883 cpu->schedule(execution,
884 cpu->clockEdge(Cycles(op_latency - 1)));
885
886 if (!pipelined) {
887 // If FU isn't pipelined, then it must be freed
888 // upon the execution completing.
889 execution->setFreeFU();
890 } else {
891 // Add the FU onto the list of FU's to be freed next cycle.
892 fuPool->freeUnitNextCycle(idx);
893 }
894 }
895
896 DPRINTF(IQ, "Thread %i: Issuing instruction PC %s "
897 "[sn:%lli]\n",
898 tid, issuing_inst->pcState(),
899 issuing_inst->seqNum);
900
901 readyInsts[op_class].pop();
902
903 if (!readyInsts[op_class].empty()) {
904 moveToYoungerInst(order_it);
905 } else {
906 readyIt[op_class] = listOrder.end();
907 queueOnList[op_class] = false;
908 }
909
910 issuing_inst->setIssued();
911 ++total_issued;
912
913#if TRACING_ON
914 issuing_inst->issueTick = curTick() - issuing_inst->fetchTick;
915#endif
916
917 if (!issuing_inst->isMemRef()) {
918 // Memory instructions can not be freed from the IQ until they
919 // complete.
920 ++freeEntries;
921 count[tid]--;
922 issuing_inst->clearInIQ();
923 } else {
924 memDepUnit[tid].issue(issuing_inst);
925 }
926
927 listOrder.erase(order_it++);
928 statIssuedInstType[tid][op_class]++;
929 } else {
930 statFuBusy[op_class]++;
931 fuBusy[tid]++;
932 ++order_it;
933 }
934 }
935
936 numIssuedDist.sample(total_issued);
937 iqInstsIssued+= total_issued;
938
939 // If we issued any instructions, tell the CPU we had activity.
940 // @todo If the way deferred memory instructions are handeled due to
941 // translation changes then the deferredMemInsts condition should be removed
942 // from the code below.
943 if (total_issued || !retryMemInsts.empty() || !deferredMemInsts.empty()) {
944 cpu->activityThisCycle();
945 } else {
946 DPRINTF(IQ, "Not able to schedule any instructions.\n");
947 }
948}
949
950template <class Impl>
951void
952InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
953{
954 DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready "
955 "to execute.\n", inst);
956
957 NonSpecMapIt inst_it = nonSpecInsts.find(inst);
958
959 assert(inst_it != nonSpecInsts.end());
960
961 ThreadID tid = (*inst_it).second->threadNumber;
962
963 (*inst_it).second->setAtCommit();
964
965 (*inst_it).second->setCanIssue();
966
967 if (!(*inst_it).second->isMemRef()) {
968 addIfReady((*inst_it).second);
969 } else {
970 memDepUnit[tid].nonSpecInstReady((*inst_it).second);
971 }
972
973 (*inst_it).second = NULL;
974
975 nonSpecInsts.erase(inst_it);
976}
977
978template <class Impl>
979void
980InstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid)
981{
982 DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n",
983 tid,inst);
984
985 ListIt iq_it = instList[tid].begin();
986
987 while (iq_it != instList[tid].end() &&
988 (*iq_it)->seqNum <= inst) {
989 ++iq_it;
990 instList[tid].pop_front();
991 }
992
993 assert(freeEntries == (numEntries - countInsts()));
994}
995
996template <class Impl>
997int
998InstructionQueue<Impl>::wakeDependents(const DynInstPtr &completed_inst)
999{
1000 int dependents = 0;
1001
1002 // The instruction queue here takes care of both floating and int ops
1003 if (completed_inst->isFloating()) {
1004 fpInstQueueWakeupAccesses++;
1005 } else if (completed_inst->isVector()) {
1006 vecInstQueueWakeupAccesses++;
1007 } else {
1008 intInstQueueWakeupAccesses++;
1009 }
1010
1011 DPRINTF(IQ, "Waking dependents of completed instruction.\n");
1012
1013 assert(!completed_inst->isSquashed());
1014
1015 // Tell the memory dependence unit to wake any dependents on this
1016 // instruction if it is a memory instruction. Also complete the memory
1017 // instruction at this point since we know it executed without issues.
1018 // @todo: Might want to rename "completeMemInst" to something that
1019 // indicates that it won't need to be replayed, and call this
1020 // earlier. Might not be a big deal.
1021 if (completed_inst->isMemRef()) {
1022 memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst);
1023 completeMemInst(completed_inst);
1024 } else if (completed_inst->isMemBarrier() ||
1025 completed_inst->isWriteBarrier()) {
1026 memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst);
1027 }
1028
1029 for (int dest_reg_idx = 0;
1030 dest_reg_idx < completed_inst->numDestRegs();
1031 dest_reg_idx++)
1032 {
1033 PhysRegIdPtr dest_reg =
1034 completed_inst->renamedDestRegIdx(dest_reg_idx);
1035
1036 // Special case of uniq or control registers. They are not
1037 // handled by the IQ and thus have no dependency graph entry.
1038 if (dest_reg->isFixedMapping()) {
1039 DPRINTF(IQ, "Reg %d [%s] is part of a fix mapping, skipping\n",
1040 dest_reg->index(), dest_reg->className());
1041 continue;
1042 }
1043
1044 DPRINTF(IQ, "Waking any dependents on register %i (%s).\n",
1045 dest_reg->index(),
1046 dest_reg->className());
1047
1048 //Go through the dependency chain, marking the registers as
1049 //ready within the waiting instructions.
1050 DynInstPtr dep_inst = dependGraph.pop(dest_reg->flatIndex());
1051
1052 while (dep_inst) {
1053 DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] "
1054 "PC %s.\n", dep_inst->seqNum, dep_inst->pcState());
1055
1056 // Might want to give more information to the instruction
1057 // so that it knows which of its source registers is
1058 // ready. However that would mean that the dependency
1059 // graph entries would need to hold the src_reg_idx.
1060 dep_inst->markSrcRegReady();
1061
1062 addIfReady(dep_inst);
1063
1064 dep_inst = dependGraph.pop(dest_reg->flatIndex());
1065
1066 ++dependents;
1067 }
1068
1069 // Reset the head node now that all of its dependents have
1070 // been woken up.
1071 assert(dependGraph.empty(dest_reg->flatIndex()));
1072 dependGraph.clearInst(dest_reg->flatIndex());
1073
1074 // Mark the scoreboard as having that register ready.
1075 regScoreboard[dest_reg->flatIndex()] = true;
1076 }
1077 return dependents;
1078}
1079
1080template <class Impl>
1081void
1082InstructionQueue<Impl>::addReadyMemInst(const DynInstPtr &ready_inst)
1083{
1084 OpClass op_class = ready_inst->opClass();
1085
1086 readyInsts[op_class].push(ready_inst);
1087
1088 // Will need to reorder the list if either a queue is not on the list,
1089 // or it has an older instruction than last time.
1090 if (!queueOnList[op_class]) {
1091 addToOrderList(op_class);
1092 } else if (readyInsts[op_class].top()->seqNum <
1093 (*readyIt[op_class]).oldestInst) {
1094 listOrder.erase(readyIt[op_class]);
1095 addToOrderList(op_class);
1096 }
1097
1098 DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1099 "the ready list, PC %s opclass:%i [sn:%lli].\n",
1100 ready_inst->pcState(), op_class, ready_inst->seqNum);
1101}
1102
1103template <class Impl>
1104void
1105InstructionQueue<Impl>::rescheduleMemInst(const DynInstPtr &resched_inst)
1106{
1107 DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum);
1108
1109 // Reset DTB translation state
1110 resched_inst->translationStarted(false);
1111 resched_inst->translationCompleted(false);
1112
1113 resched_inst->clearCanIssue();
1114 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
1115}
1116
1117template <class Impl>
1118void
1119InstructionQueue<Impl>::replayMemInst(const DynInstPtr &replay_inst)
1120{
1121 memDepUnit[replay_inst->threadNumber].replay();
1122}
1123
1124template <class Impl>
1125void
1126InstructionQueue<Impl>::completeMemInst(const DynInstPtr &completed_inst)
1127{
1128 ThreadID tid = completed_inst->threadNumber;
1129
1130 DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n",
1131 completed_inst->pcState(), completed_inst->seqNum);
1132
1133 ++freeEntries;
1134
1135 completed_inst->memOpDone(true);
1136
1137 memDepUnit[tid].completed(completed_inst);
1138 count[tid]--;
1139}
1140
1141template <class Impl>
1142void
1143InstructionQueue<Impl>::deferMemInst(const DynInstPtr &deferred_inst)
1144{
1145 deferredMemInsts.push_back(deferred_inst);
1146}
1147
1148template <class Impl>
1149void
1150InstructionQueue<Impl>::blockMemInst(const DynInstPtr &blocked_inst)
1151{
1152 blocked_inst->translationStarted(false);
1153 blocked_inst->translationCompleted(false);
1154
1155 blocked_inst->clearIssued();
1156 blocked_inst->clearCanIssue();
1157 blockedMemInsts.push_back(blocked_inst);
1158}
1159
1160template <class Impl>
1161void
1162InstructionQueue<Impl>::cacheUnblocked()
1163{
1164 retryMemInsts.splice(retryMemInsts.end(), blockedMemInsts);
1165 // Get the CPU ticking again
1166 cpu->wakeCPU();
1167}
1168
1169template <class Impl>
1170typename Impl::DynInstPtr
1171InstructionQueue<Impl>::getDeferredMemInstToExecute()
1172{
1173 for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end();
1174 ++it) {
1175 if ((*it)->translationCompleted() || (*it)->isSquashed()) {
1176 DynInstPtr mem_inst = std::move(*it);
1177 deferredMemInsts.erase(it);
1178 return mem_inst;
1179 }
1180 }
1181 return nullptr;
1182}
1183
1184template <class Impl>
1185typename Impl::DynInstPtr
1186InstructionQueue<Impl>::getBlockedMemInstToExecute()
1187{
1188 if (retryMemInsts.empty()) {
1189 return nullptr;
1190 } else {
1191 DynInstPtr mem_inst = std::move(retryMemInsts.front());
1192 retryMemInsts.pop_front();
1193 return mem_inst;
1194 }
1195}
1196
1197template <class Impl>
1198void
1199InstructionQueue<Impl>::violation(const DynInstPtr &store,
1200 const DynInstPtr &faulting_load)
1201{
1202 intInstQueueWrites++;
1203 memDepUnit[store->threadNumber].violation(store, faulting_load);
1204}
1205
1206template <class Impl>
1207void
1208InstructionQueue<Impl>::squash(ThreadID tid)
1209{
1210 DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in "
1211 "the IQ.\n", tid);
1212
1213 // Read instruction sequence number of last instruction out of the
1214 // time buffer.
1215 squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
1216
1217 doSquash(tid);
1218
1219 // Also tell the memory dependence unit to squash.
1220 memDepUnit[tid].squash(squashedSeqNum[tid], tid);
1221}
1222
1223template <class Impl>
1224void
1225InstructionQueue<Impl>::doSquash(ThreadID tid)
1226{
1227 // Start at the tail.
1228 ListIt squash_it = instList[tid].end();
1229 --squash_it;
1230
1231 DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n",
1232 tid, squashedSeqNum[tid]);
1233
1234 // Squash any instructions younger than the squashed sequence number
1235 // given.
1236 while (squash_it != instList[tid].end() &&
1237 (*squash_it)->seqNum > squashedSeqNum[tid]) {
1238
1239 DynInstPtr squashed_inst = (*squash_it);
1240 if (squashed_inst->isFloating()) {
1241 fpInstQueueWrites++;
1242 } else if (squashed_inst->isVector()) {
1243 vecInstQueueWrites++;
1244 } else {
1245 intInstQueueWrites++;
1246 }
1247
1248 // Only handle the instruction if it actually is in the IQ and
1249 // hasn't already been squashed in the IQ.
1250 if (squashed_inst->threadNumber != tid ||
1251 squashed_inst->isSquashedInIQ()) {
1252 --squash_it;
1253 continue;
1254 }
1255
1256 if (!squashed_inst->isIssued() ||
1257 (squashed_inst->isMemRef() &&
1258 !squashed_inst->memOpDone())) {
1259
1260 DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n",
1261 tid, squashed_inst->seqNum, squashed_inst->pcState());
1262
1263 bool is_acq_rel = squashed_inst->isMemBarrier() &&
1264 (squashed_inst->isLoad() ||
1265 (squashed_inst->isStore() &&
1266 !squashed_inst->isStoreConditional()));
1267
1268 // Remove the instruction from the dependency list.
1269 if (is_acq_rel ||
1270 (!squashed_inst->isNonSpeculative() &&
1271 !squashed_inst->isStoreConditional() &&
1272 !squashed_inst->isMemBarrier() &&
1273 !squashed_inst->isWriteBarrier())) {
1274
1275 for (int src_reg_idx = 0;
1276 src_reg_idx < squashed_inst->numSrcRegs();
1277 src_reg_idx++)
1278 {
1279 PhysRegIdPtr src_reg =
1280 squashed_inst->renamedSrcRegIdx(src_reg_idx);
1281
1282 // Only remove it from the dependency graph if it
1283 // was placed there in the first place.
1284
1285 // Instead of doing a linked list traversal, we
1286 // can just remove these squashed instructions
1287 // either at issue time, or when the register is
1288 // overwritten. The only downside to this is it
1289 // leaves more room for error.
1290
1291 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) &&
1292 !src_reg->isFixedMapping()) {
1293 dependGraph.remove(src_reg->flatIndex(),
1294 squashed_inst);
1295 }
1296
1297
1298 ++iqSquashedOperandsExamined;
1299 }
1300 } else if (!squashed_inst->isStoreConditional() ||
1301 !squashed_inst->isCompleted()) {
1302 NonSpecMapIt ns_inst_it =
1303 nonSpecInsts.find(squashed_inst->seqNum);
1304
1305 // we remove non-speculative instructions from
1306 // nonSpecInsts already when they are ready, and so we
1307 // cannot always expect to find them
1308 if (ns_inst_it == nonSpecInsts.end()) {
1309 // loads that became ready but stalled on a
1310 // blocked cache are alreayd removed from
1311 // nonSpecInsts, and have not faulted
1312 assert(squashed_inst->getFault() != NoFault ||
1313 squashed_inst->isMemRef());
1314 } else {
1315
1316 (*ns_inst_it).second = NULL;
1317
1318 nonSpecInsts.erase(ns_inst_it);
1319
1320 ++iqSquashedNonSpecRemoved;
1321 }
1322 }
1323
1324 // Might want to also clear out the head of the dependency graph.
1325
1326 // Mark it as squashed within the IQ.
1327 squashed_inst->setSquashedInIQ();
1328
1329 // @todo: Remove this hack where several statuses are set so the
1330 // inst will flow through the rest of the pipeline.
1331 squashed_inst->setIssued();
1332 squashed_inst->setCanCommit();
1333 squashed_inst->clearInIQ();
1334
1335 //Update Thread IQ Count
1336 count[squashed_inst->threadNumber]--;
1337
1338 ++freeEntries;
1339 }
1340
1341 // IQ clears out the heads of the dependency graph only when
1342 // instructions reach writeback stage. If an instruction is squashed
1343 // before writeback stage, its head of dependency graph would not be
1344 // cleared out; it holds the instruction's DynInstPtr. This prevents
1345 // freeing the squashed instruction's DynInst.
1346 // Thus, we need to manually clear out the squashed instructions' heads
1347 // of dependency graph.
1348 for (int dest_reg_idx = 0;
1349 dest_reg_idx < squashed_inst->numDestRegs();
1350 dest_reg_idx++)
1351 {
1352 PhysRegIdPtr dest_reg =
1353 squashed_inst->renamedDestRegIdx(dest_reg_idx);
1354 if (dest_reg->isFixedMapping()){
1355 continue;
1356 }
1357 assert(dependGraph.empty(dest_reg->flatIndex()));
1358 dependGraph.clearInst(dest_reg->flatIndex());
1359 }
1360 instList[tid].erase(squash_it--);
1361 ++iqSquashedInstsExamined;
1362 }
1363}
1364
1365template <class Impl>
1366bool
1367InstructionQueue<Impl>::addToDependents(const DynInstPtr &new_inst)
1368{
1369 // Loop through the instruction's source registers, adding
1370 // them to the dependency list if they are not ready.
1371 int8_t total_src_regs = new_inst->numSrcRegs();
1372 bool return_val = false;
1373
1374 for (int src_reg_idx = 0;
1375 src_reg_idx < total_src_regs;
1376 src_reg_idx++)
1377 {
1378 // Only add it to the dependency graph if it's not ready.
1379 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) {
1380 PhysRegIdPtr src_reg = new_inst->renamedSrcRegIdx(src_reg_idx);
1381
1382 // Check the IQ's scoreboard to make sure the register
1383 // hasn't become ready while the instruction was in flight
1384 // between stages. Only if it really isn't ready should
1385 // it be added to the dependency graph.
1386 if (src_reg->isFixedMapping()) {
1387 continue;
1388 } else if (!regScoreboard[src_reg->flatIndex()]) {
1389 DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that "
1390 "is being added to the dependency chain.\n",
1391 new_inst->pcState(), src_reg->index(),
1392 src_reg->className());
1393
1394 dependGraph.insert(src_reg->flatIndex(), new_inst);
1395
1396 // Change the return value to indicate that something
1397 // was added to the dependency graph.
1398 return_val = true;
1399 } else {
1400 DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that "
1401 "became ready before it reached the IQ.\n",
1402 new_inst->pcState(), src_reg->index(),
1403 src_reg->className());
1404 // Mark a register ready within the instruction.
1405 new_inst->markSrcRegReady(src_reg_idx);
1406 }
1407 }
1408 }
1409
1410 return return_val;
1411}
1412
1413template <class Impl>
1414void
1415InstructionQueue<Impl>::addToProducers(const DynInstPtr &new_inst)
1416{
1417 // Nothing really needs to be marked when an instruction becomes
1418 // the producer of a register's value, but for convenience a ptr
1419 // to the producing instruction will be placed in the head node of
1420 // the dependency links.
1421 int8_t total_dest_regs = new_inst->numDestRegs();
1422
1423 for (int dest_reg_idx = 0;
1424 dest_reg_idx < total_dest_regs;
1425 dest_reg_idx++)
1426 {
1427 PhysRegIdPtr dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx);
1428
1429 // Some registers have fixed mapping, and there is no need to track
1430 // dependencies as these instructions must be executed at commit.
1431 if (dest_reg->isFixedMapping()) {
1432 continue;
1433 }
1434
1435 if (!dependGraph.empty(dest_reg->flatIndex())) {
1436 dependGraph.dump();
1437 panic("Dependency graph %i (%s) (flat: %i) not empty!",
1438 dest_reg->index(), dest_reg->className(),
1439 dest_reg->flatIndex());
1440 }
1441
1442 dependGraph.setInst(dest_reg->flatIndex(), new_inst);
1443
1444 // Mark the scoreboard to say it's not yet ready.
1445 regScoreboard[dest_reg->flatIndex()] = false;
1446 }
1447}
1448
1449template <class Impl>
1450void
1451InstructionQueue<Impl>::addIfReady(const DynInstPtr &inst)
1452{
1453 // If the instruction now has all of its source registers
1454 // available, then add it to the list of ready instructions.
1455 if (inst->readyToIssue()) {
1456
1457 //Add the instruction to the proper ready list.
1458 if (inst->isMemRef()) {
1459
1460 DPRINTF(IQ, "Checking if memory instruction can issue.\n");
1461
1462 // Message to the mem dependence unit that this instruction has
1463 // its registers ready.
1464 memDepUnit[inst->threadNumber].regsReady(inst);
1465
1466 return;
1467 }
1468
1469 OpClass op_class = inst->opClass();
1470
1471 DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1472 "the ready list, PC %s opclass:%i [sn:%lli].\n",
1473 inst->pcState(), op_class, inst->seqNum);
1474
1475 readyInsts[op_class].push(inst);
1476
1477 // Will need to reorder the list if either a queue is not on the list,
1478 // or it has an older instruction than last time.
1479 if (!queueOnList[op_class]) {
1480 addToOrderList(op_class);
1481 } else if (readyInsts[op_class].top()->seqNum <
1482 (*readyIt[op_class]).oldestInst) {
1483 listOrder.erase(readyIt[op_class]);
1484 addToOrderList(op_class);
1485 }
1486 }
1487}
1488
1489template <class Impl>
1490int
1491InstructionQueue<Impl>::countInsts()
1492{
1493#if 0
1494 //ksewell:This works but definitely could use a cleaner write
1495 //with a more intuitive way of counting. Right now it's
1496 //just brute force ....
1497 // Change the #if if you want to use this method.
1498 int total_insts = 0;
1499
1500 for (ThreadID tid = 0; tid < numThreads; ++tid) {
1501 ListIt count_it = instList[tid].begin();
1502
1503 while (count_it != instList[tid].end()) {
1504 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) {
1505 if (!(*count_it)->isIssued()) {
1506 ++total_insts;
1507 } else if ((*count_it)->isMemRef() &&
1508 !(*count_it)->memOpDone) {
1509 // Loads that have not been marked as executed still count
1510 // towards the total instructions.
1511 ++total_insts;
1512 }
1513 }
1514
1515 ++count_it;
1516 }
1517 }
1518
1519 return total_insts;
1520#else
1521 return numEntries - freeEntries;
1522#endif
1523}
1524
1525template <class Impl>
1526void
1527InstructionQueue<Impl>::dumpLists()
1528{
1529 for (int i = 0; i < Num_OpClasses; ++i) {
1530 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size());
1531
1532 cprintf("\n");
1533 }
1534
1535 cprintf("Non speculative list size: %i\n", nonSpecInsts.size());
1536
1537 NonSpecMapIt non_spec_it = nonSpecInsts.begin();
1538 NonSpecMapIt non_spec_end_it = nonSpecInsts.end();
1539
1540 cprintf("Non speculative list: ");
1541
1542 while (non_spec_it != non_spec_end_it) {
1543 cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(),
1544 (*non_spec_it).second->seqNum);
1545 ++non_spec_it;
1546 }
1547
1548 cprintf("\n");
1549
1550 ListOrderIt list_order_it = listOrder.begin();
1551 ListOrderIt list_order_end_it = listOrder.end();
1552 int i = 1;
1553
1554 cprintf("List order: ");
1555
1556 while (list_order_it != list_order_end_it) {
1557 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType,
1558 (*list_order_it).oldestInst);
1559
1560 ++list_order_it;
1561 ++i;
1562 }
1563
1564 cprintf("\n");
1565}
1566
1567
1568template <class Impl>
1569void
1570InstructionQueue<Impl>::dumpInsts()
1571{
1572 for (ThreadID tid = 0; tid < numThreads; ++tid) {
1573 int num = 0;
1574 int valid_num = 0;
1575 ListIt inst_list_it = instList[tid].begin();
1576
1577 while (inst_list_it != instList[tid].end()) {
1578 cprintf("Instruction:%i\n", num);
1579 if (!(*inst_list_it)->isSquashed()) {
1580 if (!(*inst_list_it)->isIssued()) {
1581 ++valid_num;
1582 cprintf("Count:%i\n", valid_num);
1583 } else if ((*inst_list_it)->isMemRef() &&
1584 !(*inst_list_it)->memOpDone()) {
1585 // Loads that have not been marked as executed
1586 // still count towards the total instructions.
1587 ++valid_num;
1588 cprintf("Count:%i\n", valid_num);
1589 }
1590 }
1591
1592 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n"
1593 "Issued:%i\nSquashed:%i\n",
1594 (*inst_list_it)->pcState(),
1595 (*inst_list_it)->seqNum,
1596 (*inst_list_it)->threadNumber,
1597 (*inst_list_it)->isIssued(),
1598 (*inst_list_it)->isSquashed());
1599
1600 if ((*inst_list_it)->isMemRef()) {
1601 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone());
1602 }
1603
1604 cprintf("\n");
1605
1606 inst_list_it++;
1607 ++num;
1608 }
1609 }
1610
1611 cprintf("Insts to Execute list:\n");
1612
1613 int num = 0;
1614 int valid_num = 0;
1615 ListIt inst_list_it = instsToExecute.begin();
1616
1617 while (inst_list_it != instsToExecute.end())
1618 {
1619 cprintf("Instruction:%i\n",
1620 num);
1621 if (!(*inst_list_it)->isSquashed()) {
1622 if (!(*inst_list_it)->isIssued()) {
1623 ++valid_num;
1624 cprintf("Count:%i\n", valid_num);
1625 } else if ((*inst_list_it)->isMemRef() &&
1626 !(*inst_list_it)->memOpDone()) {
1627 // Loads that have not been marked as executed
1628 // still count towards the total instructions.
1629 ++valid_num;
1630 cprintf("Count:%i\n", valid_num);
1631 }
1632 }
1633
1634 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n"
1635 "Issued:%i\nSquashed:%i\n",
1636 (*inst_list_it)->pcState(),
1637 (*inst_list_it)->seqNum,
1638 (*inst_list_it)->threadNumber,
1639 (*inst_list_it)->isIssued(),
1640 (*inst_list_it)->isSquashed());
1641
1642 if ((*inst_list_it)->isMemRef()) {
1643 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone());
1644 }
1645
1646 cprintf("\n");
1647
1648 inst_list_it++;
1649 ++num;
1650 }
1651}
1652
1653#endif//__CPU_O3_INST_QUEUE_IMPL_HH__