1/*
2 * Copyright (c) 2011-2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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408 while (!readyInsts[i].empty())
409 readyInsts[i].pop();
410 queueOnList[i] = false;
411 readyIt[i] = listOrder.end();
412 }
413 nonSpecInsts.clear();
414 listOrder.clear();
415 deferredMemInsts.clear();
416}
417
418template <class Impl>
419void
420InstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
421{
422 activeThreads = at_ptr;
423}

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729void
730InstructionQueue<Impl>::scheduleReadyInsts()
731{
732 DPRINTF(IQ, "Attempting to schedule ready instructions from "
733 "the IQ.\n");
734
735 IssueStruct *i2e_info = issueToExecuteQueue->access(0);
736
737 DynInstPtr deferred_mem_inst;
738 int total_deferred_mem_issued = 0;
739 while (total_deferred_mem_issued < totalWidth &&
740 (deferred_mem_inst = getDeferredMemInstToExecute()) != 0) {
741 issueToExecuteQueue->access(0)->size++;
742 instsToExecute.push_back(deferred_mem_inst);
743 total_deferred_mem_issued++;
744 }
745
746 // Have iterator to head of the list
747 // While I haven't exceeded bandwidth or reached the end of the list,
748 // Try to get a FU that can do what this op needs.
749 // If successful, change the oldestInst to the new top of the list, put
750 // the queue in the proper place in the list.
751 // Increment the iterator.
752 // This will avoid trying to schedule a certain op class if there are no
753 // FUs that handle it.
754 ListOrderIt order_it = listOrder.begin();
755 ListOrderIt order_end_it = listOrder.end();
756 int total_issued = 0;
757
758 while (total_issued < (totalWidth - total_deferred_mem_issued) &&
759 order_it != order_end_it) {
760 OpClass op_class = (*order_it).queueType;
761
762 assert(!readyInsts[op_class].empty());
763
764 DynInstPtr issuing_inst = readyInsts[op_class].top();
765
766 issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++;
767

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869
870 numIssuedDist.sample(total_issued);
871 iqInstsIssued+= total_issued;
872
873 // If we issued any instructions, tell the CPU we had activity.
874 // @todo If the way deferred memory instructions are handeled due to
875 // translation changes then the deferredMemInsts condition should be removed
876 // from the code below.
877 if (total_issued || total_deferred_mem_issued || deferredMemInsts.size()) {
878 cpu->activityThisCycle();
879 } else {
880 DPRINTF(IQ, "Not able to schedule any instructions.\n");
881 }
882}
883
884template <class Impl>
885void

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1045 resched_inst->clearCanIssue();
1046 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
1047}
1048
1049template <class Impl>
1050void
1051InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst)
1052{
1053 memDepUnit[replay_inst->threadNumber].replay(replay_inst);
1054}
1055
1056template <class Impl>
1057void
1058InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst)
1059{
1060 ThreadID tid = completed_inst->threadNumber;
1061

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1073template <class Impl>
1074void
1075InstructionQueue<Impl>::deferMemInst(DynInstPtr &deferred_inst)
1076{
1077 deferredMemInsts.push_back(deferred_inst);
1078}
1079
1080template <class Impl>
1081typename Impl::DynInstPtr
1082InstructionQueue<Impl>::getDeferredMemInstToExecute()
1083{
1084 for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end();
1085 ++it) {
1086 if ((*it)->translationCompleted() || (*it)->isSquashed()) {
1087 DynInstPtr ret = *it;
1088 deferredMemInsts.erase(it);
1089 return ret;
1090 }
1091 }
1092 return NULL;
1093}
1094
1095template <class Impl>
1096void
1097InstructionQueue<Impl>::violation(DynInstPtr &store,
1098 DynInstPtr &faulting_load)
1099{
1100 intInstQueueWrites++;
1101 memDepUnit[store->threadNumber].violation(store, faulting_load);
1102}
1103

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