1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#include <limits>
45#include <vector>
46
47#include "cpu/o3/fu_pool.hh"
48#include "cpu/o3/inst_queue.hh"
49#include "debug/IQ.hh"
50#include "enums/OpClass.hh"
51#include "params/DerivO3CPU.hh"
52#include "sim/core.hh"
53
54using namespace std;
55
56template <class Impl>
57InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
58 int fu_idx, InstructionQueue<Impl> *iq_ptr)
59 : Event(Stat_Event_Pri, AutoDelete),
60 inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false)
61{
62}
63
64template <class Impl>
65void
66InstructionQueue<Impl>::FUCompletion::process()
67{
68 iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1);
69 inst = NULL;
70}
71
72
73template <class Impl>
74const char *
75InstructionQueue<Impl>::FUCompletion::description() const
76{
77 return "Functional unit completion";
78}
79
80template <class Impl>
81InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr,
82 DerivO3CPUParams *params)
83 : cpu(cpu_ptr),
84 iewStage(iew_ptr),
85 fuPool(params->fuPool),
86 numEntries(params->numIQEntries),
87 totalWidth(params->issueWidth),
88 numPhysIntRegs(params->numPhysIntRegs),
89 numPhysFloatRegs(params->numPhysFloatRegs),
90 commitToIEWDelay(params->commitToIEWDelay)
91{
92 assert(fuPool);
93
94 switchedOut = false;
95
96 numThreads = params->numThreads;
97
98 // Set the number of physical registers as the number of int + float
99 numPhysRegs = numPhysIntRegs + numPhysFloatRegs;
100
101 //Create an entry for each physical register within the
102 //dependency graph.
103 dependGraph.resize(numPhysRegs);
104
105 // Resize the register scoreboard.
106 regScoreboard.resize(numPhysRegs);
107
108 //Initialize Mem Dependence Units
109 for (ThreadID tid = 0; tid < numThreads; tid++) {
110 memDepUnit[tid].init(params, tid);
111 memDepUnit[tid].setIQ(this);
112 }
113
114 resetState();
115
116 std::string policy = params->smtIQPolicy;
117
118 //Convert string to lowercase
119 std::transform(policy.begin(), policy.end(), policy.begin(),
120 (int(*)(int)) tolower);
121
122 //Figure out resource sharing policy
123 if (policy == "dynamic") {
124 iqPolicy = Dynamic;
125
126 //Set Max Entries to Total ROB Capacity
127 for (ThreadID tid = 0; tid < numThreads; tid++) {
128 maxEntries[tid] = numEntries;
129 }
130
131 } else if (policy == "partitioned") {
132 iqPolicy = Partitioned;
133
134 //@todo:make work if part_amt doesnt divide evenly.
135 int part_amt = numEntries / numThreads;
136
137 //Divide ROB up evenly
138 for (ThreadID tid = 0; tid < numThreads; tid++) {
139 maxEntries[tid] = part_amt;
140 }
141
142 DPRINTF(IQ, "IQ sharing policy set to Partitioned:"
143 "%i entries per thread.\n",part_amt);
144 } else if (policy == "threshold") {
145 iqPolicy = Threshold;
146
147 double threshold = (double)params->smtIQThreshold / 100;
148
149 int thresholdIQ = (int)((double)threshold * numEntries);
150
151 //Divide up by threshold amount
152 for (ThreadID tid = 0; tid < numThreads; tid++) {
153 maxEntries[tid] = thresholdIQ;
154 }
155
156 DPRINTF(IQ, "IQ sharing policy set to Threshold:"
157 "%i entries per thread.\n",thresholdIQ);
158 } else {
159 assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
160 "Partitioned, Threshold}");
161 }
162}
163
164template <class Impl>
165InstructionQueue<Impl>::~InstructionQueue()
166{
167 dependGraph.reset();
168#ifdef DEBUG
169 cprintf("Nodes traversed: %i, removed: %i\n",
170 dependGraph.nodesTraversed, dependGraph.nodesRemoved);
171#endif
172}
173
174template <class Impl>
175std::string
176InstructionQueue<Impl>::name() const
177{
178 return cpu->name() + ".iq";
179}
180
181template <class Impl>
182void
183InstructionQueue<Impl>::regStats()
184{
185 using namespace Stats;
186 iqInstsAdded
187 .name(name() + ".iqInstsAdded")
188 .desc("Number of instructions added to the IQ (excludes non-spec)")
189 .prereq(iqInstsAdded);
190
191 iqNonSpecInstsAdded
192 .name(name() + ".iqNonSpecInstsAdded")
193 .desc("Number of non-speculative instructions added to the IQ")
194 .prereq(iqNonSpecInstsAdded);
195
196 iqInstsIssued
197 .name(name() + ".iqInstsIssued")
198 .desc("Number of instructions issued")
199 .prereq(iqInstsIssued);
200
201 iqIntInstsIssued
202 .name(name() + ".iqIntInstsIssued")
203 .desc("Number of integer instructions issued")
204 .prereq(iqIntInstsIssued);
205
206 iqFloatInstsIssued
207 .name(name() + ".iqFloatInstsIssued")
208 .desc("Number of float instructions issued")
209 .prereq(iqFloatInstsIssued);
210
211 iqBranchInstsIssued
212 .name(name() + ".iqBranchInstsIssued")
213 .desc("Number of branch instructions issued")
214 .prereq(iqBranchInstsIssued);
215
216 iqMemInstsIssued
217 .name(name() + ".iqMemInstsIssued")
218 .desc("Number of memory instructions issued")
219 .prereq(iqMemInstsIssued);
220
221 iqMiscInstsIssued
222 .name(name() + ".iqMiscInstsIssued")
223 .desc("Number of miscellaneous instructions issued")
224 .prereq(iqMiscInstsIssued);
225
226 iqSquashedInstsIssued
227 .name(name() + ".iqSquashedInstsIssued")
228 .desc("Number of squashed instructions issued")
229 .prereq(iqSquashedInstsIssued);
230
231 iqSquashedInstsExamined
232 .name(name() + ".iqSquashedInstsExamined")
233 .desc("Number of squashed instructions iterated over during squash;"
234 " mainly for profiling")
235 .prereq(iqSquashedInstsExamined);
236
237 iqSquashedOperandsExamined
238 .name(name() + ".iqSquashedOperandsExamined")
239 .desc("Number of squashed operands that are examined and possibly "
240 "removed from graph")
241 .prereq(iqSquashedOperandsExamined);
242
243 iqSquashedNonSpecRemoved
244 .name(name() + ".iqSquashedNonSpecRemoved")
245 .desc("Number of squashed non-spec instructions that were removed")
246 .prereq(iqSquashedNonSpecRemoved);
247/*
248 queueResDist
249 .init(Num_OpClasses, 0, 99, 2)
250 .name(name() + ".IQ:residence:")
251 .desc("cycles from dispatch to issue")
252 .flags(total | pdf | cdf )
253 ;
254 for (int i = 0; i < Num_OpClasses; ++i) {
255 queueResDist.subname(i, opClassStrings[i]);
256 }
257*/
258 numIssuedDist
259 .init(0,totalWidth,1)
260 .name(name() + ".issued_per_cycle")
261 .desc("Number of insts issued each cycle")
262 .flags(pdf)
263 ;
264/*
265 dist_unissued
266 .init(Num_OpClasses+2)
267 .name(name() + ".unissued_cause")
268 .desc("Reason ready instruction not issued")
269 .flags(pdf | dist)
270 ;
271 for (int i=0; i < (Num_OpClasses + 2); ++i) {
272 dist_unissued.subname(i, unissued_names[i]);
273 }
274*/
275 statIssuedInstType
276 .init(numThreads,Enums::Num_OpClass)
277 .name(name() + ".FU_type")
278 .desc("Type of FU issued")
279 .flags(total | pdf | dist)
280 ;
281 statIssuedInstType.ysubnames(Enums::OpClassStrings);
282
283 //
284 // How long did instructions for a particular FU type wait prior to issue
285 //
286/*
287 issueDelayDist
288 .init(Num_OpClasses,0,99,2)
289 .name(name() + ".")
290 .desc("cycles from operands ready to issue")
291 .flags(pdf | cdf)
292 ;
293
294 for (int i=0; i<Num_OpClasses; ++i) {
295 std::stringstream subname;
296 subname << opClassStrings[i] << "_delay";
297 issueDelayDist.subname(i, subname.str());
298 }
299*/
300 issueRate
301 .name(name() + ".rate")
302 .desc("Inst issue rate")
303 .flags(total)
304 ;
305 issueRate = iqInstsIssued / cpu->numCycles;
306
307 statFuBusy
308 .init(Num_OpClasses)
309 .name(name() + ".fu_full")
310 .desc("attempts to use FU when none available")
311 .flags(pdf | dist)
312 ;
313 for (int i=0; i < Num_OpClasses; ++i) {
314 statFuBusy.subname(i, Enums::OpClassStrings[i]);
315 }
316
317 fuBusy
318 .init(numThreads)
319 .name(name() + ".fu_busy_cnt")
320 .desc("FU busy when requested")
321 .flags(total)
322 ;
323
324 fuBusyRate
325 .name(name() + ".fu_busy_rate")
326 .desc("FU busy rate (busy events/executed inst)")
327 .flags(total)
328 ;
329 fuBusyRate = fuBusy / iqInstsIssued;
330
331 for (ThreadID tid = 0; tid < numThreads; tid++) {
332 // Tell mem dependence unit to reg stats as well.
333 memDepUnit[tid].regStats();
334 }
335
336 intInstQueueReads
337 .name(name() + ".int_inst_queue_reads")
338 .desc("Number of integer instruction queue reads")
339 .flags(total);
340
341 intInstQueueWrites
342 .name(name() + ".int_inst_queue_writes")
343 .desc("Number of integer instruction queue writes")
344 .flags(total);
345
346 intInstQueueWakeupAccesses
347 .name(name() + ".int_inst_queue_wakeup_accesses")
348 .desc("Number of integer instruction queue wakeup accesses")
349 .flags(total);
350
351 fpInstQueueReads
352 .name(name() + ".fp_inst_queue_reads")
353 .desc("Number of floating instruction queue reads")
354 .flags(total);
355
356 fpInstQueueWrites
357 .name(name() + ".fp_inst_queue_writes")
358 .desc("Number of floating instruction queue writes")
359 .flags(total);
360
361 fpInstQueueWakeupQccesses
362 .name(name() + ".fp_inst_queue_wakeup_accesses")
363 .desc("Number of floating instruction queue wakeup accesses")
364 .flags(total);
365
366 intAluAccesses
367 .name(name() + ".int_alu_accesses")
368 .desc("Number of integer alu accesses")
369 .flags(total);
370
371 fpAluAccesses
372 .name(name() + ".fp_alu_accesses")
373 .desc("Number of floating point alu accesses")
374 .flags(total);
375
376}
377
378template <class Impl>
379void
380InstructionQueue<Impl>::resetState()
381{
382 //Initialize thread IQ counts
383 for (ThreadID tid = 0; tid <numThreads; tid++) {
384 count[tid] = 0;
385 instList[tid].clear();
386 }
387
388 // Initialize the number of free IQ entries.
389 freeEntries = numEntries;
390
391 // Note that in actuality, the registers corresponding to the logical
392 // registers start off as ready. However this doesn't matter for the
393 // IQ as the instruction should have been correctly told if those
394 // registers are ready in rename. Thus it can all be initialized as
395 // unready.
396 for (int i = 0; i < numPhysRegs; ++i) {
397 regScoreboard[i] = false;
398 }
399
400 for (ThreadID tid = 0; tid < numThreads; ++tid) {
401 squashedSeqNum[tid] = 0;
402 }
403
404 for (int i = 0; i < Num_OpClasses; ++i) {
405 while (!readyInsts[i].empty())
406 readyInsts[i].pop();
407 queueOnList[i] = false;
408 readyIt[i] = listOrder.end();
409 }
410 nonSpecInsts.clear();
411 listOrder.clear();
412 deferredMemInsts.clear();
413}
414
415template <class Impl>
416void
417InstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
418{
419 activeThreads = at_ptr;
420}
421
422template <class Impl>
423void
424InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr)
425{
426 issueToExecuteQueue = i2e_ptr;
427}
428
429template <class Impl>
430void
431InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
432{
433 timeBuffer = tb_ptr;
434
435 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
436}
437
438template <class Impl>
439void
440InstructionQueue<Impl>::switchOut()
441{
442/*
443 if (!instList[0].empty() || (numEntries != freeEntries) ||
444 !readyInsts[0].empty() || !nonSpecInsts.empty() || !listOrder.empty()) {
445 dumpInsts();
446// assert(0);
447 }
448*/
449 resetState();
450 dependGraph.reset();
451 instsToExecute.clear();
452 switchedOut = true;
453 for (ThreadID tid = 0; tid < numThreads; ++tid) {
454 memDepUnit[tid].switchOut();
455 }
456}
457
458template <class Impl>
459void
460InstructionQueue<Impl>::takeOverFrom()
461{
462 switchedOut = false;
463}
464
465template <class Impl>
466int
467InstructionQueue<Impl>::entryAmount(ThreadID num_threads)
468{
469 if (iqPolicy == Partitioned) {
470 return numEntries / num_threads;
471 } else {
472 return 0;
473 }
474}
475
476
477template <class Impl>
478void
479InstructionQueue<Impl>::resetEntries()
480{
481 if (iqPolicy != Dynamic || numThreads > 1) {
482 int active_threads = activeThreads->size();
483
484 list<ThreadID>::iterator threads = activeThreads->begin();
485 list<ThreadID>::iterator end = activeThreads->end();
486
487 while (threads != end) {
488 ThreadID tid = *threads++;
489
490 if (iqPolicy == Partitioned) {
491 maxEntries[tid] = numEntries / active_threads;
492 } else if(iqPolicy == Threshold && active_threads == 1) {
493 maxEntries[tid] = numEntries;
494 }
495 }
496 }
497}
498
499template <class Impl>
500unsigned
501InstructionQueue<Impl>::numFreeEntries()
502{
503 return freeEntries;
504}
505
506template <class Impl>
507unsigned
508InstructionQueue<Impl>::numFreeEntries(ThreadID tid)
509{
510 return maxEntries[tid] - count[tid];
511}
512
513// Might want to do something more complex if it knows how many instructions
514// will be issued this cycle.
515template <class Impl>
516bool
517InstructionQueue<Impl>::isFull()
518{
519 if (freeEntries == 0) {
520 return(true);
521 } else {
522 return(false);
523 }
524}
525
526template <class Impl>
527bool
528InstructionQueue<Impl>::isFull(ThreadID tid)
529{
530 if (numFreeEntries(tid) == 0) {
531 return(true);
532 } else {
533 return(false);
534 }
535}
536
537template <class Impl>
538bool
539InstructionQueue<Impl>::hasReadyInsts()
540{
541 if (!listOrder.empty()) {
542 return true;
543 }
544
545 for (int i = 0; i < Num_OpClasses; ++i) {
546 if (!readyInsts[i].empty()) {
547 return true;
548 }
549 }
550
551 return false;
552}
553
554template <class Impl>
555void
556InstructionQueue<Impl>::insert(DynInstPtr &new_inst)
557{
558 new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
559 // Make sure the instruction is valid
560 assert(new_inst);
561
562 DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n",
563 new_inst->seqNum, new_inst->pcState());
564
565 assert(freeEntries != 0);
566
567 instList[new_inst->threadNumber].push_back(new_inst);
568
569 --freeEntries;
570
571 new_inst->setInIQ();
572
573 // Look through its source registers (physical regs), and mark any
574 // dependencies.
575 addToDependents(new_inst);
576
577 // Have this instruction set itself as the producer of its destination
578 // register(s).
579 addToProducers(new_inst);
580
581 if (new_inst->isMemRef()) {
582 memDepUnit[new_inst->threadNumber].insert(new_inst);
583 } else {
584 addIfReady(new_inst);
585 }
586
587 ++iqInstsAdded;
588
589 count[new_inst->threadNumber]++;
590
591 assert(freeEntries == (numEntries - countInsts()));
592}
593
594template <class Impl>
595void
596InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst)
597{
598 // @todo: Clean up this code; can do it by setting inst as unable
599 // to issue, then calling normal insert on the inst.
600 new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
601
602 assert(new_inst);
603
604 nonSpecInsts[new_inst->seqNum] = new_inst;
605
606 DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s "
607 "to the IQ.\n",
608 new_inst->seqNum, new_inst->pcState());
609
610 assert(freeEntries != 0);
611
612 instList[new_inst->threadNumber].push_back(new_inst);
613
614 --freeEntries;
615
616 new_inst->setInIQ();
617
618 // Have this instruction set itself as the producer of its destination
619 // register(s).
620 addToProducers(new_inst);
621
622 // If it's a memory instruction, add it to the memory dependency
623 // unit.
624 if (new_inst->isMemRef()) {
625 memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst);
626 }
627
628 ++iqNonSpecInstsAdded;
629
630 count[new_inst->threadNumber]++;
631
632 assert(freeEntries == (numEntries - countInsts()));
633}
634
635template <class Impl>
636void
637InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst)
638{
639 memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst);
640
641 insertNonSpec(barr_inst);
642}
643
644template <class Impl>
645typename Impl::DynInstPtr
646InstructionQueue<Impl>::getInstToExecute()
647{
648 assert(!instsToExecute.empty());
649 DynInstPtr inst = instsToExecute.front();
650 instsToExecute.pop_front();
651 if (inst->isFloating()){
652 fpInstQueueReads++;
653 } else {
654 intInstQueueReads++;
655 }
656 return inst;
657}
658
659template <class Impl>
660void
661InstructionQueue<Impl>::addToOrderList(OpClass op_class)
662{
663 assert(!readyInsts[op_class].empty());
664
665 ListOrderEntry queue_entry;
666
667 queue_entry.queueType = op_class;
668
669 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
670
671 ListOrderIt list_it = listOrder.begin();
672 ListOrderIt list_end_it = listOrder.end();
673
674 while (list_it != list_end_it) {
675 if ((*list_it).oldestInst > queue_entry.oldestInst) {
676 break;
677 }
678
679 list_it++;
680 }
681
682 readyIt[op_class] = listOrder.insert(list_it, queue_entry);
683 queueOnList[op_class] = true;
684}
685
686template <class Impl>
687void
688InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it)
689{
690 // Get iterator of next item on the list
691 // Delete the original iterator
692 // Determine if the next item is either the end of the list or younger
693 // than the new instruction. If so, then add in a new iterator right here.
694 // If not, then move along.
695 ListOrderEntry queue_entry;
696 OpClass op_class = (*list_order_it).queueType;
697 ListOrderIt next_it = list_order_it;
698
699 ++next_it;
700
701 queue_entry.queueType = op_class;
702 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
703
704 while (next_it != listOrder.end() &&
705 (*next_it).oldestInst < queue_entry.oldestInst) {
706 ++next_it;
707 }
708
709 readyIt[op_class] = listOrder.insert(next_it, queue_entry);
710}
711
712template <class Impl>
713void
714InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx)
715{
716 DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum);
717 // The CPU could have been sleeping until this op completed (*extremely*
718 // long latency op). Wake it if it was. This may be overkill.
719 if (isSwitchedOut()) {
720 DPRINTF(IQ, "FU completion not processed, IQ is switched out [sn:%lli]\n",
721 inst->seqNum);
722 return;
723 }
724
725 iewStage->wakeCPU();
726
727 if (fu_idx > -1)
728 fuPool->freeUnitNextCycle(fu_idx);
729
730 // @todo: Ensure that these FU Completions happen at the beginning
731 // of a cycle, otherwise they could add too many instructions to
732 // the queue.
733 issueToExecuteQueue->access(-1)->size++;
734 instsToExecute.push_back(inst);
735}
736
737// @todo: Figure out a better way to remove the squashed items from the
738// lists. Checking the top item of each list to see if it's squashed
739// wastes time and forces jumps.
740template <class Impl>
741void
742InstructionQueue<Impl>::scheduleReadyInsts()
743{
744 DPRINTF(IQ, "Attempting to schedule ready instructions from "
745 "the IQ.\n");
746
747 IssueStruct *i2e_info = issueToExecuteQueue->access(0);
748
749 DynInstPtr deferred_mem_inst;
750 int total_deferred_mem_issued = 0;
751 while (total_deferred_mem_issued < totalWidth &&
752 (deferred_mem_inst = getDeferredMemInstToExecute()) != 0) {
753 issueToExecuteQueue->access(0)->size++;
754 instsToExecute.push_back(deferred_mem_inst);
755 total_deferred_mem_issued++;
756 }
757
758 // Have iterator to head of the list
759 // While I haven't exceeded bandwidth or reached the end of the list,
760 // Try to get a FU that can do what this op needs.
761 // If successful, change the oldestInst to the new top of the list, put
762 // the queue in the proper place in the list.
763 // Increment the iterator.
764 // This will avoid trying to schedule a certain op class if there are no
765 // FUs that handle it.
766 ListOrderIt order_it = listOrder.begin();
767 ListOrderIt order_end_it = listOrder.end();
768 int total_issued = 0;
769
770 while (total_issued < (totalWidth - total_deferred_mem_issued) &&
771 iewStage->canIssue() &&
772 order_it != order_end_it) {
773 OpClass op_class = (*order_it).queueType;
774
775 assert(!readyInsts[op_class].empty());
776
777 DynInstPtr issuing_inst = readyInsts[op_class].top();
778
779 issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++;
780
781 assert(issuing_inst->seqNum == (*order_it).oldestInst);
782
783 if (issuing_inst->isSquashed()) {
784 readyInsts[op_class].pop();
785
786 if (!readyInsts[op_class].empty()) {
787 moveToYoungerInst(order_it);
788 } else {
789 readyIt[op_class] = listOrder.end();
790 queueOnList[op_class] = false;
791 }
792
793 listOrder.erase(order_it++);
794
795 ++iqSquashedInstsIssued;
796
797 continue;
798 }
799
800 int idx = -2;
801 int op_latency = 1;
802 ThreadID tid = issuing_inst->threadNumber;
803
804 if (op_class != No_OpClass) {
805 idx = fuPool->getUnit(op_class);
806 issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++;
807 if (idx > -1) {
808 op_latency = fuPool->getOpLatency(op_class);
809 }
810 }
811
812 // If we have an instruction that doesn't require a FU, or a
813 // valid FU, then schedule for execution.
814 if (idx == -2 || idx != -1) {
815 if (op_latency == 1) {
816 i2e_info->size++;
817 instsToExecute.push_back(issuing_inst);
818
819 // Add the FU onto the list of FU's to be freed next
820 // cycle if we used one.
821 if (idx >= 0)
822 fuPool->freeUnitNextCycle(idx);
823 } else {
824 int issue_latency = fuPool->getIssueLatency(op_class);
825 // Generate completion event for the FU
826 FUCompletion *execution = new FUCompletion(issuing_inst,
827 idx, this);
828
829 cpu->schedule(execution, curTick() + cpu->ticks(op_latency - 1));
830
831 // @todo: Enforce that issue_latency == 1 or op_latency
832 if (issue_latency > 1) {
833 // If FU isn't pipelined, then it must be freed
834 // upon the execution completing.
835 execution->setFreeFU();
836 } else {
837 // Add the FU onto the list of FU's to be freed next cycle.
838 fuPool->freeUnitNextCycle(idx);
839 }
840 }
841
842 DPRINTF(IQ, "Thread %i: Issuing instruction PC %s "
843 "[sn:%lli]\n",
844 tid, issuing_inst->pcState(),
845 issuing_inst->seqNum);
846
847 readyInsts[op_class].pop();
848
849 if (!readyInsts[op_class].empty()) {
850 moveToYoungerInst(order_it);
851 } else {
852 readyIt[op_class] = listOrder.end();
853 queueOnList[op_class] = false;
854 }
855
856 issuing_inst->setIssued();
857 ++total_issued;
858
859#if TRACING_ON
860 issuing_inst->issueTick = curTick();
861#endif
862
863 if (!issuing_inst->isMemRef()) {
864 // Memory instructions can not be freed from the IQ until they
865 // complete.
866 ++freeEntries;
867 count[tid]--;
868 issuing_inst->clearInIQ();
869 } else {
870 memDepUnit[tid].issue(issuing_inst);
871 }
872
873 listOrder.erase(order_it++);
874 statIssuedInstType[tid][op_class]++;
875 iewStage->incrWb(issuing_inst->seqNum);
876 } else {
877 statFuBusy[op_class]++;
878 fuBusy[tid]++;
879 ++order_it;
880 }
881 }
882
883 numIssuedDist.sample(total_issued);
884 iqInstsIssued+= total_issued;
885
886 // If we issued any instructions, tell the CPU we had activity.
887 // @todo If the way deferred memory instructions are handeled due to
888 // translation changes then the deferredMemInsts condition should be removed
889 // from the code below.
890 if (total_issued || total_deferred_mem_issued || deferredMemInsts.size()) {
891 cpu->activityThisCycle();
892 } else {
893 DPRINTF(IQ, "Not able to schedule any instructions.\n");
894 }
895}
896
897template <class Impl>
898void
899InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
900{
901 DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready "
902 "to execute.\n", inst);
903
904 NonSpecMapIt inst_it = nonSpecInsts.find(inst);
905
906 assert(inst_it != nonSpecInsts.end());
907
908 ThreadID tid = (*inst_it).second->threadNumber;
909
910 (*inst_it).second->setAtCommit();
911
912 (*inst_it).second->setCanIssue();
913
914 if (!(*inst_it).second->isMemRef()) {
915 addIfReady((*inst_it).second);
916 } else {
917 memDepUnit[tid].nonSpecInstReady((*inst_it).second);
918 }
919
920 (*inst_it).second = NULL;
921
922 nonSpecInsts.erase(inst_it);
923}
924
925template <class Impl>
926void
927InstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid)
928{
929 DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n",
930 tid,inst);
931
932 ListIt iq_it = instList[tid].begin();
933
934 while (iq_it != instList[tid].end() &&
935 (*iq_it)->seqNum <= inst) {
936 ++iq_it;
937 instList[tid].pop_front();
938 }
939
940 assert(freeEntries == (numEntries - countInsts()));
941}
942
943template <class Impl>
944int
945InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
946{
947 int dependents = 0;
948
949 // The instruction queue here takes care of both floating and int ops
950 if (completed_inst->isFloating()) {
951 fpInstQueueWakeupQccesses++;
952 } else {
953 intInstQueueWakeupAccesses++;
954 }
955
956 DPRINTF(IQ, "Waking dependents of completed instruction.\n");
957
958 assert(!completed_inst->isSquashed());
959
960 // Tell the memory dependence unit to wake any dependents on this
961 // instruction if it is a memory instruction. Also complete the memory
962 // instruction at this point since we know it executed without issues.
963 // @todo: Might want to rename "completeMemInst" to something that
964 // indicates that it won't need to be replayed, and call this
965 // earlier. Might not be a big deal.
966 if (completed_inst->isMemRef()) {
967 memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst);
968 completeMemInst(completed_inst);
969 } else if (completed_inst->isMemBarrier() ||
970 completed_inst->isWriteBarrier()) {
971 memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst);
972 }
973
974 for (int dest_reg_idx = 0;
975 dest_reg_idx < completed_inst->numDestRegs();
976 dest_reg_idx++)
977 {
978 PhysRegIndex dest_reg =
979 completed_inst->renamedDestRegIdx(dest_reg_idx);
980
981 // Special case of uniq or control registers. They are not
982 // handled by the IQ and thus have no dependency graph entry.
983 // @todo Figure out a cleaner way to handle this.
984 if (dest_reg >= numPhysRegs) {
985 DPRINTF(IQ, "dest_reg :%d, numPhysRegs: %d\n", dest_reg,
986 numPhysRegs);
987 continue;
988 }
989
990 DPRINTF(IQ, "Waking any dependents on register %i.\n",
991 (int) dest_reg);
992
993 //Go through the dependency chain, marking the registers as
994 //ready within the waiting instructions.
995 DynInstPtr dep_inst = dependGraph.pop(dest_reg);
996
997 while (dep_inst) {
998 DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] "
999 "PC %s.\n", dep_inst->seqNum, dep_inst->pcState());
1000
1001 // Might want to give more information to the instruction
1002 // so that it knows which of its source registers is
1003 // ready. However that would mean that the dependency
1004 // graph entries would need to hold the src_reg_idx.
1005 dep_inst->markSrcRegReady();
1006
1007 addIfReady(dep_inst);
1008
1009 dep_inst = dependGraph.pop(dest_reg);
1010
1011 ++dependents;
1012 }
1013
1014 // Reset the head node now that all of its dependents have
1015 // been woken up.
1016 assert(dependGraph.empty(dest_reg));
1017 dependGraph.clearInst(dest_reg);
1018
1019 // Mark the scoreboard as having that register ready.
1020 regScoreboard[dest_reg] = true;
1021 }
1022 return dependents;
1023}
1024
1025template <class Impl>
1026void
1027InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst)
1028{
1029 OpClass op_class = ready_inst->opClass();
1030
1031 readyInsts[op_class].push(ready_inst);
1032
1033 // Will need to reorder the list if either a queue is not on the list,
1034 // or it has an older instruction than last time.
1035 if (!queueOnList[op_class]) {
1036 addToOrderList(op_class);
1037 } else if (readyInsts[op_class].top()->seqNum <
1038 (*readyIt[op_class]).oldestInst) {
1039 listOrder.erase(readyIt[op_class]);
1040 addToOrderList(op_class);
1041 }
1042
1043 DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1044 "the ready list, PC %s opclass:%i [sn:%lli].\n",
1045 ready_inst->pcState(), op_class, ready_inst->seqNum);
1046}
1047
1048template <class Impl>
1049void
1050InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst)
1051{
1052 DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum);
1053
1054 // Reset DTB translation state
1055 resched_inst->translationStarted = false;
1056 resched_inst->translationCompleted = false;
1057
1058 resched_inst->clearCanIssue();
1059 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
1060}
1061
1062template <class Impl>
1063void
1064InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst)
1065{
1066 memDepUnit[replay_inst->threadNumber].replay(replay_inst);
1067}
1068
1069template <class Impl>
1070void
1071InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst)
1072{
1073 ThreadID tid = completed_inst->threadNumber;
1074
1075 DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n",
1076 completed_inst->pcState(), completed_inst->seqNum);
1077
1078 ++freeEntries;
1079
1080 completed_inst->memOpDone = true;
1081
1082 memDepUnit[tid].completed(completed_inst);
1083 count[tid]--;
1084}
1085
1086template <class Impl>
1087void
1088InstructionQueue<Impl>::deferMemInst(DynInstPtr &deferred_inst)
1089{
1090 deferredMemInsts.push_back(deferred_inst);
1091}
1092
1093template <class Impl>
1094typename Impl::DynInstPtr
1095InstructionQueue<Impl>::getDeferredMemInstToExecute()
1096{
1097 for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end();
1098 ++it) {
1099 if ((*it)->translationCompleted || (*it)->isSquashed()) {
1100 DynInstPtr ret = *it;
1101 deferredMemInsts.erase(it);
1102 return ret;
1103 }
1104 }
1105 return NULL;
1106}
1107
1108template <class Impl>
1109void
1110InstructionQueue<Impl>::violation(DynInstPtr &store,
1111 DynInstPtr &faulting_load)
1112{
1113 intInstQueueWrites++;
1114 memDepUnit[store->threadNumber].violation(store, faulting_load);
1115}
1116
1117template <class Impl>
1118void
1119InstructionQueue<Impl>::squash(ThreadID tid)
1120{
1121 DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in "
1122 "the IQ.\n", tid);
1123
1124 // Read instruction sequence number of last instruction out of the
1125 // time buffer.
1126 squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
1127
1128 // Call doSquash if there are insts in the IQ
1129 if (count[tid] > 0) {
1130 doSquash(tid);
1131 }
1132
1133 // Also tell the memory dependence unit to squash.
1134 memDepUnit[tid].squash(squashedSeqNum[tid], tid);
1135}
1136
1137template <class Impl>
1138void
1139InstructionQueue<Impl>::doSquash(ThreadID tid)
1140{
1141 // Start at the tail.
1142 ListIt squash_it = instList[tid].end();
1143 --squash_it;
1144
1145 DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n",
1146 tid, squashedSeqNum[tid]);
1147
1148 // Squash any instructions younger than the squashed sequence number
1149 // given.
1150 while (squash_it != instList[tid].end() &&
1151 (*squash_it)->seqNum > squashedSeqNum[tid]) {
1152
1153 DynInstPtr squashed_inst = (*squash_it);
1154 squashed_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
1155
1156 // Only handle the instruction if it actually is in the IQ and
1157 // hasn't already been squashed in the IQ.
1158 if (squashed_inst->threadNumber != tid ||
1159 squashed_inst->isSquashedInIQ()) {
1160 --squash_it;
1161 continue;
1162 }
1163
1164 if (!squashed_inst->isIssued() ||
1165 (squashed_inst->isMemRef() &&
1166 !squashed_inst->memOpDone)) {
1167
1168 DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n",
1169 tid, squashed_inst->seqNum, squashed_inst->pcState());
1170
1171 // Remove the instruction from the dependency list.
1172 if (!squashed_inst->isNonSpeculative() &&
1173 !squashed_inst->isStoreConditional() &&
1174 !squashed_inst->isMemBarrier() &&
1175 !squashed_inst->isWriteBarrier()) {
1176
1177 for (int src_reg_idx = 0;
1178 src_reg_idx < squashed_inst->numSrcRegs();
1179 src_reg_idx++)
1180 {
1181 PhysRegIndex src_reg =
1182 squashed_inst->renamedSrcRegIdx(src_reg_idx);
1183
1184 // Only remove it from the dependency graph if it
1185 // was placed there in the first place.
1186
1187 // Instead of doing a linked list traversal, we
1188 // can just remove these squashed instructions
1189 // either at issue time, or when the register is
1190 // overwritten. The only downside to this is it
1191 // leaves more room for error.
1192
1193 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) &&
1194 src_reg < numPhysRegs) {
1195 dependGraph.remove(src_reg, squashed_inst);
1196 }
1197
1198
1199 ++iqSquashedOperandsExamined;
1200 }
1201 } else if (!squashed_inst->isStoreConditional() ||
1202 !squashed_inst->isCompleted()) {
1203 NonSpecMapIt ns_inst_it =
1204 nonSpecInsts.find(squashed_inst->seqNum);
1205
1206 if (ns_inst_it == nonSpecInsts.end()) {
1207 assert(squashed_inst->getFault() != NoFault);
1208 } else {
1209
1210 (*ns_inst_it).second = NULL;
1211
1212 nonSpecInsts.erase(ns_inst_it);
1213
1214 ++iqSquashedNonSpecRemoved;
1215 }
1216 }
1217
1218 // Might want to also clear out the head of the dependency graph.
1219
1220 // Mark it as squashed within the IQ.
1221 squashed_inst->setSquashedInIQ();
1222
1223 // @todo: Remove this hack where several statuses are set so the
1224 // inst will flow through the rest of the pipeline.
1225 squashed_inst->setIssued();
1226 squashed_inst->setCanCommit();
1227 squashed_inst->clearInIQ();
1228
1229 //Update Thread IQ Count
1230 count[squashed_inst->threadNumber]--;
1231
1232 ++freeEntries;
1233 }
1234
1235 instList[tid].erase(squash_it--);
1236 ++iqSquashedInstsExamined;
1237 }
1238}
1239
1240template <class Impl>
1241bool
1242InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst)
1243{
1244 // Loop through the instruction's source registers, adding
1245 // them to the dependency list if they are not ready.
1246 int8_t total_src_regs = new_inst->numSrcRegs();
1247 bool return_val = false;
1248
1249 for (int src_reg_idx = 0;
1250 src_reg_idx < total_src_regs;
1251 src_reg_idx++)
1252 {
1253 // Only add it to the dependency graph if it's not ready.
1254 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) {
1255 PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx);
1256
1257 // Check the IQ's scoreboard to make sure the register
1258 // hasn't become ready while the instruction was in flight
1259 // between stages. Only if it really isn't ready should
1260 // it be added to the dependency graph.
1261 if (src_reg >= numPhysRegs) {
1262 continue;
1263 } else if (regScoreboard[src_reg] == false) {
1264 DPRINTF(IQ, "Instruction PC %s has src reg %i that "
1265 "is being added to the dependency chain.\n",
1266 new_inst->pcState(), src_reg);
1267
1268 dependGraph.insert(src_reg, new_inst);
1269
1270 // Change the return value to indicate that something
1271 // was added to the dependency graph.
1272 return_val = true;
1273 } else {
1274 DPRINTF(IQ, "Instruction PC %s has src reg %i that "
1275 "became ready before it reached the IQ.\n",
1276 new_inst->pcState(), src_reg);
1277 // Mark a register ready within the instruction.
1278 new_inst->markSrcRegReady(src_reg_idx);
1279 }
1280 }
1281 }
1282
1283 return return_val;
1284}
1285
1286template <class Impl>
1287void
1288InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst)
1289{
1290 // Nothing really needs to be marked when an instruction becomes
1291 // the producer of a register's value, but for convenience a ptr
1292 // to the producing instruction will be placed in the head node of
1293 // the dependency links.
1294 int8_t total_dest_regs = new_inst->numDestRegs();
1295
1296 for (int dest_reg_idx = 0;
1297 dest_reg_idx < total_dest_regs;
1298 dest_reg_idx++)
1299 {
1300 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx);
1301
1302 // Instructions that use the misc regs will have a reg number
1303 // higher than the normal physical registers. In this case these
1304 // registers are not renamed, and there is no need to track
1305 // dependencies as these instructions must be executed at commit.
1306 if (dest_reg >= numPhysRegs) {
1307 continue;
1308 }
1309
1310 if (!dependGraph.empty(dest_reg)) {
1311 dependGraph.dump();
1312 panic("Dependency graph %i not empty!", dest_reg);
1313 }
1314
1315 dependGraph.setInst(dest_reg, new_inst);
1316
1317 // Mark the scoreboard to say it's not yet ready.
1318 regScoreboard[dest_reg] = false;
1319 }
1320}
1321
1322template <class Impl>
1323void
1324InstructionQueue<Impl>::addIfReady(DynInstPtr &inst)
1325{
1326 // If the instruction now has all of its source registers
1327 // available, then add it to the list of ready instructions.
1328 if (inst->readyToIssue()) {
1329
1330 //Add the instruction to the proper ready list.
1331 if (inst->isMemRef()) {
1332
1333 DPRINTF(IQ, "Checking if memory instruction can issue.\n");
1334
1335 // Message to the mem dependence unit that this instruction has
1336 // its registers ready.
1337 memDepUnit[inst->threadNumber].regsReady(inst);
1338
1339 return;
1340 }
1341
1342 OpClass op_class = inst->opClass();
1343
1344 DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1345 "the ready list, PC %s opclass:%i [sn:%lli].\n",
1346 inst->pcState(), op_class, inst->seqNum);
1347
1348 readyInsts[op_class].push(inst);
1349
1350 // Will need to reorder the list if either a queue is not on the list,
1351 // or it has an older instruction than last time.
1352 if (!queueOnList[op_class]) {
1353 addToOrderList(op_class);
1354 } else if (readyInsts[op_class].top()->seqNum <
1355 (*readyIt[op_class]).oldestInst) {
1356 listOrder.erase(readyIt[op_class]);
1357 addToOrderList(op_class);
1358 }
1359 }
1360}
1361
1362template <class Impl>
1363int
1364InstructionQueue<Impl>::countInsts()
1365{
1366#if 0
1367 //ksewell:This works but definitely could use a cleaner write
1368 //with a more intuitive way of counting. Right now it's
1369 //just brute force ....
1370 // Change the #if if you want to use this method.
1371 int total_insts = 0;
1372
1373 for (ThreadID tid = 0; tid < numThreads; ++tid) {
1374 ListIt count_it = instList[tid].begin();
1375
1376 while (count_it != instList[tid].end()) {
1377 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) {
1378 if (!(*count_it)->isIssued()) {
1379 ++total_insts;
1380 } else if ((*count_it)->isMemRef() &&
1381 !(*count_it)->memOpDone) {
1382 // Loads that have not been marked as executed still count
1383 // towards the total instructions.
1384 ++total_insts;
1385 }
1386 }
1387
1388 ++count_it;
1389 }
1390 }
1391
1392 return total_insts;
1393#else
1394 return numEntries - freeEntries;
1395#endif
1396}
1397
1398template <class Impl>
1399void
1400InstructionQueue<Impl>::dumpLists()
1401{
1402 for (int i = 0; i < Num_OpClasses; ++i) {
1403 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size());
1404
1405 cprintf("\n");
1406 }
1407
1408 cprintf("Non speculative list size: %i\n", nonSpecInsts.size());
1409
1410 NonSpecMapIt non_spec_it = nonSpecInsts.begin();
1411 NonSpecMapIt non_spec_end_it = nonSpecInsts.end();
1412
1413 cprintf("Non speculative list: ");
1414
1415 while (non_spec_it != non_spec_end_it) {
1416 cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(),
1417 (*non_spec_it).second->seqNum);
1418 ++non_spec_it;
1419 }
1420
1421 cprintf("\n");
1422
1423 ListOrderIt list_order_it = listOrder.begin();
1424 ListOrderIt list_order_end_it = listOrder.end();
1425 int i = 1;
1426
1427 cprintf("List order: ");
1428
1429 while (list_order_it != list_order_end_it) {
1430 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType,
1431 (*list_order_it).oldestInst);
1432
1433 ++list_order_it;
1434 ++i;
1435 }
1436
1437 cprintf("\n");
1438}
1439
1440
1441template <class Impl>
1442void
1443InstructionQueue<Impl>::dumpInsts()
1444{
1445 for (ThreadID tid = 0; tid < numThreads; ++tid) {
1446 int num = 0;
1447 int valid_num = 0;
1448 ListIt inst_list_it = instList[tid].begin();
1449
1450 while (inst_list_it != instList[tid].end()) {
1451 cprintf("Instruction:%i\n", num);
1452 if (!(*inst_list_it)->isSquashed()) {
1453 if (!(*inst_list_it)->isIssued()) {
1454 ++valid_num;
1455 cprintf("Count:%i\n", valid_num);
1456 } else if ((*inst_list_it)->isMemRef() &&
1457 !(*inst_list_it)->memOpDone) {
1458 // Loads that have not been marked as executed
1459 // still count towards the total instructions.
1460 ++valid_num;
1461 cprintf("Count:%i\n", valid_num);
1462 }
1463 }
1464
1465 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n"
1466 "Issued:%i\nSquashed:%i\n",
1467 (*inst_list_it)->pcState(),
1468 (*inst_list_it)->seqNum,
1469 (*inst_list_it)->threadNumber,
1470 (*inst_list_it)->isIssued(),
1471 (*inst_list_it)->isSquashed());
1472
1473 if ((*inst_list_it)->isMemRef()) {
1474 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
1475 }
1476
1477 cprintf("\n");
1478
1479 inst_list_it++;
1480 ++num;
1481 }
1482 }
1483
1484 cprintf("Insts to Execute list:\n");
1485
1486 int num = 0;
1487 int valid_num = 0;
1488 ListIt inst_list_it = instsToExecute.begin();
1489
1490 while (inst_list_it != instsToExecute.end())
1491 {
1492 cprintf("Instruction:%i\n",
1493 num);
1494 if (!(*inst_list_it)->isSquashed()) {
1495 if (!(*inst_list_it)->isIssued()) {
1496 ++valid_num;
1497 cprintf("Count:%i\n", valid_num);
1498 } else if ((*inst_list_it)->isMemRef() &&
1499 !(*inst_list_it)->memOpDone) {
1500 // Loads that have not been marked as executed
1501 // still count towards the total instructions.
1502 ++valid_num;
1503 cprintf("Count:%i\n", valid_num);
1504 }
1505 }
1506
1507 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n"
1508 "Issued:%i\nSquashed:%i\n",
1509 (*inst_list_it)->pcState(),
1510 (*inst_list_it)->seqNum,
1511 (*inst_list_it)->threadNumber,
1512 (*inst_list_it)->isIssued(),
1513 (*inst_list_it)->isSquashed());
1514
1515 if ((*inst_list_it)->isMemRef()) {
1516 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
1517 }
1518
1519 cprintf("\n");
1520
1521 inst_list_it++;
1522 ++num;
1523 }
1524}