| inst_queue.hh (9920:028e4da64b42) | inst_queue.hh (10333:6be8945d226b) |
|---|---|
| 1/* | 1/* |
| 2 * Copyright (c) 2011-2012 ARM Limited | 2 * Copyright (c) 2011-2012, 2014 ARM Limited |
| 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license --- 172 unchanged lines hidden (view full) --- 183 */ 184 void insertBarrier(DynInstPtr &barr_inst); 185 186 /** Returns the oldest scheduled instruction, and removes it from 187 * the list of instructions waiting to execute. 188 */ 189 DynInstPtr getInstToExecute(); 190 | 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license --- 172 unchanged lines hidden (view full) --- 183 */ 184 void insertBarrier(DynInstPtr &barr_inst); 185 186 /** Returns the oldest scheduled instruction, and removes it from 187 * the list of instructions waiting to execute. 188 */ 189 DynInstPtr getInstToExecute(); 190 |
| 191 /** Returns a memory instruction that was referred due to a delayed DTB 192 * translation if it is now ready to execute. | 191 /** Gets a memory instruction that was referred due to a delayed DTB 192 * translation if it is now ready to execute. NULL if none available. |
| 193 */ 194 DynInstPtr getDeferredMemInstToExecute(); 195 | 193 */ 194 DynInstPtr getDeferredMemInstToExecute(); 195 |
| 196 /** Gets a memory instruction that was blocked on the cache. NULL if none 197 * available. 198 */ 199 DynInstPtr getBlockedMemInstToExecute(); 200 |
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| 196 /** 197 * Records the instruction as the producer of a register without 198 * adding it to the rest of the IQ. 199 */ 200 void recordProducer(DynInstPtr &inst) 201 { addToProducers(inst); } 202 203 /** Process FU completion event. */ --- 33 unchanged lines hidden (view full) --- 237 void completeMemInst(DynInstPtr &completed_inst); 238 239 /** 240 * Defers a memory instruction when its DTB translation incurs a hw 241 * page table walk. 242 */ 243 void deferMemInst(DynInstPtr &deferred_inst); 244 | 201 /** 202 * Records the instruction as the producer of a register without 203 * adding it to the rest of the IQ. 204 */ 205 void recordProducer(DynInstPtr &inst) 206 { addToProducers(inst); } 207 208 /** Process FU completion event. */ --- 33 unchanged lines hidden (view full) --- 242 void completeMemInst(DynInstPtr &completed_inst); 243 244 /** 245 * Defers a memory instruction when its DTB translation incurs a hw 246 * page table walk. 247 */ 248 void deferMemInst(DynInstPtr &deferred_inst); 249 |
| 250 /** Defers a memory instruction when it is cache blocked. */ 251 void blockMemInst(DynInstPtr &blocked_inst); 252 253 /** Notify instruction queue that a previous blockage has resolved */ 254 void cacheUnblocked(); 255 |
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| 245 /** Indicates an ordering violation between a store and a load. */ 246 void violation(DynInstPtr &store, DynInstPtr &faulting_load); 247 248 /** 249 * Squashes instructions for a thread. Squashing information is obtained 250 * from the time buffer. 251 */ 252 void squash(ThreadID tid); --- 50 unchanged lines hidden (view full) --- 303 /** List of instructions that are ready to be executed. */ 304 std::list<DynInstPtr> instsToExecute; 305 306 /** List of instructions waiting for their DTB translation to 307 * complete (hw page table walk in progress). 308 */ 309 std::list<DynInstPtr> deferredMemInsts; 310 | 256 /** Indicates an ordering violation between a store and a load. */ 257 void violation(DynInstPtr &store, DynInstPtr &faulting_load); 258 259 /** 260 * Squashes instructions for a thread. Squashing information is obtained 261 * from the time buffer. 262 */ 263 void squash(ThreadID tid); --- 50 unchanged lines hidden (view full) --- 314 /** List of instructions that are ready to be executed. */ 315 std::list<DynInstPtr> instsToExecute; 316 317 /** List of instructions waiting for their DTB translation to 318 * complete (hw page table walk in progress). 319 */ 320 std::list<DynInstPtr> deferredMemInsts; 321 |
| 322 /** List of instructions that have been cache blocked. */ 323 std::list<DynInstPtr> blockedMemInsts; 324 325 /** List of instructions that were cache blocked, but a retry has been seen 326 * since, so they can now be retried. May fail again go on the blocked list. 327 */ 328 std::list<DynInstPtr> retryMemInsts; 329 |
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| 311 /** 312 * Struct for comparing entries to be added to the priority queue. 313 * This gives reverse ordering to the instructions in terms of 314 * sequence numbers: the instructions with smaller sequence 315 * numbers (and hence are older) will be at the top of the 316 * priority queue. 317 */ 318 struct pqCompare { --- 209 unchanged lines hidden --- | 330 /** 331 * Struct for comparing entries to be added to the priority queue. 332 * This gives reverse ordering to the instructions in terms of 333 * sequence numbers: the instructions with smaller sequence 334 * numbers (and hence are older) will be at the top of the 335 * priority queue. 336 */ 337 struct pqCompare { --- 209 unchanged lines hidden --- |